From 0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 17 Aug 2020 08:16:38 +0200 Subject: dts: update to v5.9-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/coresight.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'dts/Bindings/arm/coresight.txt') diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt index 846f6daae7..d711676b4a 100644 --- a/dts/Bindings/arm/coresight.txt +++ b/dts/Bindings/arm/coresight.txt @@ -108,6 +108,13 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. + * qcom,skip-power-up: boolean. Indicates that an implementation can + skip powering up the trace unit. TRCPDCR.PU does not have to be set + on Qualcomm Technologies Inc. systems since ETMs are in the same power + domain as their CPU cores. This property is required to identify such + systems with hardware errata where the CPU watchdog counter is stopped + when TRCPDCR.PU is set. + * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR @@ -121,6 +128,12 @@ its hardware characteristcs. * interrupts : Exactly one SPI may be listed for reporting the address error +* Optional property for configurable replicators: + + * qcom,replicator-loses-context: boolean. Indicates that the replicator + will lose register context when AMBA clock is removed which is observed + in some replicator designs. + Graph bindings for Coresight ------------------------------- -- cgit v1.2.3