From 796af3473b8222bcd89aa63e9886c355a6baf95d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Jun 2019 00:06:30 +0200 Subject: dts: update to v5.2-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt | 2 ++ dts/Bindings/arm/mediatek/mediatek,audsys.txt | 1 + dts/Bindings/arm/mediatek/mediatek,camsys.txt | 22 ++++++++++++ dts/Bindings/arm/mediatek/mediatek,imgsys.txt | 1 + dts/Bindings/arm/mediatek/mediatek,infracfg.txt | 2 ++ dts/Bindings/arm/mediatek/mediatek,ipu.txt | 43 +++++++++++++++++++++++ dts/Bindings/arm/mediatek/mediatek,mcucfg.txt | 1 + dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + dts/Bindings/arm/mediatek/mediatek,mmsys.txt | 1 + dts/Bindings/arm/mediatek/mediatek,topckgen.txt | 2 ++ dts/Bindings/arm/mediatek/mediatek,vdecsys.txt | 1 + dts/Bindings/arm/mediatek/mediatek,vencsys.txt | 1 + 12 files changed, 78 insertions(+) create mode 100644 dts/Bindings/arm/mediatek/mediatek,camsys.txt create mode 100644 dts/Bindings/arm/mediatek/mediatek,ipu.txt (limited to 'dts/Bindings/arm/mediatek') diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt index de4075413d..161e63a6c2 100644 --- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -14,6 +14,8 @@ Required Properties: - "mediatek,mt7629-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" + - "mediatek,mt8183-apmixedsys", "syscon" + - "mediatek,mt8516-apmixedsys" - #clock-cells: Must be 1 The apmixedsys controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt index d1606b2c3e..f3cef1a6d9 100644 --- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,audsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-audsys", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt8183-audiosys", "syscon" - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,camsys.txt b/dts/Bindings/arm/mediatek/mediatek,camsys.txt new file mode 100644 index 0000000000..d8930f64aa --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,camsys.txt @@ -0,0 +1,22 @@ +MediaTek CAMSYS controller +============================ + +The MediaTek camsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt8183-camsys", "syscon" +- #clock-cells: Must be 1 + +The camsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +camsys: camsys@1a000000 { + compatible = "mediatek,mt8183-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt index 3f99672163..e3bc4a1e7a 100644 --- a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" + - "mediatek,mt8183-imgsys", "syscon" - #clock-cells: Must be 1 The imgsys controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt index 417bd83d13..a90913988d 100644 --- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt +++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt @@ -15,6 +15,8 @@ Required Properties: - "mediatek,mt7629-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" + - "mediatek,mt8183-infracfg", "syscon" + - "mediatek,mt8516-infracfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/dts/Bindings/arm/mediatek/mediatek,ipu.txt b/dts/Bindings/arm/mediatek/mediatek,ipu.txt new file mode 100644 index 0000000000..aabc8c5c8e --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,ipu.txt @@ -0,0 +1,43 @@ +Mediatek IPU controller +============================ + +The Mediatek ipu controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt8183-ipu_conn", "syscon" + - "mediatek,mt8183-ipu_adl", "syscon" + - "mediatek,mt8183-ipu_core0", "syscon" + - "mediatek,mt8183-ipu_core1", "syscon" +- #clock-cells: Must be 1 + +The ipu controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +ipu_conn: syscon@19000000 { + compatible = "mediatek,mt8183-ipu_conn", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_adl: syscon@19010000 { + compatible = "mediatek,mt8183-ipu_adl", "syscon"; + reg = <0 0x19010000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_core0: syscon@19180000 { + compatible = "mediatek,mt8183-ipu_core0", "syscon"; + reg = <0 0x19180000 0 0x1000>; + #clock-cells = <1>; +}; + +ipu_core1: syscon@19280000 { + compatible = "mediatek,mt8183-ipu_core1", "syscon"; + reg = <0 0x19280000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/dts/Bindings/arm/mediatek/mediatek,mcucfg.txt b/dts/Bindings/arm/mediatek/mediatek,mcucfg.txt index b8fb03f361..2b882b7ca7 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mcucfg.txt +++ b/dts/Bindings/arm/mediatek/mediatek,mcucfg.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-mcucfg", "syscon" + - "mediatek,mt8183-mcucfg", "syscon" - #clock-cells: Must be 1 The mcucfg controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt b/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt index 859e67b416..72787e7dd2 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt +++ b/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2712-mfgcfg", "syscon" + - "mediatek,mt8183-mfgcfg", "syscon" - #clock-cells: Must be 1 The mfgcfg controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt index 15d977afad..545eab717c 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" + - "mediatek,mt8183-mmsys", "syscon" - #clock-cells: Must be 1 The mmsys controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt index d160c2b4b6..a023b83389 100644 --- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt +++ b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt @@ -14,6 +14,8 @@ Required Properties: - "mediatek,mt7629-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" + - "mediatek,mt8183-topckgen", "syscon" + - "mediatek,mt8516-topckgen" - #clock-cells: Must be 1 The topckgen controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt index 3212afc753..57176bb8db 100644 --- a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-vdecsys", "syscon" - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon" + - "mediatek,mt8183-vdecsys", "syscon" - #clock-cells: Must be 1 The vdecsys controller uses the common clk binding from diff --git a/dts/Bindings/arm/mediatek/mediatek,vencsys.txt b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt index 851545357e..c9faa62690 100644 --- a/dts/Bindings/arm/mediatek/mediatek,vencsys.txt +++ b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2712-vencsys", "syscon" - "mediatek,mt6797-vencsys", "syscon" - "mediatek,mt8173-vencsys", "syscon" + - "mediatek,mt8183-vencsys", "syscon" - #clock-cells: Must be 1 The vencsys controller uses the common clk binding from -- cgit v1.2.3