From ab001302c8e1718110bb8839c270d2caa817b214 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 9 Feb 2015 08:45:25 +0100 Subject: dts: update to v3.19-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/mediatek/mediatek,sysirq.txt | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 dts/Bindings/arm/mediatek/mediatek,sysirq.txt (limited to 'dts/Bindings/arm/mediatek') diff --git a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt b/dts/Bindings/arm/mediatek/mediatek,sysirq.txt new file mode 100644 index 0000000000..d680b07ec6 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,sysirq.txt @@ -0,0 +1,28 @@ +Mediatek 65xx/81xx sysirq + +Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI +interrupt. + +Required properties: +- compatible: should be one of: + "mediatek,mt8135-sysirq" + "mediatek,mt8127-sysirq" + "mediatek,mt6589-sysirq" + "mediatek,mt6582-sysirq" + "mediatek,mt6577-sysirq" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Use the same format as specified by GIC in + Documentation/devicetree/bindings/arm/gic.txt +- interrupt-parent: phandle of irq parent for sysirq. The parent must + use the same interrupt-cells format as GIC. +- reg: Physical base address of the intpol registers and length of memory + mapped region. + +Example: + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200100 0 0x1c>; + }; -- cgit v1.2.3