From 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Sep 2018 08:26:30 +0200 Subject: dts: update to v4.19-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 dts/Bindings/arm/msm/qcom,llcc.txt (limited to 'dts/Bindings/arm/msm') diff --git a/dts/Bindings/arm/msm/qcom,llcc.txt b/dts/Bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000000..5e85749262 --- /dev/null +++ b/dts/Bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: Start address and the the size of the register region. + +Example: + + cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + }; -- cgit v1.2.3