From 6940ba22c66ac1c713500027bf5f6832442a1410 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 19 Aug 2019 08:56:20 +0200 Subject: dts: update to v5.3-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/stm32/mlahb.txt | 37 +++++++++++++++++++++++++++++++++++++ dts/Bindings/arm/stm32/stm32.txt | 10 ---------- dts/Bindings/arm/stm32/stm32.yaml | 31 +++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+), 10 deletions(-) create mode 100644 dts/Bindings/arm/stm32/mlahb.txt delete mode 100644 dts/Bindings/arm/stm32/stm32.txt create mode 100644 dts/Bindings/arm/stm32/stm32.yaml (limited to 'dts/Bindings/arm/stm32') diff --git a/dts/Bindings/arm/stm32/mlahb.txt b/dts/Bindings/arm/stm32/mlahb.txt new file mode 100644 index 0000000000..25307aa1eb --- /dev/null +++ b/dts/Bindings/arm/stm32/mlahb.txt @@ -0,0 +1,37 @@ +ML-AHB interconnect bindings + +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects +a Cortex-M subsystem with dedicated memories. +The MCU SRAM and RETRAM memory parts can be accessed through different addresses +(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the +Cortex-M firmware accesses among those ports allows to tune the system +performance. + +[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf +[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +Required properties: +- compatible: should be "simple-bus" +- dma-ranges: describes memory addresses translation between the local CPU and + the remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + +The Cortex-M remote processor accessed via the mlahb interconnect is described +by a child node. + +Example: +mlahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@10000000 { + ... + }; +}; diff --git a/dts/Bindings/arm/stm32/stm32.txt b/dts/Bindings/arm/stm32/stm32.txt deleted file mode 100644 index 6808ed9ddf..0000000000 --- a/dts/Bindings/arm/stm32/stm32.txt +++ /dev/null @@ -1,10 +0,0 @@ -STMicroelectronics STM32 Platforms Device Tree Bindings - -Each device tree must specify which STM32 SoC it uses, -using one of the following compatible strings: - - st,stm32f429 - st,stm32f469 - st,stm32f746 - st,stm32h743 - st,stm32mp157 diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml new file mode 100644 index 0000000000..4d194f1eb0 --- /dev/null +++ b/dts/Bindings/arm/stm32/stm32.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/stm32/stm32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Platforms Device Tree Bindings + +maintainers: + - Alexandre Torgue + +properties: + compatible: + oneOf: + - items: + - const: st,stm32f429 + + - items: + - const: st,stm32f469 + + - items: + - const: st,stm32f746 + + - items: + - const: st,stm32h743 + + - items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: st,stm32mp157 +... -- cgit v1.2.3