From 9313920df6d3d55fbd03ce8ec1c0da9a10c29824 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 17 Jun 2014 22:16:07 +0200 Subject: dts: update to v3.16-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arm/altera/socfpga-reset.txt | 11 ---- dts/Bindings/arm/armada-370-xp-mpic.txt | 38 ----------- dts/Bindings/arm/armada-370-xp-pmsu.txt | 19 +++--- dts/Bindings/arm/armada-cpu-reset.txt | 14 ++++ dts/Bindings/arm/axxia.txt | 12 ++++ dts/Bindings/arm/coherency-fabric.txt | 32 ++++++++-- dts/Bindings/arm/cpus.txt | 8 ++- dts/Bindings/arm/exynos/smp-sysram.txt | 38 +++++++++++ dts/Bindings/arm/global_timer.txt | 7 +- dts/Bindings/arm/marvell,berlin.txt | 102 ++++++++++++++++++++++++++++++ dts/Bindings/arm/omap/l3-noc.txt | 2 + dts/Bindings/arm/omap/omap.txt | 18 +++++- dts/Bindings/arm/pmu.txt | 1 + dts/Bindings/arm/psci.txt | 37 ++++++++++- dts/Bindings/arm/rockchip.txt | 10 +++ dts/Bindings/arm/samsung/pmu.txt | 4 ++ dts/Bindings/arm/samsung/sysreg.txt | 11 +++- dts/Bindings/arm/sti.txt | 15 +++++ dts/Bindings/arm/vexpress-sysreg.txt | 79 +++++++++++++++++++---- dts/Bindings/arm/vexpress.txt | 15 +++-- 20 files changed, 383 insertions(+), 90 deletions(-) delete mode 100644 dts/Bindings/arm/altera/socfpga-reset.txt delete mode 100644 dts/Bindings/arm/armada-370-xp-mpic.txt create mode 100644 dts/Bindings/arm/armada-cpu-reset.txt create mode 100644 dts/Bindings/arm/axxia.txt create mode 100644 dts/Bindings/arm/exynos/smp-sysram.txt create mode 100644 dts/Bindings/arm/rockchip.txt create mode 100644 dts/Bindings/arm/sti.txt (limited to 'dts/Bindings/arm') diff --git a/dts/Bindings/arm/altera/socfpga-reset.txt b/dts/Bindings/arm/altera/socfpga-reset.txt deleted file mode 100644 index ecdb57d69d..0000000000 --- a/dts/Bindings/arm/altera/socfpga-reset.txt +++ /dev/null @@ -1,11 +0,0 @@ -Altera SOCFPGA Reset Manager - -Required properties: -- compatible : "altr,rst-mgr" -- reg : Should contain 1 register ranges(address and length) - -Example: - rstmgr@ffd05000 { - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; diff --git a/dts/Bindings/arm/armada-370-xp-mpic.txt b/dts/Bindings/arm/armada-370-xp-mpic.txt deleted file mode 100644 index 5fc03134a9..0000000000 --- a/dts/Bindings/arm/armada-370-xp-mpic.txt +++ /dev/null @@ -1,38 +0,0 @@ -Marvell Armada 370, 375, 38x, XP Interrupt Controller ------------------------------------------------------ - -Required properties: -- compatible: Should be "marvell,mpic" -- interrupt-controller: Identifies the node as an interrupt controller. -- msi-controller: Identifies the node as an PCI Message Signaled - Interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. Should be 1. - The cell is the IRQ number - -- reg: Should contain PMIC registers location and length. First pair - for the main interrupt registers, second pair for the per-CPU - interrupt registers. For this last pair, to be compliant with SMP - support, the "virtual" must be use (For the record, these registers - automatically map to the interrupt controller registers of the - current CPU) - -Optional properties: - -- interrupts: If defined, then it indicates that this MPIC is - connected as a slave to another interrupt controller. This is - typically the case on Armada 375 and Armada 38x, where the MPIC is - connected as a slave to the Cortex-A9 GIC. The provided interrupt - indicate to which GIC interrupt the MPIC output is connected. - -Example: - - mpic: interrupt-controller@d0020000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; - reg = <0xd0020a00 0x1d0>, - <0xd0021070 0x58>; - }; diff --git a/dts/Bindings/arm/armada-370-xp-pmsu.txt b/dts/Bindings/arm/armada-370-xp-pmsu.txt index 926b4d6aae..26799ef562 100644 --- a/dts/Bindings/arm/armada-370-xp-pmsu.txt +++ b/dts/Bindings/arm/armada-370-xp-pmsu.txt @@ -1,20 +1,21 @@ Power Management Service Unit(PMSU) ----------------------------------- -Available on Marvell SOCs: Armada 370 and Armada XP +Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP Required properties: -- compatible: "marvell,armada-370-xp-pmsu" +- compatible: should be one of: + - "marvell,armada-370-pmsu" for Armada 370 or Armada XP + - "marvell,armada-380-pmsu" for Armada 38x + - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now + deprecated and will be removed -- reg: Should contain PMSU registers location and length. First pair - for the per-CPU SW Reset Control registers, second pair for the - Power Management Service Unit. +- reg: Should contain PMSU registers location and length. Example: -armada-370-xp-pmsu@d0022000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0xd0022100 0x430>, - <0xd0020800 0x20>; +armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; }; diff --git a/dts/Bindings/arm/armada-cpu-reset.txt b/dts/Bindings/arm/armada-cpu-reset.txt new file mode 100644 index 0000000000..b63a7b6ab9 --- /dev/null +++ b/dts/Bindings/arm/armada-cpu-reset.txt @@ -0,0 +1,14 @@ +Marvell Armada CPU reset controller +=================================== + +Required properties: + +- compatible: Should be "marvell,armada-370-cpu-reset". + +- reg: should be register base and length as documented in the + datasheet for the CPU reset registers + +cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; +}; diff --git a/dts/Bindings/arm/axxia.txt b/dts/Bindings/arm/axxia.txt new file mode 100644 index 0000000000..7b4ef9c076 --- /dev/null +++ b/dts/Bindings/arm/axxia.txt @@ -0,0 +1,12 @@ +Axxia AXM55xx device tree bindings + +Boards using the AXM55xx SoC need to have the following properties: + +Required root node property: + + - compatible = "lsi,axm5516" + +Boards: + + LSI AXM5516 Validation board (Amarillo) + compatible = "lsi,axm5516-amarillo", "lsi,axm5516" diff --git a/dts/Bindings/arm/coherency-fabric.txt b/dts/Bindings/arm/coherency-fabric.txt index 17d8cd1075..8dd46617c8 100644 --- a/dts/Bindings/arm/coherency-fabric.txt +++ b/dts/Bindings/arm/coherency-fabric.txt @@ -1,16 +1,33 @@ Coherency fabric ---------------- -Available on Marvell SOCs: Armada 370 and Armada XP +Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP Required properties: -- compatible: "marvell,coherency-fabric" +- compatible: the possible values are: + + * "marvell,coherency-fabric", to be used for the coherency fabric of + the Armada 370 and Armada XP. + + * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency + fabric. + + * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency + fabric. - reg: Should contain coherency fabric registers location and - length. First pair for the coherency fabric registers, second pair - for the per-CPU fabric registers registers. + length. + + * For "marvell,coherency-fabric", the first pair for the coherency + fabric registers, second pair for the per-CPU fabric registers. -Example: + * For "marvell,armada-375-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. + + * For "marvell,armada-380-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. + +Examples: coherency-fabric@d0020200 { compatible = "marvell,coherency-fabric"; @@ -19,3 +36,8 @@ coherency-fabric@d0020200 { }; +coherency-fabric@21810 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21810 0x1c>; +}; + diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt index 333f4aea30..1fe72a0778 100644 --- a/dts/Bindings/arm/cpus.txt +++ b/dts/Bindings/arm/cpus.txt @@ -178,13 +178,19 @@ nodes to be present and contain the properties described below. Usage and definition depend on ARM architecture version. # On ARM v8 64-bit this property is required and must be one of: - "spin-table" "psci" + "spin-table" # On ARM 32-bit systems this property is optional and can be one of: + "allwinner,sun6i-a31" + "arm,psci" + "marvell,armada-375-smp" + "marvell,armada-380-smp" + "marvell,armada-xp-smp" "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3066-smp" - cpu-release-addr Usage: required for systems that have an "enable-method" diff --git a/dts/Bindings/arm/exynos/smp-sysram.txt b/dts/Bindings/arm/exynos/smp-sysram.txt new file mode 100644 index 0000000000..4a0a4f70a0 --- /dev/null +++ b/dts/Bindings/arm/exynos/smp-sysram.txt @@ -0,0 +1,38 @@ +Samsung Exynos SYSRAM for SMP bringup: +------------------------------------ + +Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup +of the secondary cores. Once the core gets powered up it executes the +code that is residing at some specific location of the SYSRAM. + +Therefore reserved section sub-nodes have to be added to the mmio-sram +declaration. These nodes are of two types depending upon secure or +non-secure execution environment. + +Required sub-node properties: +- compatible : depending upon boot mode, should be + "samsung,exynos4210-sysram" : for Secure SYSRAM + "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sysram.txt + +Example: + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; diff --git a/dts/Bindings/arm/global_timer.txt b/dts/Bindings/arm/global_timer.txt index 1e548981ed..bdae3a8187 100644 --- a/dts/Bindings/arm/global_timer.txt +++ b/dts/Bindings/arm/global_timer.txt @@ -4,8 +4,11 @@ ** Timer node required properties: -- compatible : Should be "arm,cortex-a9-global-timer" - Driver supports versions r2p0 and above. +- compatible : should contain + * "arm,cortex-a5-global-timer" for Cortex-A5 global timers. + * "arm,cortex-a9-global-timer" for Cortex-A9 global + timers or any compatible implementation. Note: driver + supports versions r2p0 and above. - interrupts : One interrupt to each core diff --git a/dts/Bindings/arm/marvell,berlin.txt b/dts/Bindings/arm/marvell,berlin.txt index 737afa5f81..94013a9a87 100644 --- a/dts/Bindings/arm/marvell,berlin.txt +++ b/dts/Bindings/arm/marvell,berlin.txt @@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are: "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) * Example: @@ -22,3 +23,104 @@ SoC and board used. Currently known SoC compatibles are: ... } + +* Marvell Berlin2 chip control binding + +Marvell Berlin SoCs have a chip control register set providing several +individual registers dealing with pinmux, padmux, clock, reset, and secondary +CPU boot address. Unfortunately, the individual registers are spread among the +chip control registers, so there should be a single DT node only providing the +different functions which are described below. + +Required properties: +- compatible: shall be one of + "marvell,berlin2-chip-ctrl" for BG2 + "marvell,berlin2cd-chip-ctrl" for BG2CD + "marvell,berlin2q-chip-ctrl" for BG2Q +- reg: address and length of following register sets for + BG2/BG2CD: chip control register set + BG2Q: chip control register set and cpu pll registers + +* Marvell Berlin2 system control binding + +Marvell Berlin SoCs have a system control register set providing several +individual registers dealing with pinmux, padmux, and reset. + +Required properties: +- compatible: should be one of + "marvell,berlin2-system-ctrl" for BG2 + "marvell,berlin2cd-system-ctrl" for BG2CD + "marvell,berlin2q-system-ctrl" for BG2Q +- reg: address and length of the system control register set + +* Clock provider binding + +As clock related registers are spread among the chip control registers, the +chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q) +SoCs share the same IP for PLLs and clocks, with some minor differences in +features and register layout. + +Required properties: +- #clock-cells: shall be set to 1 +- clocks: clock specifiers referencing the core clock input clocks +- clock-names: array of strings describing the input clock specifiers above. + Allowed clock-names for the reference clocks are + "refclk" for the SoCs osciallator input on all SoCs, + and SoC-specific input clocks for + BG2/BG2CD: "video_ext0" for the external video clock input + +Clocks provided by core clocks shall be referenced by a clock specifier +indexing one of the provided clocks. Refer to dt-bindings/clock/berlin.h +for the corresponding index mapping. + +* Pin controller binding + +Pin control registers are part of both register sets, chip control and system +control. The pins controlled are organized in groups, so no actual pin +information is needed. + +A pin-controller node should contain subnodes representing the pin group +configurations, one per function. Each subnode has the group name and the muxing +function used. + +Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called +a 'function' in the pin-controller subsystem. + +Required subnode-properties: +- groups: a list of strings describing the group names. +- function: a string describing the function used to mux the groups. + +Example: + +chip: chip-control@ea0000 { + compatible = "marvell,berlin2-chip-ctrl"; + #clock-cells = <1>; + reg = <0xea0000 0x400>; + clocks = <&refclk>, <&externaldev 0>; + clock-names = "refclk", "video_ext0"; + + spi1_pmux: spi1-pmux { + groups = "G0"; + function = "spi1"; + }; +}; + +sysctrl: system-controller@d000 { + compatible = "marvell,berlin2-system-ctrl"; + reg = <0xd000 0x100>; + + uart0_pmux: uart0-pmux { + groups = "GSM4"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM5"; + function = "uart1"; + }; + + uart2_pmux: uart2-pmux { + groups = "GSM3"; + function = "uart2"; + }; +}; diff --git a/dts/Bindings/arm/omap/l3-noc.txt b/dts/Bindings/arm/omap/l3-noc.txt index c0105de55c..974624ea68 100644 --- a/dts/Bindings/arm/omap/l3-noc.txt +++ b/dts/Bindings/arm/omap/l3-noc.txt @@ -6,6 +6,8 @@ provided by Arteris. Required properties: - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family Should be "ti,omap4-l3-noc" for OMAP4 family + Should be "ti,dra7-l3-noc" for DRA7 family + Should be "ti,am4372-l3-noc" for AM43 family - reg: Contains L3 register address range for each noc domain. - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt index 36ede19a16..d22b216f5d 100644 --- a/dts/Bindings/arm/omap/omap.txt +++ b/dts/Bindings/arm/omap/omap.txt @@ -80,7 +80,10 @@ SoCs: compatible = "ti,omap5432", "ti,omap5" - DRA742 - compatible = "ti,dra7xx", "ti,dra7" + compatible = "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 + compatible = "ti,dra722", "ti,dra72", "ti,dra7" - AM4372 compatible = "ti,am4372", "ti,am43" @@ -102,6 +105,12 @@ Boards: - OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; +- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN + compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + +- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen + compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x compatible = "ti,omap3-evm", "ti,omap3" @@ -120,5 +129,8 @@ Boards: - AM437x GP EVM compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" -- DRA7 EVM: Software Developement Board for DRA7XX - compatible = "ti,dra7-evm", "ti,dra7" +- DRA742 EVM: Software Development Board for DRA742 + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 EVM: Software Development Board for DRA722 + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt index fe5cef8976..75ef91d08f 100644 --- a/dts/Bindings/arm/pmu.txt +++ b/dts/Bindings/arm/pmu.txt @@ -8,6 +8,7 @@ Required properties: - compatible : should be one of "arm,armv8-pmuv3" + "arm,cortex-a17-pmu" "arm,cortex-a15-pmu" "arm,cortex-a12-pmu" "arm,cortex-a9-pmu" diff --git a/dts/Bindings/arm/psci.txt b/dts/Bindings/arm/psci.txt index 433afe9cb5..b4a58f3922 100644 --- a/dts/Bindings/arm/psci.txt +++ b/dts/Bindings/arm/psci.txt @@ -21,7 +21,15 @@ to #0. Main node required properties: - - compatible : Must be "arm,psci" + - compatible : should contain at least one of: + + * "arm,psci" : for implementations complying to PSCI versions prior to + 0.2. For these cases function IDs must be provided. + + * "arm,psci-0.2" : for implementations complying to PSCI 0.2. Function + IDs are not required and should be ignored by an OS with PSCI 0.2 + support, but are permitted to be present for compatibility with + existing software when "arm,psci" is later in the compatible list. - method : The method of calling the PSCI firmware. Permitted values are: @@ -45,6 +53,8 @@ Main node optional properties: Example: +Case 1: PSCI v0.1 only. + psci { compatible = "arm,psci"; method = "smc"; @@ -53,3 +63,28 @@ Example: cpu_on = <0x95c10002>; migrate = <0x95c10003>; }; + + +Case 2: PSCI v0.2 only + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Case 3: PSCI v0.2 and PSCI v0.1. + + A DTB may provide IDs for use by kernels without PSCI 0.2 support, + enabling firmware and hypervisors to support existing and new kernels. + These IDs will be ignored by kernels with PSCI 0.2 support, which will + use the standard PSCI 0.2 IDs exclusively. + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "hvc"; + + cpu_on = < arbitrary value >; + cpu_off = < arbitrary value >; + + ... + }; diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt new file mode 100644 index 0000000000..857f12636e --- /dev/null +++ b/dts/Bindings/arm/rockchip.txt @@ -0,0 +1,10 @@ +Rockchip platforms device tree bindings +--------------------------------------- + +- bq Curie 2 tablet: + Required root node properties: + - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; + +- Radxa Rock board: + Required root node properties: + - compatible = "radxa,rock", "rockchip,rk3188"; diff --git a/dts/Bindings/arm/samsung/pmu.txt b/dts/Bindings/arm/samsung/pmu.txt index f1f155255f..2a4ab046a8 100644 --- a/dts/Bindings/arm/samsung/pmu.txt +++ b/dts/Bindings/arm/samsung/pmu.txt @@ -2,6 +2,10 @@ SAMSUNG Exynos SoC series PMU Registers Properties: - compatible : should contain two values. First value must be one from following list: + - "samsung,exynos3250-pmu" - for Exynos3250 SoC, + - "samsung,exynos4210-pmu" - for Exynos4210 SoC, + - "samsung,exynos4212-pmu" - for Exynos4212 SoC, + - "samsung,exynos4412-pmu" - for Exynos4412 SoC, - "samsung,exynos5250-pmu" - for Exynos5250 SoC, - "samsung,exynos5420-pmu" - for Exynos5420 SoC. second value must be always "syscon". diff --git a/dts/Bindings/arm/samsung/sysreg.txt b/dts/Bindings/arm/samsung/sysreg.txt index 0ab3251a6e..4fced6e9d5 100644 --- a/dts/Bindings/arm/samsung/sysreg.txt +++ b/dts/Bindings/arm/samsung/sysreg.txt @@ -1,8 +1,10 @@ SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) Properties: - - compatible : should contain "samsung,-sysreg", "syscon"; - For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon"; + - compatible : should contain two values. First value must be one from following list: + - "samsung,exynos4-sysreg" - for Exynos4 based SoCs, + - "samsung,exynos5-sysreg" - for Exynos5 based SoCs. + second value must be always "syscon". - reg : offset and length of the register set. Example: @@ -10,3 +12,8 @@ Example: compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; }; + + syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; diff --git a/dts/Bindings/arm/sti.txt b/dts/Bindings/arm/sti.txt new file mode 100644 index 0000000000..92f16c78bb --- /dev/null +++ b/dts/Bindings/arm/sti.txt @@ -0,0 +1,15 @@ +ST STi Platforms Device Tree Bindings +--------------------------------------- + +Boards with the ST STiH415 SoC shall have the following properties: +Required root node property: +compatible = "st,stih415"; + +Boards with the ST STiH416 SoC shall have the following properties: +Required root node property: +compatible = "st,stih416"; + +Boards with the ST STiH407 SoC shall have the following properties: +Required root node property: +compatible = "st,stih407"; + diff --git a/dts/Bindings/arm/vexpress-sysreg.txt b/dts/Bindings/arm/vexpress-sysreg.txt index 5580e9c4bd..00318d083c 100644 --- a/dts/Bindings/arm/vexpress-sysreg.txt +++ b/dts/Bindings/arm/vexpress-sysreg.txt @@ -8,6 +8,8 @@ interrupt generation, MMC and NOR Flash control etc. Required node properties: - compatible value : = "arm,vexpress,sysreg"; - reg : physical base address and the size of the registers window + +Deprecated properties, replaced by GPIO subnodes (see below): - gpio-controller : specifies that the node is a GPIO controller - #gpio-cells : size of the GPIO specifier, should be 2: - first cell is the pseudo-GPIO line number: @@ -16,35 +18,86 @@ Required node properties: 2 - NOR FLASH WPn - second cell can take standard GPIO flags (currently ignored). +Control registers providing pseudo-GPIO lines must be represented +by subnodes, each of them requiring the following properties: +- compatible value : one of + "arm,vexpress-sysreg,sys_led" + "arm,vexpress-sysreg,sys_mci" + "arm,vexpress-sysreg,sys_flash" +- gpio-controller : makes the node a GPIO controller +- #gpio-cells : size of the GPIO specifier, must be 2: + - first cell is the function number: + - for sys_led : 0..7 = LED 0..7 + - for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT + - for sys_flash : 0 = NOR FLASH WPn + - second cell can take standard GPIO flags (currently ignored). + Example: v2m_sysreg: sysreg@10000000 { compatible = "arm,vexpress-sysreg"; reg = <0x10000000 0x1000>; - gpio-controller; - #gpio-cells = <2>; + + v2m_led_gpios: sys_led@08 { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; }; This block also can also act a bridge to the platform's configuration bus via "system control" interface, addressing devices with site number, position in the board stack, config controller, function and device -numbers - see motherboard's TRM for more details. - -The node describing a config device must refer to the sysreg node via -"arm,vexpress,config-bridge" phandle (can be also defined in the node's -parent) and relies on the board topology properties - see main vexpress -node documentation for more details. It must also define the following -property: -- arm,vexpress-sysreg,func : must contain two cells: - - first cell defines function number (eg. 1 for clock generator, - 2 for voltage regulators etc.) - - device number (eg. osc 0, osc 1 etc.) +numbers - see motherboard's TRM for more details. All configuration +controller accessible via this interface must reference the sysreg +node via "arm,vexpress,config-bridge" phandle and define appropriate +topology properties - see main vexpress node documentation for more +details. Each child of such node describes one function and must +define the following properties: +- compatible value : must be one of (corresponding to the TRM): + "arm,vexpress-amp" + "arm,vexpress-dvimode" + "arm,vexpress-energy" + "arm,vexpress-muxfpga" + "arm,vexpress-osc" + "arm,vexpress-power" + "arm,vexpress-reboot" + "arm,vexpress-reset" + "arm,vexpress-scc" + "arm,vexpress-shutdown" + "arm,vexpress-temp" + "arm,vexpress-volt" +- arm,vexpress-sysreg,func : must contain a set of two cells long groups: + - first cell of each group defines the function number + (eg. 1 for clock generator, 2 for voltage regulators etc.) + - second cell of each group defines device number (eg. osc 0, + osc 1 etc.) + - some functions (eg. energy meter, with its 64 bit long counter) + are using more than one function/device number pair Example: mcc { + compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; osc@0 { compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; }; + + energy@0 { + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>, <13 1>; + }; }; diff --git a/dts/Bindings/arm/vexpress.txt b/dts/Bindings/arm/vexpress.txt index ae49161e47..39844cd0bc 100644 --- a/dts/Bindings/arm/vexpress.txt +++ b/dts/Bindings/arm/vexpress.txt @@ -80,12 +80,17 @@ but also control clock generators, voltage regulators, gather environmental data like temperature, power consumption etc. Even the video output switch (FPGA) is controlled that way. -Nodes describing devices controlled by this infrastructure should -point at the bridge device node: +The controllers are not mapped into normal memory address space +and must be accessed through bridges - other devices capable +of generating transactions on the configuration bus. + +The nodes describing configuration controllers must define +the following properties: +- compatible value: + compatible = "arm,vexpress,config-bus"; - bridge phandle: arm,vexpress,config-bridge = ; -This property can be also defined in a parent node (eg. for a DCC) -and is effective for all children. +and children describing available functions. Platform topology @@ -197,7 +202,7 @@ Example of a VE tile description (simplified) }; dcc { - compatible = "simple-bus"; + compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; osc@0 { -- cgit v1.2.3