From 6e6cb6c407a220b61d66e957713a919f4afbc54a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 13 Jun 2016 07:30:56 +0200 Subject: dts: update to v4.6-rc3 Signed-off-by: Sascha Hauer --- dts/Bindings/clock/qca,ath79-pll.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'dts/Bindings/clock/qca,ath79-pll.txt') diff --git a/dts/Bindings/clock/qca,ath79-pll.txt b/dts/Bindings/clock/qca,ath79-pll.txt index e0fc2c11dd..241fb0545b 100644 --- a/dts/Bindings/clock/qca,ath79-pll.txt +++ b/dts/Bindings/clock/qca,ath79-pll.txt @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. Required Properties: -- compatible: has to be "qca,-cpu-intc" and one of the following +- compatible: has to be "qca,-pll" and one of the following fallbacks: - "qca,ar7100-pll" - "qca,ar7240-pll" @@ -21,8 +21,8 @@ Optional properties: Example: - memory-controller@18050000 { - compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; + pll-controller@18050000 { + compatible = "qca,ar9132-pll", "qca,ar9130-pll"; reg = <0x18050000 0x20>; clock-names = "ref"; -- cgit v1.2.3