From 574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Dec 2019 05:46:54 +0100 Subject: dts: update to v5.5-rc1 Signed-off-by: Sascha Hauer --- .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 5 + dts/Bindings/display/amlogic,meson-dw-hdmi.yaml | 2 - dts/Bindings/display/arm,malidp.txt | 3 + dts/Bindings/display/bridge/anx6345.yaml | 102 ++++++++++++++ dts/Bindings/display/bridge/anx7814.txt | 6 +- dts/Bindings/display/bridge/renesas,dw-hdmi.txt | 1 + dts/Bindings/display/bridge/renesas,lvds.txt | 1 + dts/Bindings/display/bridge/ti,sn65dsi86.txt | 2 +- dts/Bindings/display/cirrus,clps711x-fb.txt | 2 +- dts/Bindings/display/imx/fsl,imx-fb.txt | 2 +- dts/Bindings/display/mediatek/mediatek,disp.txt | 30 +++-- dts/Bindings/display/mediatek/mediatek,dsi.txt | 4 +- dts/Bindings/display/msm/gmu.txt | 51 +++++++ dts/Bindings/display/msm/mdp5.txt | 2 + dts/Bindings/display/panel/sharp,ld-d5116z01b.txt | 26 ---- dts/Bindings/display/panel/sharp,ld-d5116z01b.yaml | 30 +++++ dts/Bindings/display/renesas,du.txt | 2 + dts/Bindings/display/rockchip/rockchip-vop.txt | 6 +- dts/Bindings/display/st,stm32-dsi.yaml | 150 +++++++++++++++++++++ dts/Bindings/display/st,stm32-ltdc.txt | 144 -------------------- dts/Bindings/display/st,stm32-ltdc.yaml | 81 +++++++++++ 21 files changed, 460 insertions(+), 192 deletions(-) create mode 100644 dts/Bindings/display/bridge/anx6345.yaml delete mode 100644 dts/Bindings/display/panel/sharp,ld-d5116z01b.txt create mode 100644 dts/Bindings/display/panel/sharp,ld-d5116z01b.yaml create mode 100644 dts/Bindings/display/st,stm32-dsi.yaml delete mode 100644 dts/Bindings/display/st,stm32-ltdc.txt create mode 100644 dts/Bindings/display/st,stm32-ltdc.yaml (limited to 'dts/Bindings/display') diff --git a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index 47950fced2..dafc0980c4 100644 --- a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -36,6 +36,9 @@ properties: resets: maxItems: 1 + vcc-dsi-supply: + description: VCC-DSI power supply of the DSI encoder + phys: maxItems: 1 @@ -64,6 +67,7 @@ required: - phys - phy-names - resets + - vcc-dsi-supply - port additionalProperties: false @@ -79,6 +83,7 @@ examples: resets = <&ccu 4>; phys = <&dphy0>; phy-names = "dphy"; + vcc-dsi-supply = <®_dcdc1>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml index fb74768200..0da42ab8fd 100644 --- a/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/dts/Bindings/display/amlogic,meson-dw-hdmi.yaml @@ -79,8 +79,6 @@ properties: hdmi-supply: description: phandle to an external 5V regulator to power the HDMI logic - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle port@0: type: object diff --git a/dts/Bindings/display/arm,malidp.txt b/dts/Bindings/display/arm,malidp.txt index 2f7870983e..7a97a2b48c 100644 --- a/dts/Bindings/display/arm,malidp.txt +++ b/dts/Bindings/display/arm,malidp.txt @@ -37,6 +37,8 @@ Optional properties: Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be used for the framebuffer; if not present, the framebuffer may be located anywhere in memory. + - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS + levels of DP500's QoS signaling. Example: @@ -54,6 +56,7 @@ Example: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-high-level = <0xd000d000>; port { dp0_output: endpoint { remote-endpoint = <&tda998x_2_input>; diff --git a/dts/Bindings/display/bridge/anx6345.yaml b/dts/Bindings/display/bridge/anx6345.yaml new file mode 100644 index 0000000000..6d72b3d11f --- /dev/null +++ b/dts/Bindings/display/bridge/anx6345.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analogix ANX6345 eDP Transmitter Device Tree Bindings + +maintainers: + - Torsten Duwe + +description: | + The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for + portable devices. + +properties: + compatible: + const: analogix,anx6345 + + reg: + maxItems: 1 + description: base I2C address of the device + + reset-gpios: + maxItems: 1 + description: GPIO connected to active low reset + + dvdd12-supply: + maxItems: 1 + description: Regulator for 1.2V digital core power. + + dvdd25-supply: + maxItems: 1 + description: Regulator for 2.5V digital core power. + + ports: + type: object + + properties: + port@0: + type: object + description: | + Video port for LVTTL input + + port@1: + type: object + description: | + Video port for eDP output (panel or connector). + May be omitted if EDID works reliably. + + required: + - port@0 + +required: + - compatible + - reg + - reset-gpios + - dvdd12-supply + - dvdd25-supply + - ports + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + anx6345: anx6345@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + anx6345_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + anx6345_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_anx6345>; + }; + }; + + anx6345_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + anx6345_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/anx7814.txt b/dts/Bindings/display/bridge/anx7814.txt index dbd7c84ee5..17258747ff 100644 --- a/dts/Bindings/display/bridge/anx7814.txt +++ b/dts/Bindings/display/bridge/anx7814.txt @@ -6,7 +6,11 @@ designed for portable devices. Required properties: - - compatible : "analogix,anx7814" + - compatible : Must be one of: + "analogix,anx7808" + "analogix,anx7812" + "analogix,anx7814" + "analogix,anx7818" - reg : I2C address of the device - interrupts : Should contain the INTP interrupt - hpd-gpios : Which GPIO to use for hpd diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt index db680413e8..819f3e3101 100644 --- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt +++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt @@ -13,6 +13,7 @@ Required properties: - compatible : Shall contain one or more of - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX + - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX diff --git a/dts/Bindings/display/bridge/renesas,lvds.txt b/dts/Bindings/display/bridge/renesas,lvds.txt index c6a196d0b0..c62ce2494e 100644 --- a/dts/Bindings/display/bridge/renesas,lvds.txt +++ b/dts/Bindings/display/bridge/renesas,lvds.txt @@ -10,6 +10,7 @@ Required properties: - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders + - "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders diff --git a/dts/Bindings/display/bridge/ti,sn65dsi86.txt b/dts/Bindings/display/bridge/ti,sn65dsi86.txt index 0a3fbb53a1..8ec4a7f262 100644 --- a/dts/Bindings/display/bridge/ti,sn65dsi86.txt +++ b/dts/Bindings/display/bridge/ti,sn65dsi86.txt @@ -21,7 +21,7 @@ Optional properties: - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify flags. See ../../gpio/gpio.txt for more information. -- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of +- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of the cell formats. - clock-names: should be "refclk" diff --git a/dts/Bindings/display/cirrus,clps711x-fb.txt b/dts/Bindings/display/cirrus,clps711x-fb.txt index b0e5066104..0ab5f06636 100644 --- a/dts/Bindings/display/cirrus,clps711x-fb.txt +++ b/dts/Bindings/display/cirrus,clps711x-fb.txt @@ -27,11 +27,11 @@ Example: display: display { model = "320x240x4"; - native-mode = <&timing0>; bits-per-pixel = <4>; ac-prescale = <17>; display-timings { + native-mode = <&timing0>; timing0: 320x240 { hactive = <320>; hback-porch = <0>; diff --git a/dts/Bindings/display/imx/fsl,imx-fb.txt b/dts/Bindings/display/imx/fsl,imx-fb.txt index e5a8b363d8..f4df9e83bc 100644 --- a/dts/Bindings/display/imx/fsl,imx-fb.txt +++ b/dts/Bindings/display/imx/fsl,imx-fb.txt @@ -38,10 +38,10 @@ Example: display0: display0 { model = "Primeview-PD050VL1"; - native-mode = <&timing_disp0>; bits-per-pixel = <16>; fsl,pcr = <0xf0c88080>; /* non-standard but required */ display-timings { + native-mode = <&timing_disp0>; timing_disp0: 640x480 { hactive = <640>; vactive = <480>; diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt index 8469de5100..b91e709db7 100644 --- a/dts/Bindings/display/mediatek/mediatek,disp.txt +++ b/dts/Bindings/display/mediatek/mediatek,disp.txt @@ -27,19 +27,22 @@ Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. Required properties (all function blocks): - compatible: "mediatek,-disp-", one of - "mediatek,-disp-ovl" - overlay (4 layers, blending, csc) - "mediatek,-disp-rdma" - read DMA / line buffer - "mediatek,-disp-wdma" - write DMA - "mediatek,-disp-color" - color processor - "mediatek,-disp-aal" - adaptive ambient light controller - "mediatek,-disp-gamma" - gamma correction - "mediatek,-disp-merge" - merge streams from two RDMA sources - "mediatek,-disp-split" - split stream to two encoders - "mediatek,-disp-ufoe" - data compression engine - "mediatek,-dsi" - DSI controller, see mediatek,dsi.txt - "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt - "mediatek,-disp-mutex" - display mutex - "mediatek,-disp-od" - overdrive + "mediatek,-disp-ovl" - overlay (4 layers, blending, csc) + "mediatek,-disp-ovl-2l" - overlay (2 layers, blending, csc) + "mediatek,-disp-rdma" - read DMA / line buffer + "mediatek,-disp-wdma" - write DMA + "mediatek,-disp-ccorr" - color correction + "mediatek,-disp-color" - color processor + "mediatek,-disp-dither" - dither + "mediatek,-disp-aal" - adaptive ambient light controller + "mediatek,-disp-gamma" - gamma correction + "mediatek,-disp-merge" - merge streams from two RDMA sources + "mediatek,-disp-split" - split stream to two encoders + "mediatek,-disp-ufoe" - data compression engine + "mediatek,-dsi" - DSI controller, see mediatek,dsi.txt + "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt + "mediatek,-disp-mutex" - display mutex + "mediatek,-disp-od" - overdrive the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for @@ -49,6 +52,7 @@ Required properties (all function blocks): For most function blocks this is just a single clock input. Only the DSI and DPI controller nodes have multiple clock inputs. These are documented in mediatek,dsi.txt and mediatek,dpi.txt, respectively. + An exception is that the mt8183 mutex is always free running with no clocks property. Required properties (DMA function blocks): - compatible: Should be one of diff --git a/dts/Bindings/display/mediatek/mediatek,dsi.txt b/dts/Bindings/display/mediatek/mediatek,dsi.txt index fadf327c7c..a19a6cc375 100644 --- a/dts/Bindings/display/mediatek/mediatek,dsi.txt +++ b/dts/Bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder diff --git a/dts/Bindings/display/msm/gmu.txt b/dts/Bindings/display/msm/gmu.txt index 90af5b0a56..bf9c7a2a49 100644 --- a/dts/Bindings/display/msm/gmu.txt +++ b/dts/Bindings/display/msm/gmu.txt @@ -31,6 +31,10 @@ Required properties: - iommus: phandle to the adreno iommu - operating-points-v2: phandle to the OPP operating points +Optional properties: +- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon + SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. + Example: / { @@ -63,3 +67,50 @@ Example: operating-points-v2 = <&gmu_opp_table>; }; }; + +a3xx example with OCMEM support: + +/ { + ... + + gpu: adreno@fdb00000 { + compatible = "qcom,adreno-330.2", + "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 0>; + }; + + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", + "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", + "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; + ranges = <0 0 0xfec00000 0x100000>; + }; + }; +}; diff --git a/dts/Bindings/display/msm/mdp5.txt b/dts/Bindings/display/msm/mdp5.txt index 4e11338548..43d11279c9 100644 --- a/dts/Bindings/display/msm/mdp5.txt +++ b/dts/Bindings/display/msm/mdp5.txt @@ -76,6 +76,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut" + * "tbu" + * "tbu_rt" Example: diff --git a/dts/Bindings/display/panel/sharp,ld-d5116z01b.txt b/dts/Bindings/display/panel/sharp,ld-d5116z01b.txt deleted file mode 100644 index fd9cf39bde..0000000000 --- a/dts/Bindings/display/panel/sharp,ld-d5116z01b.txt +++ /dev/null @@ -1,26 +0,0 @@ -Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel - -Required properties: -- compatible: should be "sharp,ld-d5116z01b" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -This binding is compatible with the simple-panel binding. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [1]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - panel: panel { - compatible = "sharp,ld-d5116z01b"; - power-supply = <&vlcd_3v3>; - - port { - panel_ep: endpoint { - remote-endpoint = <&bridge_out_ep>; - }; - }; - }; diff --git a/dts/Bindings/display/panel/sharp,ld-d5116z01b.yaml b/dts/Bindings/display/panel/sharp,ld-d5116z01b.yaml new file mode 100644 index 0000000000..fbb647eb33 --- /dev/null +++ b/dts/Bindings/display/panel/sharp,ld-d5116z01b.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel + +maintainers: + - Jeffrey Hugo + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ld-d5116z01b + + power-supply: true + backlight: true + port: true + no-hpd: true + +additionalProperties: false + +required: + - compatible + - power-supply + +... diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt index c97dfacad2..17cb277136 100644 --- a/dts/Bindings/display/renesas,du.txt +++ b/dts/Bindings/display/renesas,du.txt @@ -8,6 +8,7 @@ Required Properties: - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU + - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU @@ -60,6 +61,7 @@ corresponding to each DU output. R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - + R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - diff --git a/dts/Bindings/display/rockchip/rockchip-vop.txt b/dts/Bindings/display/rockchip/rockchip-vop.txt index 4f58c5a2d1..8b3a5f5142 100644 --- a/dts/Bindings/display/rockchip/rockchip-vop.txt +++ b/dts/Bindings/display/rockchip/rockchip-vop.txt @@ -20,6 +20,10 @@ Required properties: "rockchip,rk3228-vop"; "rockchip,rk3328-vop"; +- reg: Must contain one entry corresponding to the base address and length + of the register space. Can optionally contain a second entry + corresponding to the CRTC gamma LUT address. + - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier format depends on the interrupt controller used. @@ -48,7 +52,7 @@ Example: SoC specific DT entry: vopb: vopb@ff930000 { compatible = "rockchip,rk3288-vop"; - reg = <0xff930000 0x19c>; + reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml new file mode 100644 index 0000000000..3be76d15bf --- /dev/null +++ b/dts/Bindings/display/st,stm32-dsi.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DSI host controller + +maintainers: + - Philippe Cornu + - Yannick Fertre + +description: + The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. + +properties: + compatible: + const: st,stm32-dsi + + reg: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: DSI bus clock + - description: Pixel clock + minItems: 2 + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: ref + - const: px_clk + minItems: 2 + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + items: + - const: apb + + phy-dsi-supply: + description: + Phandle of the regulator that provides the supply voltage. + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + properties: + port@0: + type: object + description: + DSI input port node, connected to the ltdc rgb output port. + + port@1: + type: object + description: + DSI output port node, connected to a panel or a bridge input port" + +patternProperties: + "^(panel|panel-dsi)@[0-9]$": + type: object + description: + A node containing the panel or bridge description as documented in + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + properties: + port: + type: object + description: + Panel or bridge port node, connected to the DSI output port (port@1) + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + phy-dsi-supply = <®18>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... + + diff --git a/dts/Bindings/display/st,stm32-ltdc.txt b/dts/Bindings/display/st,stm32-ltdc.txt deleted file mode 100644 index 60c54da4e5..0000000000 --- a/dts/Bindings/display/st,stm32-ltdc.txt +++ /dev/null @@ -1,144 +0,0 @@ -* STMicroelectronics STM32 lcd-tft display controller - -- ltdc: lcd-tft display controller host - Required properties: - - compatible: "st,stm32-ltdc" - - reg: Physical base address of the IP registers and length of memory mapped region. - - clocks: A list of phandle + clock-specifier pairs, one for each - entry in 'clock-names'. - - clock-names: A list of clock names. For ltdc it should contain: - - "lcd" for the clock feeding the output pixel clock & IP clock. - - resets: reset to be used by the device (defined by use of RCC macro). - Required nodes: - - Video port for DPI RGB output: ltdc has one video port with up to 2 - endpoints: - - for external dpi rgb panel or bridge, using gpios. - - for internal dpi input of the MIPI DSI host controller. - Note: These 2 endpoints cannot be activated simultaneously. - -* STMicroelectronics STM32 DSI controller specific extensions to Synopsys - DesignWare MIPI DSI host controller - -The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI -DSI host controller. For all mandatory properties & nodes, please refer -to the related documentation in [5]. - -Mandatory properties specific to STM32 DSI: -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. -- compatible: "st,stm32-dsi". -- clock-names: - - phy pll reference clock string name, must be "ref". -- resets: see [5]. -- reset-names: see [5]. - -Mandatory nodes specific to STM32 DSI: -- ports: A node containing DSI input & output port nodes with endpoint - definitions as documented in [3] & [4]. - - port@0: DSI input port node, connected to the ltdc rgb output port. - - port@1: DSI output port node, connected to a panel or a bridge input port. -- panel or bridge node: A node containing the panel or bridge description as - documented in [6]. - - port: panel or bridge port node, connected to the DSI output port (port@1). -Optional properties: -- phy-dsi-supply: phandle of the regulator that provides the supply voltage. - -Note: You can find more documentation in the following references -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/graph.txt -[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt -[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt - -Example 1: RGB panel -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_rgb: endpoint { - }; - }; - }; - }; -}; - -Example 2: DSI panel - -/ { - ... - soc { - ... - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - - dsi: dsi@40016c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_in_panel>; - }; - }; - - }; - - panel-dsi@0 { - reg = <0>; /* dsi virtual channel (0..3) */ - compatible = ...; - enable-gpios = ...; - - port { - dsi_in_panel: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - }; - - }; - - }; -}; diff --git a/dts/Bindings/display/st,stm32-ltdc.yaml b/dts/Bindings/display/st,stm32-ltdc.yaml new file mode 100644 index 0000000000..bf8ad916e9 --- /dev/null +++ b/dts/Bindings/display/st,stm32-ltdc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 lcd-tft display controller + +maintainers: + - Philippe Cornu + - Yannick Fertre + +properties: + compatible: + const: st,stm32-ltdc + + reg: + maxItems: 1 + + interrupts: + items: + - description: events interrupt line. + - description: errors interrupt line. + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: lcd + + resets: + maxItems: 1 + + port: + type: object + description: + "Video port for DPI RGB output. + ltdc has one video port with up to 2 endpoints: + - for external dpi rgb panel or bridge, using gpios. + - for internal dpi input of the MIPI DSI host controller. + Note: These 2 endpoints cannot be activated simultaneously. + Please refer to the bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt." + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - port + +additionalProperties: false + +examples: + - | + #include + #include + #include + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + +... + -- cgit v1.2.3