From 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Sep 2018 08:26:30 +0200 Subject: dts: update to v4.19-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/dma/jz4780-dma.txt | 1 - dts/Bindings/dma/nvidia,tegra210-adma.txt | 1 - dts/Bindings/dma/owl-dma.txt | 47 +++++++++++++++++++++++++++++++ dts/Bindings/dma/renesas,rcar-dmac.txt | 1 + dts/Bindings/dma/snps,dw-axi-dmac.txt | 2 -- dts/Bindings/dma/snps-dma.txt | 2 -- dts/Bindings/dma/ti-edma.txt | 1 - dts/Bindings/dma/xilinx/xilinx_dma.txt | 2 ++ dts/Bindings/dma/xilinx/zynqmp_dma.txt | 1 - 9 files changed, 50 insertions(+), 8 deletions(-) create mode 100644 dts/Bindings/dma/owl-dma.txt (limited to 'dts/Bindings/dma') diff --git a/dts/Bindings/dma/jz4780-dma.txt b/dts/Bindings/dma/jz4780-dma.txt index f25feee62b..03e9cf7b42 100644 --- a/dts/Bindings/dma/jz4780-dma.txt +++ b/dts/Bindings/dma/jz4780-dma.txt @@ -5,7 +5,6 @@ Required properties: - compatible: Should be "ingenic,jz4780-dma" - reg: Should contain the DMA controller registers location and length. - interrupts: Should contain the interrupt specifier of the DMA controller. -- interrupt-parent: Should be the phandle of the interrupt controller that - clocks: Should contain a clock specifier for the JZ4780 PDMA clock. - #dma-cells: Must be <2>. Number of integer cells in the dmas property of DMA clients (see below). diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.txt b/dts/Bindings/dma/nvidia,tegra210-adma.txt index 1e1dc8f972..2f35b047f7 100644 --- a/dts/Bindings/dma/nvidia,tegra210-adma.txt +++ b/dts/Bindings/dma/nvidia,tegra210-adma.txt @@ -8,7 +8,6 @@ Required properties: - reg: Should contain DMA registers location and length. This should be a single entry that includes all of the per-channel registers in one contiguous bank. -- interrupt-parent: Phandle to the interrupt parent controller. - interrupts: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. - clocks: Must contain one entry for the ADMA module clock diff --git a/dts/Bindings/dma/owl-dma.txt b/dts/Bindings/dma/owl-dma.txt new file mode 100644 index 0000000000..03e9bb12b7 --- /dev/null +++ b/dts/Bindings/dma/owl-dma.txt @@ -0,0 +1,47 @@ +* Actions Semi Owl SoCs DMA controller + +This binding follows the generic DMA bindings defined in dma.txt. + +Required properties: +- compatible: Should be "actions,s900-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain 4 interrupts shared by all channel. +- #dma-cells: Must be <1>. Used to represent the number of integer + cells in the dmas property of client device. +- dma-channels: Physical channels supported. +- dma-requests: Number of DMA request signals supported by the controller. + Refer to Documentation/devicetree/bindings/dma/dma.txt +- clocks: Phandle and Specifier of the clock feeding the DMA controller. + +Example: + +Controller: + dma: dma-controller@e0260000 { + compatible = "actions,s900-dma"; + reg = <0x0 0xe0260000 0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&clock CLK_DMAC>; + }; + +Client: + +DMA clients connected to the Actions Semi Owl SoCs DMA controller must +use the format described in the dma.txt file, using a two-cell specifier +for each channel. + +The two cells in order are: +1. A phandle pointing to the DMA controller. +2. The channel id. + +uart5: serial@e012a000 { + ... + dma-names = "tx", "rx"; + dmas = <&dma 26>, <&dma 27>; + ... +}; diff --git a/dts/Bindings/dma/renesas,rcar-dmac.txt b/dts/Bindings/dma/renesas,rcar-dmac.txt index b1ba639554..946229c486 100644 --- a/dts/Bindings/dma/renesas,rcar-dmac.txt +++ b/dts/Bindings/dma/renesas,rcar-dmac.txt @@ -29,6 +29,7 @@ Required Properties: - "renesas,dmac-r8a77965" (R-Car M3-N) - "renesas,dmac-r8a77970" (R-Car V3M) - "renesas,dmac-r8a77980" (R-Car V3H) + - "renesas,dmac-r8a77990" (R-Car E3) - "renesas,dmac-r8a77995" (R-Car D3) - reg: base address and length of the registers block for the DMAC diff --git a/dts/Bindings/dma/snps,dw-axi-dmac.txt b/dts/Bindings/dma/snps,dw-axi-dmac.txt index f237b79282..dbe160400a 100644 --- a/dts/Bindings/dma/snps,dw-axi-dmac.txt +++ b/dts/Bindings/dma/snps,dw-axi-dmac.txt @@ -5,8 +5,6 @@ Required properties: - reg: Address range of the DMAC registers. This should include all of the per-channel registers. - interrupt: Should contain the DMAC interrupt number. -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device. - dma-channels: Number of channels supported by hardware. - snps,dma-masters: Number of AXI masters supported by the hardware. - snps,data-width: Maximum AXI data width supported by hardware. diff --git a/dts/Bindings/dma/snps-dma.txt b/dts/Bindings/dma/snps-dma.txt index 99acc712f8..39e2b26be3 100644 --- a/dts/Bindings/dma/snps-dma.txt +++ b/dts/Bindings/dma/snps-dma.txt @@ -23,8 +23,6 @@ Deprecated properties: Optional properties: -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device - is_private: The device channels should be marked as private and not for by the general purpose DMA channel allocator. False if not passed. - multi-block: Multi block transfers supported by hardware. Array property with diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt index 3f15f66445..4bbc94d829 100644 --- a/dts/Bindings/dma/ti-edma.txt +++ b/dts/Bindings/dma/ti-edma.txt @@ -201,7 +201,6 @@ Required properties: - #dma-cells: Should be set to <1> Clients should use a single channel number per DMA request. - reg: Memory map for accessing module -- interrupt-parent: Interrupt controller the interrupt is routed through - interrupts: Exactly 3 interrupts need to be specified in the order: 1. Transfer completion interrupt. 2. Memory protection interrupt. diff --git a/dts/Bindings/dma/xilinx/xilinx_dma.txt b/dts/Bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec4..174af2c45e 100644 --- a/dts/Bindings/dma/xilinx/xilinx_dma.txt +++ b/dts/Bindings/dma/xilinx/xilinx_dma.txt @@ -66,6 +66,8 @@ Optional child node properties: Optional child node properties for VDMA: - xlnx,genlock-mode: Tells Genlock synchronization is enabled/disabled in hardware. +- xlnx,enable-vert-flip: Tells vertical flip is + enabled/disabled in hardware(S2MM path). Optional child node properties for AXI DMA: -dma-channels: Number of dma channels in child node. diff --git a/dts/Bindings/dma/xilinx/zynqmp_dma.txt b/dts/Bindings/dma/xilinx/zynqmp_dma.txt index a784cdd947..07a5a7aa9e 100644 --- a/dts/Bindings/dma/xilinx/zynqmp_dma.txt +++ b/dts/Bindings/dma/xilinx/zynqmp_dma.txt @@ -5,7 +5,6 @@ control and rate control support for slave/peripheral dma access. Required properties: - compatible : Should be "xlnx,zynqmp-dma-1.0" - reg : Memory map for gdma/adma module access. -- interrupt-parent : Interrupt controller the interrupt is routed through - interrupts : Should contain DMA channel interrupt. - xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 - clock-names : List of input clocks "clk_main", "clk_apb" -- cgit v1.2.3