From 796af3473b8222bcd89aa63e9886c355a6baf95d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Jun 2019 00:06:30 +0200 Subject: dts: update to v5.2-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt (limited to 'dts/Bindings/fpga') diff --git a/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt new file mode 100644 index 0000000000..3052bf619d --- /dev/null +++ b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -0,0 +1,25 @@ +Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. +The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the +Programmable Logic (PL). The configuration uses the firmware interface. + +Required properties: +- compatible: should contain "xlnx,zynqmp-pcap-fpga" + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + }; + }; + }; -- cgit v1.2.3