From 3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 17 Nov 2021 07:36:09 +0100 Subject: dts: update to v5.16-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml (limited to 'dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml') diff --git a/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml new file mode 100644 index 0000000000..31c0fc3459 --- /dev/null +++ b/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ZynqMP Mode Pin GPIO controller + +description: + PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin + GPIO controller with configurable from numbers of pins (from 0 to 3 per + PS_MODE). Every pin can be configured as input/output. + +maintainers: + - Piyush Mehta + +properties: + compatible: + const: xlnx,zynqmp-gpio-modepin + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + zynqmp-firmware { + gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +... -- cgit v1.2.3