From a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 8 Dec 2015 07:33:36 +0100 Subject: dts: update to v4.3-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/gpio/brcm,brcmstb-gpio.txt | 35 ++++++++++++++++++++++++++------- dts/Bindings/gpio/gpio-etraxfs.txt | 3 ++- dts/Bindings/gpio/gpio-mpc8xxx.txt | 22 +++++++++++++++++++++ dts/Bindings/gpio/renesas,gpio-rcar.txt | 1 + dts/Bindings/gpio/zx296702-gpio.txt | 24 ++++++++++++++++++++++ 5 files changed, 77 insertions(+), 8 deletions(-) create mode 100644 dts/Bindings/gpio/gpio-mpc8xxx.txt create mode 100644 dts/Bindings/gpio/zx296702-gpio.txt (limited to 'dts/Bindings/gpio') diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt index 435f1bcca3..b405b4410b 100644 --- a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt +++ b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt @@ -33,6 +33,13 @@ Optional properties: - interrupt-parent: phandle of the parent interrupt controller +- interrupts-extended: + Alternate form of specifying interrupts and parents that allows for + multiple parents. This takes precedence over 'interrupts' and + 'interrupt-parent'. Wakeup-capable GPIO controllers often route their + wakeup interrupt lines through a different interrupt controller than the + primary interrupt line, making this property necessary. + - #interrupt-cells: Should be <2>. The first cell is the GPIO number, the second should specify flags. The following subset of flags is supported: @@ -47,19 +54,33 @@ Optional properties: - interrupt-controller: Marks the device node as an interrupt controller -- interrupt-names: - The name of the IRQ resource used by this controller +- wakeup-source: + GPIOs for this controller can be used as a wakeup source Example: upg_gio: gpio@f040a700 { - #gpio-cells = <0x2>; - #interrupt-cells = <0x2>; + #gpio-cells = <2>; + #interrupt-cells = <2>; compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; gpio-controller; interrupt-controller; reg = <0xf040a700 0x80>; - interrupt-parent = <0xf>; + interrupt-parent = <&irq0_intc>; + interrupts = <0x6>; + brcm,gpio-bank-widths = <32 32 32 24>; + }; + + upg_gio_aon: gpio@f04172c0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf04172c0 0x40>; + interrupt-parent = <&irq0_aon_intc>; interrupts = <0x6>; - interrupt-names = "upg_gio"; - brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>; + interrupts-extended = <&irq0_aon_intc 0x6>, + <&aon_pm_l2_intc 0x5>; + wakeup-source; + brcm,gpio-bank-widths = <18 4>; }; diff --git a/dts/Bindings/gpio/gpio-etraxfs.txt b/dts/Bindings/gpio/gpio-etraxfs.txt index abf4db736c..170194af30 100644 --- a/dts/Bindings/gpio/gpio-etraxfs.txt +++ b/dts/Bindings/gpio/gpio-etraxfs.txt @@ -2,8 +2,9 @@ Axis ETRAX FS General I/O controller bindings Required properties: -- compatible: +- compatible: one of: - "axis,etraxfs-gio" + - "axis,artpec3-gio" - reg: Physical base address and length of the controller's registers. - #gpio-cells: Should be 3 - The first cell is the gpio offset number. diff --git a/dts/Bindings/gpio/gpio-mpc8xxx.txt b/dts/Bindings/gpio/gpio-mpc8xxx.txt new file mode 100644 index 0000000000..805ddcd79a --- /dev/null +++ b/dts/Bindings/gpio/gpio-mpc8xxx.txt @@ -0,0 +1,22 @@ +* Freescale MPC512x/MPC8xxx GPIO controller + +Required properties: +- compatible : Should be "fsl,-gpio" + The following s are known to be supported: + mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq +- reg : Address and length of the register set for the device +- interrupts : Should be the port interrupt shared by all 32 pins. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + +Example: + +gpio0: gpio@1100 { + compatible = "fsl,mpc5125-gpio"; + #gpio-cells = <2>; + reg = <0x1100 0x080>; + interrupts = <78 0x8>; + status = "okay"; +}; diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt index 38fb86f28b..f60e2f477e 100644 --- a/dts/Bindings/gpio/renesas,gpio-rcar.txt +++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt @@ -9,6 +9,7 @@ Required Properties: - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. + - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - "renesas,gpio-rcar": for generic R-Car GPIO controller. - reg: Base address and length of each memory resource used by the GPIO diff --git a/dts/Bindings/gpio/zx296702-gpio.txt b/dts/Bindings/gpio/zx296702-gpio.txt new file mode 100644 index 0000000000..0dab156fcf --- /dev/null +++ b/dts/Bindings/gpio/zx296702-gpio.txt @@ -0,0 +1,24 @@ +ZTE ZX296702 GPIO controller + +Required properties: +- compatible : "zte,zx296702-gpio" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters: + - bit 0 specifies polarity (0 for normal, 1 for inverted) +- gpio-controller : Marks the device node as a GPIO controller. +- interrupts : Interrupt mapping for GPIO IRQ. +- gpio-ranges : Interaction with the PINCTRL subsystem. + +gpio1: gpio@b008040 { + compatible = "zte,zx296702-gpio"; + reg = <0xb008040 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>; + interrupts = ; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <2>; + clock-names = "gpio_pclk"; + clocks = <&lsp0clk ZX296702_GPIO_CLK>; +}; -- cgit v1.2.3