From 796af3473b8222bcd89aa63e9886c355a6baf95d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Jun 2019 00:06:30 +0200 Subject: dts: update to v5.2-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/i2c/i2c-designware.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'dts/Bindings/i2c/i2c-designware.txt') diff --git a/dts/Bindings/i2c/i2c-designware.txt b/dts/Bindings/i2c/i2c-designware.txt index 3e4bcc2fb6..08be4d3846 100644 --- a/dts/Bindings/i2c/i2c-designware.txt +++ b/dts/Bindings/i2c/i2c-designware.txt @@ -6,12 +6,21 @@ Required properties : or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback - reg : Offset and length of the register set for the device - interrupts : where IRQ is the interrupt number. + - clocks : phandles for the clocks, see the description of clock-names below. + The phandle for the "ic_clk" clock is required. The phandle for the "pclk" + clock is optional. If a single clock is specified but no clock-name, it is + the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first. Recommended properties : - clock-frequency : desired I2C bus clock frequency in Hz. Optional properties : + + - clock-names : Contains the names of the clocks: + "ic_clk", for the core clock used to generate the external I2C clock. + "pclk", the interface clock, required for register access. + - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold time, named ICPU_CFG:TWI_DELAY in the datasheet. -- cgit v1.2.3