From 6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 8 Dec 2015 07:35:17 +0100 Subject: dts: update to v4.4-rc1 Signed-off-by: Sascha Hauer --- .../arm,versatile-fpga-irq.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt (limited to 'dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt') diff --git a/dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt new file mode 100644 index 0000000000..c9cf605bb9 --- /dev/null +++ b/dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt @@ -0,0 +1,36 @@ +* ARM Versatile FPGA interrupt controller + +One or more FPGA IRQ controllers can be synthesized in an ARM reference board +such as the Integrator or Versatile family. The output of these different +controllers are OR:ed together and fed to the CPU tile's IRQ input. Each +instance can handle up to 32 interrupts. + +Required properties: +- compatible: "arm,versatile-fpga-irq" +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. Must be 1 + as the FPGA IRQ controller has no configuration options for interrupt + sources. The cell is a u32 and defines the interrupt number. +- reg: The register bank for the FPGA interrupt controller. +- clear-mask: a u32 number representing the mask written to clear all IRQs + on the controller at boot for example. +- valid-mask: a u32 number representing a bit mask determining which of + the interrupts are valid. Unconnected/unused lines are set to 0, and + the system till not make it possible for devices to request these + interrupts. + +Example: + +pic: pic@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x003fffff>; +}; + +Optional properties: +- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ + output is simply connected to the input of another IRQ controller, + then the parent IRQ shall be specified in this property. -- cgit v1.2.3