From 87360e3dd42bb627a9f2611f961728c0789e1c21 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Jul 2015 14:44:21 +0200 Subject: dts: update to v4.2-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/interrupt-controller/ingenic,intc.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 dts/Bindings/interrupt-controller/ingenic,intc.txt (limited to 'dts/Bindings/interrupt-controller/ingenic,intc.txt') diff --git a/dts/Bindings/interrupt-controller/ingenic,intc.txt b/dts/Bindings/interrupt-controller/ingenic,intc.txt new file mode 100644 index 0000000000..5f89fb635a --- /dev/null +++ b/dts/Bindings/interrupt-controller/ingenic,intc.txt @@ -0,0 +1,28 @@ +Ingenic SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,-intc". Valid strings are: + ingenic,jz4740-intc + ingenic,jz4770-intc + ingenic,jz4775-intc + ingenic,jz4780-intc +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; -- cgit v1.2.3