From 6b85c20d46812bdbc062b863261c3e5100e30556 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 8 May 2018 08:14:56 +0200 Subject: dts: update to v4.17-rc1 Signed-off-by: Sascha Hauer --- .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt (limited to 'dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt') diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt new file mode 100644 index 0000000000..b47a8a02b1 --- /dev/null +++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -0,0 +1,22 @@ +Microsemi Ocelot SoC ICPU Interrupt Controller + +Required properties: + +- compatible : should be "mscc,ocelot-icpu-intr" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; -- cgit v1.2.3