From eaa819409db6ac80fbd7c3d36450b2d1bec93576 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 3 Mar 2015 08:11:01 +0100 Subject: dts: update to v4.0-rc1 Signed-off-by: Sascha Hauer --- .../interrupt-controller/ti,omap-intc-irq.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt (limited to 'dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt') diff --git a/dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt b/dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt new file mode 100644 index 0000000000..38ce5d0377 --- /dev/null +++ b/dts/Bindings/interrupt-controller/ti,omap-intc-irq.txt @@ -0,0 +1,28 @@ +Omap2/3 intc controller + +On TI omap2 and 3 the intc interrupt controller can provide +96 or 128 IRQ signals to the ARM host depending on the SoC. + +Required Properties: +- compatible: should be one of + "ti,omap2-intc" + "ti,omap3-intc" + "ti,dm814-intc" + "ti,dm816-intc" + "ti,am33xx-intc" + +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 for intc +- interrupts: interrupt reference to primary interrupt controller + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + intc: interrupt-controller@48200000 { + compatible = "ti,omap3-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; -- cgit v1.2.3