From ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 6 Oct 2017 06:12:41 +0200 Subject: dts: update to v4.14-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/memory-controllers/mediatek,smi-larb.txt | 15 +++++++++++++++ dts/Bindings/memory-controllers/mvebu-devbus.txt | 1 - 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'dts/Bindings/memory-controllers') diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt index 21277a56e9..ddf46b8856 100644 --- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt +++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt @@ -15,6 +15,9 @@ Required properties: the register. - "smi" : It's the clock for transfer data and command. +Required property for mt2701: +- mediatek,larb-id :the hardware id of this larb. + Example: larb1: larb@16010000 { compatible = "mediatek,mt8173-smi-larb"; @@ -25,3 +28,15 @@ Example: <&vdecsys CLK_VDEC_LARB_CKEN>; clock-names = "apb", "smi"; }; + +Example for mt2701: + larb0: larb@14010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; diff --git a/dts/Bindings/memory-controllers/mvebu-devbus.txt b/dts/Bindings/memory-controllers/mvebu-devbus.txt index 1ee3bc09f3..8b9388cc1c 100644 --- a/dts/Bindings/memory-controllers/mvebu-devbus.txt +++ b/dts/Bindings/memory-controllers/mvebu-devbus.txt @@ -130,7 +130,6 @@ The reg property implicitly specifies the chip select as this: Example: devbus-bootcs@d0010400 { - status = "okay"; ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */ #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3