From 86186c232241b607f84cc266a6cda49160f44948 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 13 Jun 2016 07:31:46 +0200 Subject: dts: update to v4.7-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/mips/brcm/soc.txt | 3 ++- dts/Bindings/mips/cavium/ciu3.txt | 27 +++++++++++++++++++++++++++ dts/Bindings/mips/cpu_irq.txt | 2 +- 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 dts/Bindings/mips/cavium/ciu3.txt (limited to 'dts/Bindings/mips') diff --git a/dts/Bindings/mips/brcm/soc.txt b/dts/Bindings/mips/brcm/soc.txt index 7bab90cc4a..4a7e030e4f 100644 --- a/dts/Bindings/mips/brcm/soc.txt +++ b/dts/Bindings/mips/brcm/soc.txt @@ -4,7 +4,8 @@ Required properties: - compatible: "brcm,bcm3384", "brcm,bcm33843" "brcm,bcm3384-viper", "brcm,bcm33843-viper" - "brcm,bcm6328", "brcm,bcm6368", + "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6368", + "brcm,bcm63168", "brcm,bcm63268", "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360", "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425" diff --git a/dts/Bindings/mips/cavium/ciu3.txt b/dts/Bindings/mips/cavium/ciu3.txt new file mode 100644 index 0000000000..616862ad2b --- /dev/null +++ b/dts/Bindings/mips/cavium/ciu3.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit v3 + +Properties: +- compatible: "cavium,octeon-7890-ciu3" + + Compatibility with 78XX and 73XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is source number. + The second cell indicates the triggering semantics, and may have a + value of either 4 for level semantics, or 1 for edge semantics. + +Example: + interrupt-controller@1010000000000 { + compatible = "cavium,octeon-7890-ciu3"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Source number (20 significant bits) + * 2) Trigger type: (4 == level, 1 == edge) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10100 0x00000000 0x0 0xb0000000>; + }; diff --git a/dts/Bindings/mips/cpu_irq.txt b/dts/Bindings/mips/cpu_irq.txt index fc149f326d..f080f06da6 100644 --- a/dts/Bindings/mips/cpu_irq.txt +++ b/dts/Bindings/mips/cpu_irq.txt @@ -13,7 +13,7 @@ Required properties: - compatible : Should be "mti,cpu-interrupt-controller" Example devicetree: - cpu-irq: cpu-irq@0 { + cpu-irq: cpu-irq { #address-cells = <0>; interrupt-controller; -- cgit v1.2.3