From 6940ba22c66ac1c713500027bf5f6832442a1410 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 19 Aug 2019 08:56:20 +0200 Subject: dts: update to v5.3-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/mmc/sdhci-sprd.txt | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'dts/Bindings/mmc/sdhci-sprd.txt') diff --git a/dts/Bindings/mmc/sdhci-sprd.txt b/dts/Bindings/mmc/sdhci-sprd.txt index 45c9978aad..eb7eb1b529 100644 --- a/dts/Bindings/mmc/sdhci-sprd.txt +++ b/dts/Bindings/mmc/sdhci-sprd.txt @@ -14,10 +14,31 @@ Required properties: - clock-names: Should contain the following: "sdio" - SDIO source clock (required) "enable" - gate clock which used for enabling/disabling the device (required) + "2x_enable" - gate clock controlling the device for some special platforms (optional) Optional properties: - assigned-clocks: the same with "sdio" clock - assigned-clock-parents: the default parent of "sdio" clock +- pinctrl-names: should be "default", "state_uhs" +- pinctrl-0: should contain default/high speed pin control +- pinctrl-1: should contain uhs mode pin control + +PHY DLL delays are used to delay the data valid window, and align the window +to sampling clock. PHY DLL delays can be configured by following properties, +and each property contains 4 cells which are used to configure the clock data +write line delay value, clock read command line delay value, clock read data +positive edge delay value and clock read data negative edge delay value. +Each cell's delay value unit is cycle of the PHY clock. + +- sprd,phy-delay-legacy: Delay value for legacy timing. +- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing. +- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing. +- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing. +- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing. +- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing. +- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing. +- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing. +- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing. Examples: @@ -32,6 +53,11 @@ sdio0: sdio@20600000 { assigned-clocks = <&ap_clk CLK_EMMC_2X>; assigned-clock-parents = <&rpll CLK_RPLL_390M>; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd0_pins_default>; + pinctrl-1 = <&sd0_pins_uhs>; + + sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>; bus-width = <8>; non-removable; no-sdio; -- cgit v1.2.3