From 119c632f12509eab4bc58daf629c4b16fffcedca Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 9 Nov 2020 12:38:26 +0100 Subject: dts: update to v5.10-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/perf/arm,cmn.yaml | 57 ++++++++++++++++++++++++++++++++++++++ dts/Bindings/perf/fsl-imx-ddr.txt | 22 --------------- dts/Bindings/perf/fsl-imx-ddr.yaml | 49 ++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 22 deletions(-) create mode 100644 dts/Bindings/perf/arm,cmn.yaml delete mode 100644 dts/Bindings/perf/fsl-imx-ddr.txt create mode 100644 dts/Bindings/perf/fsl-imx-ddr.yaml (limited to 'dts/Bindings/perf') diff --git a/dts/Bindings/perf/arm,cmn.yaml b/dts/Bindings/perf/arm,cmn.yaml new file mode 100644 index 0000000000..e4fcc0de25 --- /dev/null +++ b/dts/Bindings/perf/arm,cmn.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2020 Arm Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,cmn.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm CMN (Coherent Mesh Network) Performance Monitors + +maintainers: + - Robin Murphy + +properties: + compatible: + const: arm,cmn-600 + + reg: + items: + - description: Physical address of the base (PERIPHBASE) and + size (up to 64MB) of the configuration address space. + + interrupts: + minItems: 1 + maxItems: 4 + items: + - description: Overflow interrupt for DTC0 + - description: Overflow interrupt for DTC1 + - description: Overflow interrupt for DTC2 + - description: Overflow interrupt for DTC3 + description: One interrupt for each DTC domain implemented must + be specified, in order. DTC0 is always present. + + arm,root-node: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset from PERIPHBASE of the configuration + discovery node (see TRM definition of ROOTNODEBASE). + +required: + - compatible + - reg + - interrupts + - arm,root-node + +additionalProperties: false + +examples: + - | + #include + #include + pmu@50000000 { + compatible = "arm,cmn-600"; + reg = <0x50000000 0x4000000>; + /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */ + interrupts = ; + arm,root-node = <0x104000>; + }; +... diff --git a/dts/Bindings/perf/fsl-imx-ddr.txt b/dts/Bindings/perf/fsl-imx-ddr.txt deleted file mode 100644 index 7822a806ea..0000000000 --- a/dts/Bindings/perf/fsl-imx-ddr.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Freescale(NXP) IMX8 DDR performance monitor - -Required properties: - -- compatible: should be one of: - "fsl,imx8-ddr-pmu" - "fsl,imx8m-ddr-pmu" - "fsl,imx8mp-ddr-pmu" - -- reg: physical address and size - -- interrupts: single interrupt - generated by the control block - -Example: - - ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; - reg = <0x5c020000 0x10000>; - interrupt-parent = <&gic>; - interrupts = ; - }; diff --git a/dts/Bindings/perf/fsl-imx-ddr.yaml b/dts/Bindings/perf/fsl-imx-ddr.yaml new file mode 100644 index 0000000000..5aad9f4e0b --- /dev/null +++ b/dts/Bindings/perf/fsl-imx-ddr.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale(NXP) IMX8 DDR performance monitor + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - fsl,imx8-ddr-pmu + - fsl,imx8m-ddr-pmu + - fsl,imx8mp-ddr-pmu + - items: + - enum: + - fsl,imx8mm-ddr-pmu + - fsl,imx8mn-ddr-pmu + - fsl,imx8mq-ddr-pmu + - fsl,imx8mp-ddr-pmu + - const: fsl,imx8m-ddr-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; -- cgit v1.2.3