From 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Sep 2018 08:26:30 +0200 Subject: dts: update to v4.19-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt (limited to 'dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt') diff --git a/dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt new file mode 100644 index 0000000000..66de750904 --- /dev/null +++ b/dts/Bindings/pinctrl/fsl,imx8mq-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale IMX8MQ IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mq-iomuxc" +- reg: should contain the base physical address and size of the iomuxc + registers. + +Required properties in sub-nodes: +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x0 0x30330000 0x0 0x10000>; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; +}; -- cgit v1.2.3