From 33fdc89d4cbd74aa54c28dc61d62972ab164e64d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 14 Jan 2019 09:09:57 +0100 Subject: dts: update to v5.0-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/pinctrl/actions,s700-pinctrl.txt | 170 +++++++++++++++++++++++ dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 14 ++ dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt | 16 +-- dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt | 66 ++++----- dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt | 3 +- dts/Bindings/pinctrl/pinctrl-mt6797.txt | 83 +++++++++++ dts/Bindings/pinctrl/pinctrl-mt7622.txt | 131 +++++++++++++++++ dts/Bindings/pinctrl/qcom,pmic-gpio.txt | 2 +- dts/Bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 ++++++++++++ dts/Bindings/pinctrl/st,stm32-pinctrl.txt | 1 + 10 files changed, 525 insertions(+), 48 deletions(-) create mode 100644 dts/Bindings/pinctrl/actions,s700-pinctrl.txt create mode 100644 dts/Bindings/pinctrl/pinctrl-mt6797.txt create mode 100644 dts/Bindings/pinctrl/renesas,rza2-pinctrl.txt (limited to 'dts/Bindings/pinctrl') diff --git a/dts/Bindings/pinctrl/actions,s700-pinctrl.txt b/dts/Bindings/pinctrl/actions,s700-pinctrl.txt new file mode 100644 index 0000000000..d13ff82f85 --- /dev/null +++ b/dts/Bindings/pinctrl/actions,s700-pinctrl.txt @@ -0,0 +1,170 @@ +Actions Semi S700 Pin Controller + +This binding describes the pin controller found in the S700 SoC. + +Required Properties: + +- compatible: Should be "actions,s700-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller +- gpio-controller: Marks the device node as a GPIO controller. +- gpio-ranges: Specifies the mapping between gpio controller and + pin-controller pins. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt +- interrupts: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends + on the number of GPIO banks on the SoC. The interrupts must be + ordered by bank, starting with bank 0. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, + sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, + i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, + csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, + dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, + dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, + dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, + dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 + +- groups: An array of strings, each string containing the name of a pin + group. These pin groups are used for selecting the pinmux + functions. + rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, + rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, + rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, + i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, + ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, + lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, + dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, + sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, + i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, + pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, + nand_ceb2_mfp, nand_ceb3_mfp + + These pin groups are used for selecting the drive strength + parameters. + + sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, + rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, + pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, + dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, + uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, + sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv + +- function: An array of strings, each string containing the name of the + pinmux functions. These functions can only be selected by + the corresponding pin groups. The following are the list of + pinmux functions available: + + nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, + sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, + clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 + +Optional Properties: + +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <2> + <4> + <8> + <12> + +Example: + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + uart3-default: uart3-default { + pinmux { + groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; + function = "uart3"; + }; + pinconf { + groups = "uart3_all_drv"; + drive-strength = <2>; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 258a4648ab..cf96b7c20e 100644 --- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -29,6 +29,7 @@ Required properties: "allwinner,sun50i-h5-pinctrl" "allwinner,sun50i-h6-pinctrl" "allwinner,sun50i-h6-r-pinctrl" + "allwinner,suniv-f1c100s-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the @@ -43,6 +44,19 @@ Note: For backward compatibility reasons, the hosc and losc clocks are only required if you need to use the optional input-debounce property. Any new device tree should set them. +Each pin bank, depending on the SoC, can have an associated regulator: + +- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs +- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs +- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs +- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs +- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs +- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs +- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs +- vcc-ph-supply: for the A31, A31s and A80 SoCs +- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs +- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs + Optional properties: - input-debounce: Array of debouncing periods in microseconds. One period per irq bank found in the controller. 0 if no setup required. diff --git a/dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt b/dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt index 4fa9539070..8ab2d468db 100644 --- a/dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt +++ b/dts/Bindings/pinctrl/brcm,bcm4708-pinmux.txt @@ -7,13 +7,15 @@ configure controller correctly. A list of pins varies across chipsets so few bindings are available. +Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" +noce. + Required properties: - compatible: must be one of: "brcm,bcm4708-pinmux" "brcm,bcm4709-pinmux" "brcm,bcm53012-pinmux" -- reg: iomem address range of CRU (Central Resource Unit) pin registers -- reg-names: "cru_gpio_control" - the only needed & supported reg right now +- offset: offset of pin registers in the CRU block Functions and their groups available for all chipsets: - "spi": "spi_grp" @@ -37,16 +39,12 @@ Example: #size-cells = <1>; cru@100 { - compatible = "simple-bus"; + compatible = "syscon", "simple-mfd"; reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - pin-controller@1c0 { + pinctrl { compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; + offset = <0xc0>; spi-pins { function = "spi"; diff --git a/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt index 44ad670ae1..bfa3703a74 100644 --- a/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ b/dts/Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -7,55 +7,47 @@ Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it only supports generic pin config. -Please also refer pinctrl-bindings.txt in this directory for generic pinctrl -binding. - -=== Pin Controller Node === +Please refer to fsl,imx-pinctrl.txt in this directory for common binding +part and usage. Required properties: -- compatible: "fsl,imx7ulp-iomuxc1" -- reg: Should contain the base physical address and size of the iomuxc - registers. - -=== Pin Configuration Node === -- pinmux: One integers array, represents a group of pins mux setting. - The format is pinmux = , PIN_FUNC_ID is a pin working on - a specific function. - - NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux - and config register as follows: - - - Refer to imx7ulp-pinfunc.h in in device tree source folder for all - available imx7ulp PIN_FUNC_ID. - -Optional Properties: -- drive-strength Integer. Controls Drive Strength - 0: Standard - 1: Hi Driver -- drive-push-pull Bool. Enable Pin Push-pull -- drive-open-drain Bool. Enable Pin Open-drian -- slew-rate: Integer. Controls Slew Rate - 0: Standard - 1: Slow -- bias-disable: Bool. Pull disabled -- bias-pull-down: Bool. Pull down on pin -- bias-pull-up: Bool. Pull up on pin +- compatible: "fsl,imx7ulp-iomuxc1". +- fsl,pins: Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + +CONFIG bits definition: +PAD_CTL_OBE (1 << 17) +PAD_CTL_IBE (1 << 16) +PAD_CTL_LK (1 << 16) +PAD_CTL_DSE_HI (1 << 6) +PAD_CTL_DSE_STD (0 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_PUSH_PULL (0 << 5) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_STD (0 << 2) +PAD_CTL_PE (1 << 0) Examples: #include "imx7ulp-pinfunc.h" /* Pin Controller Node */ -iomuxc1: iomuxc@40ac0000 { +iomuxc1: pinctrl@40ac0000 { compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; /* Pin Configuration Node */ pinctrl_lpuart4: lpuart4grp { - pinmux = < - IMX7ULP_PAD_PTC3__LPUART4_RX - IMX7ULP_PAD_PTC2__LPUART4_TX + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 >; - bias-pull-up; }; }; diff --git a/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt b/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt index 24a210e0c5..32a8a8fa78 100644 --- a/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl" or + "mscc,jaguar2-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/dts/Bindings/pinctrl/pinctrl-mt6797.txt b/dts/Bindings/pinctrl/pinctrl-mt6797.txt new file mode 100644 index 0000000000..bd83401e61 --- /dev/null +++ b/dts/Bindings/pinctrl/pinctrl-mt6797.txt @@ -0,0 +1,83 @@ +* MediaTek MT6797 Pin Controller + +The MediaTek's MT6797 Pin controller is used to control SoC pins. + +Required properties: +- compatible: Value should be one of the following. + "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl. +- reg: Should contain address and size for gpio, iocfgl, iocfgb, + iocfgr and iocfgt register bases. +- reg-names: An array of strings describing the "reg" entries. Must + contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt". +- gpio-controller: Marks the device node as a gpio controller. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. + +Optional properties: +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- interrupts : The interrupt outputs from the controller. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Subnode format +A pinctrl node should contain at least one subnodes representing the +pinctrl groups available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive strength, input enable/disable and input schmitt. + + node { + pinmux = ; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, + bias-pull, bias-pull-down, input-enable, input-schmitt-enable, + input-schmitt-disable, output-enable output-low, output-high, + drive-strength, and slew-rate are valid. + + Valid arguments for 'slew-rate' are '0' for no slew rate controlled and + '1' for slower slew rate respectively. Valid arguments for 'drive-strength' + is limited, such as 2, 4, 8, 12, or 16 in mA. + + Some optional vendor properties as defined are valid to specify in a + pinconf subnode: + - mediatek,tdsel: An integer describing the steps for output level shifter + duty cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + - mediatek,rdsel: An integer describing the steps for input level shifter + duty cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 63. + - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2 + or 3 for the advanced pull-up resistors. + - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2, + or 3 for the advanced pull-down resistors. + +Examples: + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6797-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x400>, + <0 0x10002400 0 0x400>, + <0 0x10002800 0 0x400>, + <0 0x10002C00 0 0x400>; + reg-names = "gpio", "iocfgl", "iocfgb", + "iocfgr", "iocfgt"; + gpio-controller; + #gpio-cells = <2>; + + uart1_pins_a: uart1 { + pins1 { + pinmux = , + ; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/pinctrl-mt7622.txt b/dts/Bindings/pinctrl/pinctrl-mt7622.txt index 3b695131c5..7a7aca1ed7 100644 --- a/dts/Bindings/pinctrl/pinctrl-mt7622.txt +++ b/dts/Bindings/pinctrl/pinctrl-mt7622.txt @@ -3,6 +3,7 @@ Required properties for the root node: - compatible: Should be one of the following "mediatek,mt7622-pinctrl" for MT7622 SoC + "mediatek,mt7629-pinctrl" for MT7629 SoC - reg: offset and length of the pinctrl space - gpio-controller: Marks the device node as a GPIO controller. @@ -324,6 +325,136 @@ group. "uart4_2_rts_cts" "uart" 95, 96 "watchdog" "watchdog" 78 + +== Valid values for pins, function and groups on MT7629 == + + Pin #: Valid values for pins + ----------------------------- + PIN 0: "TOP_5G_CLK" + PIN 1: "TOP_5G_DATA" + PIN 2: "WF0_5G_HB0" + PIN 3: "WF0_5G_HB1" + PIN 4: "WF0_5G_HB2" + PIN 5: "WF0_5G_HB3" + PIN 6: "WF0_5G_HB4" + PIN 7: "WF0_5G_HB5" + PIN 8: "WF0_5G_HB6" + PIN 9: "XO_REQ" + PIN 10: "TOP_RST_N" + PIN 11: "SYS_WATCHDOG" + PIN 12: "EPHY_LED0_N_JTDO" + PIN 13: "EPHY_LED1_N_JTDI" + PIN 14: "EPHY_LED2_N_JTMS" + PIN 15: "EPHY_LED3_N_JTCLK" + PIN 16: "EPHY_LED4_N_JTRST_N" + PIN 17: "WF2G_LED_N" + PIN 18: "WF5G_LED_N" + PIN 19: "I2C_SDA" + PIN 20: "I2C_SCL" + PIN 21: "GPIO_9" + PIN 22: "GPIO_10" + PIN 23: "GPIO_11" + PIN 24: "GPIO_12" + PIN 25: "UART1_TXD" + PIN 26: "UART1_RXD" + PIN 27: "UART1_CTS" + PIN 28: "UART1_RTS" + PIN 29: "UART2_TXD" + PIN 30: "UART2_RXD" + PIN 31: "UART2_CTS" + PIN 32: "UART2_RTS" + PIN 33: "MDI_TP_P1" + PIN 34: "MDI_TN_P1" + PIN 35: "MDI_RP_P1" + PIN 36: "MDI_RN_P1" + PIN 37: "MDI_RP_P2" + PIN 38: "MDI_RN_P2" + PIN 39: "MDI_TP_P2" + PIN 40: "MDI_TN_P2" + PIN 41: "MDI_TP_P3" + PIN 42: "MDI_TN_P3" + PIN 43: "MDI_RP_P3" + PIN 44: "MDI_RN_P3" + PIN 45: "MDI_RP_P4" + PIN 46: "MDI_RN_P4" + PIN 47: "MDI_TP_P4" + PIN 48: "MDI_TN_P4" + PIN 49: "SMI_MDC" + PIN 50: "SMI_MDIO" + PIN 51: "PCIE_PERESET_N" + PIN 52: "PWM_0" + PIN 53: "GPIO_0" + PIN 54: "GPIO_1" + PIN 55: "GPIO_2" + PIN 56: "GPIO_3" + PIN 57: "GPIO_4" + PIN 58: "GPIO_5" + PIN 59: "GPIO_6" + PIN 60: "GPIO_7" + PIN 61: "GPIO_8" + PIN 62: "SPI_CLK" + PIN 63: "SPI_CS" + PIN 64: "SPI_MOSI" + PIN 65: "SPI_MISO" + PIN 66: "SPI_WP" + PIN 67: "SPI_HOLD" + PIN 68: "UART0_TXD" + PIN 69: "UART0_RXD" + PIN 70: "TOP_2G_CLK" + PIN 71: "TOP_2G_DATA" + PIN 72: "WF0_2G_HB0" + PIN 73: "WF0_2G_HB1" + PIN 74: "WF0_2G_HB2" + PIN 75: "WF0_2G_HB3" + PIN 76: "WF0_2G_HB4" + PIN 77: "WF0_2G_HB5" + PIN 78: "WF0_2G_HB6" + +Valid values for function are: + "eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart", + "watchdog", "wifi" + +Valid values for groups are: + Valid value function pins (in pin#) + ---------------------------------------------------------------- + "mdc_mdio" "eth" 23, 24 + "i2c_0" "i2c" 19, 20 + "i2c_1" "i2c" 53, 54 + "ephy_leds" "led" 12, 13, 14, 15, 16, + 17, 18 + "ephy0_led" "led" 12 + "ephy1_led" "led" 13 + "ephy2_led" "led" 14 + "ephy3_led" "led" 15 + "ephy4_led" "led" 16 + "wf2g_led" "led" 17 + "wf5g_led" "led" 18 + "snfi" "flash" 62, 63, 64, 65, 66, 67 + "spi_nor" "flash" 62, 63, 64, 65, 66, 67 + "pcie_pereset" "pcie" 51 + "pcie_wake" "pcie" 55 + "pcie_clkreq" "pcie" 56 + "pwm_0" "pwm" 52 + "pwm_1" "pwm" 61 + "spi_0" "spi" 21, 22, 23, 24 + "spi_1" "spi" 62, 63, 64, 65 + "spi_wp" "spi" 66 + "spi_hold" "spi" 67 + "uart0_txd_rxd" "uart" 68, 69 + "uart1_0_txd_rxd" "uart" 25, 26 + "uart1_0_cts_rts" "uart" 27, 28 + "uart1_1_txd_rxd" "uart" 53, 54 + "uart1_1_cts_rts" "uart" 55, 56 + "uart2_0_txd_rxd" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 + "uart2_1_txd_rxd" "uart" 57, 58 + "uart2_1_cts_rts" "uart" 59, 60 + "watchdog" "watchdog" 11 + "wf0_2g" "wifi" 70, 71, 72, 73, 74, + 75, 76, 77, 78 + "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10 + Example: pio: pinctrl@10211000 { diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt index ab4000eab0..759aa1732e 100644 --- a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt +++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt @@ -92,7 +92,7 @@ to specify in a pin configuration subnode: gpio1-gpio26 for pm8998 gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 - gpio1-gpio11 for pms405 + gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - function: Usage: required diff --git a/dts/Bindings/pinctrl/renesas,rza2-pinctrl.txt b/dts/Bindings/pinctrl/renesas,rza2-pinctrl.txt new file mode 100644 index 0000000000..a63ccd476c --- /dev/null +++ b/dts/Bindings/pinctrl/renesas,rza2-pinctrl.txt @@ -0,0 +1,87 @@ +Renesas RZ/A2 combined Pin and GPIO controller + +The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller. +Pin multiplexing and GPIO configuration is performed on a per-pin basis. +Each port features up to 8 pins, each of them configurable for GPIO +function (port mode) or in alternate function mode. +Up to 8 different alternate function modes exist for each single pin. + +Pin controller node +------------------- + +Required properties: + - compatible: shall be: + - "renesas,r7s9210-pinctrl": for RZ/A2M + - reg + Address base and length of the memory area where the pin controller + hardware is mapped to. + - gpio-controller + This pin controller also controls pins as GPIO + - #gpio-cells + Must be 2 + - gpio-ranges + Expresses the total number of GPIO ports/pins in this SoC + +Example: Pin controller node for RZ/A2M SoC (r7s9210) + + pinctrl: pin-controller@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + }; + +Sub-nodes +--------- + +The child nodes of the pin controller designate pins to be used for +specific peripheral functions or as GPIO. + +- Pin multiplexing sub-nodes: + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + The values for the pinmux properties are a combination of port name, pin + number and the desired function index. Use the RZA2_PINMUX macro located + in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these. + For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h + to express the desired port pin. + + Required properties: + - pinmux: + integer array representing pin number and pin multiplexing configuration. + When a pin has to be configured in alternate function mode, use this + property to identify the pin by its global index, and provide its + alternate function configuration number along with it. + When multiple pins are required to be configured as part of the same + alternate function they shall be specified as members of the same + argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function identifier + are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 8 + PIN) | MUX_FUNC << 16) + + Example: Board specific pins configuration + + &pinctrl { + /* Serial Console */ + scif4_pins: serial4 { + pinmux = , /* TxD4 */ + ; /* RxD4 */ + }; + }; + + Example: Assigning a GPIO: + + leds { + status = "okay"; + compatible = "gpio-leds"; + + led0 { + /* P6_0 */ + gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt index ef4f2ff4a1..48df30a36b 100644 --- a/dts/Bindings/pinctrl/st,stm32-pinctrl.txt +++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.txt @@ -56,6 +56,7 @@ Optional properties: More details in Documentation/devicetree/bindings/gpio/gpio.txt. - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line used to select GPIOs as interrupts). + - hwlocks: reference to a phandle of a hardware spinlock provider node. Example 1: #include -- cgit v1.2.3