From eaa819409db6ac80fbd7c3d36450b2d1bec93576 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 3 Mar 2015 08:11:01 +0100 Subject: dts: update to v4.0-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/pwm/img-pwm.txt | 24 ++++++++++++++++++++++++ dts/Bindings/pwm/nvidia,tegra20-pwm.txt | 7 ++++--- dts/Bindings/pwm/pwm-sun4i.txt | 20 ++++++++++++++++++++ 3 files changed, 48 insertions(+), 3 deletions(-) create mode 100644 dts/Bindings/pwm/img-pwm.txt create mode 100644 dts/Bindings/pwm/pwm-sun4i.txt (limited to 'dts/Bindings/pwm') diff --git a/dts/Bindings/pwm/img-pwm.txt b/dts/Bindings/pwm/img-pwm.txt new file mode 100644 index 0000000000..fade5f26fc --- /dev/null +++ b/dts/Bindings/pwm/img-pwm.txt @@ -0,0 +1,24 @@ +*Imagination Technologies PWM DAC driver + +Required properties: + - compatible: Should be "img,pistachio-pwm" + - reg: Should contain physical base address and length of pwm registers. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include the following entries. + - pwm: PWM operating clock. + - sys: PWM system interface clock. + - #pwm-cells: Should be 2. See pwm.txt in this directory for the + description of the cells format. + - img,cr-periph: Must contain a phandle to the peripheral control + syscon node which contains PWM control registers. + +Example: + pwm: pwm@18101300 { + compatible = "img,pistachio-pwm"; + reg = <0x18101300 0x100>; + clocks = <&pwm_clk>, <&system_clk>; + clock-names = "pwm", "sys"; + #pwm-cells = <2>; + img,cr-periph = <&cr_periph>; + }; diff --git a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt index c7ea9d4a98..c52f03b503 100644 --- a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt +++ b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt @@ -1,9 +1,10 @@ Tegra SoC PWFM controller Required properties: -- compatible: should be one of: - - "nvidia,tegra20-pwm" - - "nvidia,tegra30-pwm" +- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30, + must contain "nvidia,tegra30-pwm". Otherwise, must contain + "nvidia,-pwm", plus one of the above, where is tegra114, + tegra124, tegra132, or tegra210. - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. diff --git a/dts/Bindings/pwm/pwm-sun4i.txt b/dts/Bindings/pwm/pwm-sun4i.txt new file mode 100644 index 0000000000..ae0273e195 --- /dev/null +++ b/dts/Bindings/pwm/pwm-sun4i.txt @@ -0,0 +1,20 @@ +Allwinner sun4i and sun7i SoC PWM controller + +Required properties: + - compatible: should be one of: + - "allwinner,sun4i-a10-pwm" + - "allwinner,sun7i-a20-pwm" + - reg: physical base address and length of the controller's registers + - #pwm-cells: should be 3. See pwm.txt in this directory for a description of + the cells format. + - clocks: From common clock binding, handle to the parent clock. + +Example: + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; -- cgit v1.2.3