From a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 10 Jan 2017 08:26:15 +0100 Subject: dts: update to v4.10-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/reset/renesas,rst.txt | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 dts/Bindings/reset/renesas,rst.txt (limited to 'dts/Bindings/reset/renesas,rst.txt') diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt new file mode 100644 index 0000000000..fe5e0f37b3 --- /dev/null +++ b/dts/Bindings/reset/renesas,rst.txt @@ -0,0 +1,37 @@ +DT bindings for the Renesas R-Car and RZ/G Reset Controllers + +The R-Car and RZ/G Reset Controllers provide reset control, and implement the +following functions: + - Latching of the levels on mode pins when PRESET# is negated, + - Mode monitoring register, + - Reset control of peripheral devices (on R-Car Gen1), + - Watchdog timer (on R-Car Gen1), + - Register-based reset control and boot address registers for the various CPU + cores (on R-Car Gen2 and Gen3, and on RZ/G). + + +Required properties: + - compatible: Should be + - "renesas,-reset-wdt" for R-Car Gen1, + - "renesas,-rst" for R-Car Gen2 and Gen3, and RZ/G + Examples with soctypes are: + - "renesas,r8a7743-rst" (RZ/G1M) + - "renesas,r8a7745-rst" (RZ/G1E) + - "renesas,r8a7778-reset-wdt" (R-Car M1A) + - "renesas,r8a7779-reset-wdt" (R-Car H1) + - "renesas,r8a7790-rst" (R-Car H2) + - "renesas,r8a7791-rst" (R-Car M2-W) + - "renesas,r8a7792-rst" (R-Car V2H + - "renesas,r8a7793-rst" (R-Car M2-N) + - "renesas,r8a7794-rst" (R-Car E2) + - "renesas,r8a7795-rst" (R-Car H3) + - "renesas,r8a7796-rst" (R-Car M3-W) + - reg: Address start and address range for the device. + + +Example: + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7795-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; -- cgit v1.2.3