From 119c632f12509eab4bc58daf629c4b16fffcedca Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 9 Nov 2020 12:38:26 +0100 Subject: dts: update to v5.10-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/riscv/cpus.yaml | 2 + dts/Bindings/riscv/sifive-l2-cache.txt | 51 ----------------- dts/Bindings/riscv/sifive-l2-cache.yaml | 98 +++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 51 deletions(-) delete mode 100644 dts/Bindings/riscv/sifive-l2-cache.txt create mode 100644 dts/Bindings/riscv/sifive-l2-cache.yaml (limited to 'dts/Bindings/riscv') diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml index f80ba2c66f..c6925e0b16 100644 --- a/dts/Bindings/riscv/cpus.yaml +++ b/dts/Bindings/riscv/cpus.yaml @@ -91,6 +91,8 @@ required: - riscv,isa - interrupt-controller +additionalProperties: true + examples: - | // Example 1: SiFive Freedom U540G Development Kit diff --git a/dts/Bindings/riscv/sifive-l2-cache.txt b/dts/Bindings/riscv/sifive-l2-cache.txt deleted file mode 100644 index 73d8f19c3b..0000000000 --- a/dts/Bindings/riscv/sifive-l2-cache.txt +++ /dev/null @@ -1,51 +0,0 @@ -SiFive L2 Cache Controller --------------------------- -The SiFive Level 2 Cache Controller is used to provide access to fast copies -of memory for masters in a Core Complex. The Level 2 Cache Controller also -acts as directory-based coherency manager. -All the properties in ePAPR/DeviceTree specification applies for this platform - -Required Properties: --------------------- -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" - -- cache-block-size: Specifies the block size in bytes of the cache. - Should be 64 - -- cache-level: Should be set to 2 for a level 2 cache - -- cache-sets: Specifies the number of associativity sets of the cache. - Should be 1024 - -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 - -- cache-unified: Specifies the cache is a unified cache - -- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) - -- reg: Physical base address and size of L2 cache controller registers map - -Optional Properties: --------------------- -- next-level-cache: phandle to the next level cache if present. - -- memory-region: reference to the reserved-memory for the L2 Loosely Integrated - Memory region. The reserved memory node should be defined as per the bindings - in reserved-memory.txt - - -Example: - - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - next-level-cache = <&L25 &L40 &L36>; - memory-region = <&l2_lim>; - }; diff --git a/dts/Bindings/riscv/sifive-l2-cache.yaml b/dts/Bindings/riscv/sifive-l2-cache.yaml new file mode 100644 index 0000000000..3f4a193955 --- /dev/null +++ b/dts/Bindings/riscv/sifive-l2-cache.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive L2 Cache Controller + +maintainers: + - Sagar Kadam + - Yash Shah + - Paul Walmsley + +description: + The SiFive Level 2 Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Level 2 Cache Controller also + acts as directory-based coherency manager. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + items: + - enum: + - sifive,fu540-c000-ccache + + required: + - compatible + +properties: + compatible: + items: + - const: sifive,fu540-c000-ccache + - const: cache + + cache-block-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + const: 2097152 + + cache-unified: true + + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + minItems: 3 + maxItems: 3 + + reg: + maxItems: 1 + + next-level-cache: true + + memory-region: + description: | + The reference to the reserved-memory for the L2 Loosely Integrated Memory region. + The reserved memory node should be defined as per the bindings in reserved-memory.txt. + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + reg = <0x2010000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <1>, + <2>, + <3>; + next-level-cache = <&L25>; + memory-region = <&l2_lim>; + }; -- cgit v1.2.3