From d14b844b08635c717fb52a294ed8d6872e260315 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 31 Jul 2017 20:03:05 +0200 Subject: dts: update to v4.13-rc2 Signed-off-by: Lucas Stach --- dts/Bindings/rtc/brcm,brcmstb-waketimer.txt | 22 ++++++++++++++++++++ dts/Bindings/rtc/cortina,gemini.txt | 14 ------------- dts/Bindings/rtc/faraday,ftrtc010.txt | 28 +++++++++++++++++++++++++ dts/Bindings/rtc/st,stm32-rtc.txt | 32 ++++++++++++++++++++++++----- 4 files changed, 77 insertions(+), 19 deletions(-) create mode 100644 dts/Bindings/rtc/brcm,brcmstb-waketimer.txt delete mode 100644 dts/Bindings/rtc/cortina,gemini.txt create mode 100644 dts/Bindings/rtc/faraday,ftrtc010.txt (limited to 'dts/Bindings/rtc') diff --git a/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt b/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt new file mode 100644 index 0000000000..1d990bcc0b --- /dev/null +++ b/dts/Bindings/rtc/brcm,brcmstb-waketimer.txt @@ -0,0 +1,22 @@ +Broadcom STB wake-up Timer + +The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the +ability to wake up the system from low-power suspend/standby modes. + +Required properties: +- compatible : should contain "brcm,brcmstb-waketimer" +- reg : the register start and length for the WKTMR block +- interrupts : The TIMER interrupt +- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2 + interrupt controller node +- clocks : The phandle to the UPG fixed clock (27Mhz domain) + +Example: + +waketimer@f0411580 { + compatible = "brcm,brcmstb-waketimer"; + reg = <0xf0411580 0x14>; + interrupts = <0x3>; + interrupt-parent = <&aon_pm_l2_intc>; + clocks = <&upg_fixed>; +}; diff --git a/dts/Bindings/rtc/cortina,gemini.txt b/dts/Bindings/rtc/cortina,gemini.txt deleted file mode 100644 index 4ce4e794dd..0000000000 --- a/dts/Bindings/rtc/cortina,gemini.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Cortina Systems Gemini RTC - -Gemini SoC real-time clock. - -Required properties: -- compatible : Should be "cortina,gemini-rtc" - -Examples: - -rtc@45000000 { - compatible = "cortina,gemini-rtc"; - reg = <0x45000000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/dts/Bindings/rtc/faraday,ftrtc010.txt b/dts/Bindings/rtc/faraday,ftrtc010.txt new file mode 100644 index 0000000000..e3938f5e0b --- /dev/null +++ b/dts/Bindings/rtc/faraday,ftrtc010.txt @@ -0,0 +1,28 @@ +* Faraday Technology FTRTC010 Real Time Clock + +This RTC appears in for example the Storlink Gemini family of +SoCs. + +Required properties: +- compatible : Should be one of: + "faraday,ftrtc010" + "cortina,gemini-rtc", "faraday,ftrtc010" + +Optional properties: +- clocks: when present should contain clock references to the + PCLK and EXTCLK clocks. Faraday calls the later CLK1HZ and + says the clock should be 1 Hz, but implementers actually seem + to choose different clocks here, like Cortina who chose + 32768 Hz (a typical low-power clock). +- clock-names: should name the clocks "PCLK" and "EXTCLK" + respectively. + +Examples: + +rtc@45000000 { + compatible = "cortina,gemini-rtc"; + reg = <0x45000000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&foo 0>, <&foo 1>; + clock-names = "PCLK", "EXTCLK"; +}; diff --git a/dts/Bindings/rtc/st,stm32-rtc.txt b/dts/Bindings/rtc/st,stm32-rtc.txt index e2837b9512..0a4c371a9b 100644 --- a/dts/Bindings/rtc/st,stm32-rtc.txt +++ b/dts/Bindings/rtc/st,stm32-rtc.txt @@ -1,17 +1,25 @@ STM32 Real Time Clock Required properties: -- compatible: "st,stm32-rtc". +- compatible: can be either "st,stm32-rtc" or "st,stm32h7-rtc", depending on + the device is compatible with stm32(f4/f7) or stm32h7. - reg: address range of rtc register set. -- clocks: reference to the clock entry ck_rtc. +- clocks: can use up to two clocks, depending on part used: + - "rtc_ck": RTC clock source. + It is required on stm32(f4/f7) and stm32h7. + - "pclk": RTC APB interface clock. + It is not present on stm32(f4/f7). + It is required on stm32h7. +- clock-names: must be "rtc_ck" and "pclk". + It is required only on stm32h7. - interrupt-parent: phandle for the interrupt controller. - interrupts: rtc alarm interrupt. - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain (RTC registers) write protection. -Optional properties (to override default ck_rtc parent clock): -- assigned-clocks: reference to the ck_rtc clock entry. -- assigned-clock-parents: phandle of the new parent clock of ck_rtc. +Optional properties (to override default rtc_ck parent clock): +- assigned-clocks: reference to the rtc_ck clock entry. +- assigned-clock-parents: phandle of the new parent clock of rtc_ck. Example: @@ -25,3 +33,17 @@ Example: interrupts = <17 1>; st,syscfg = <&pwrcfg>; }; + + rtc: rtc@58004000 { + compatible = "st,stm32h7-rtc"; + reg = <0x58004000 0x400>; + clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; + clock-names = "pclk", "rtc_ck"; + assigned-clocks = <&rcc RTC_CK>; + assigned-clock-parents = <&rcc LSE_CK>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + interrupt-names = "alarm"; + st,syscfg = <&pwrcfg>; + status = "disabled"; + }; -- cgit v1.2.3