From 461f8cfc7ea788428240271818363333ceff5c4c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 6 May 2015 08:56:43 +0200 Subject: dts: update to v4.1-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/security/tpm/st33zp24-spi.txt | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 dts/Bindings/security/tpm/st33zp24-spi.txt (limited to 'dts/Bindings/security') diff --git a/dts/Bindings/security/tpm/st33zp24-spi.txt b/dts/Bindings/security/tpm/st33zp24-spi.txt new file mode 100644 index 0000000000..158b0165e0 --- /dev/null +++ b/dts/Bindings/security/tpm/st33zp24-spi.txt @@ -0,0 +1,34 @@ +* STMicroelectronics SAS. ST33ZP24 TPM SoC + +Required properties: +- compatible: Should be "st,st33zp24-spi". +- spi-max-frequency: Maximum SPI frequency (<= 10000000). + +Optional ST33ZP24 Properties: +- interrupt-parent: phandle for the interrupt gpio controller +- interrupts: GPIO interrupt to which the chip is connected +- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state. +If set, power must be present when the platform is going into sleep/hibernate mode. + +Optional SoC Specific Properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. + +Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4): + +&mcspi4 { + + status = "okay"; + + st33zp24@0 { + + compatible = "st,st33zp24-spi"; + + spi-max-frequency = <10000000>; + + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + + lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit v1.2.3