From 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Sep 2018 08:26:30 +0200 Subject: dts: update to v4.19-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/serial/xlnx,opb-uartlite.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 dts/Bindings/serial/xlnx,opb-uartlite.txt (limited to 'dts/Bindings/serial/xlnx,opb-uartlite.txt') diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.txt b/dts/Bindings/serial/xlnx,opb-uartlite.txt new file mode 100644 index 0000000000..c37deb44de --- /dev/null +++ b/dts/Bindings/serial/xlnx,opb-uartlite.txt @@ -0,0 +1,23 @@ +Xilinx Axi Uartlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be either of + "xlnx,xps-uartlite-1.00.a" + "xlnx,opb-uartlite-1.00.b" +- reg : Physical base address and size of the Axi Uartlite + registers map. +- interrupts : Should contain the UART controller interrupt. + +Optional properties: +- port-number : Set Uart port number +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. + +Example: +serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x0 0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; +}; -- cgit v1.2.3