From 81ce4a7dec8ba066c73692e10634091b14c1e494 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 14 Feb 2020 09:05:53 +0100 Subject: dts: update to v5.6-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/serial/fsl-lpuart.txt | 2 + dts/Bindings/serial/rs485.txt | 32 +------------- dts/Bindings/serial/rs485.yaml | 45 +++++++++++++++++++ dts/Bindings/serial/st,stm32-uart.yaml | 80 ++++++++++++++++++++++++++++++++++ dts/Bindings/serial/st,stm32-usart.txt | 57 ------------------------ 5 files changed, 128 insertions(+), 88 deletions(-) create mode 100644 dts/Bindings/serial/rs485.yaml create mode 100644 dts/Bindings/serial/st,stm32-uart.yaml delete mode 100644 dts/Bindings/serial/st,stm32-usart.txt (limited to 'dts/Bindings/serial') diff --git a/dts/Bindings/serial/fsl-lpuart.txt b/dts/Bindings/serial/fsl-lpuart.txt index f5f5ab0fd1..c904e2e683 100644 --- a/dts/Bindings/serial/fsl-lpuart.txt +++ b/dts/Bindings/serial/fsl-lpuart.txt @@ -10,6 +10,8 @@ Required properties: on i.MX7ULP SoC with 32-bit little-endian register organization - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated on i.MX8QXP SoC with 32-bit little-endian register organization + - "fsl,imx8qm-lpuart" for lpuart compatible with the one integrated + on i.MX8QM SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names diff --git a/dts/Bindings/serial/rs485.txt b/dts/Bindings/serial/rs485.txt index b92592dff6..a7fe93efc4 100644 --- a/dts/Bindings/serial/rs485.txt +++ b/dts/Bindings/serial/rs485.txt @@ -1,31 +1 @@ -* RS485 serial communications - -The RTS signal is capable of automatically controlling line direction for -the built-in half-duplex mode. -The properties described hereafter shall be given to a half-duplex capable -UART node. - -Optional properties: -- rs485-rts-delay: prop-encoded-array where: - * a is the delay between rts signal and beginning of data sent in milliseconds. - it corresponds to the delay before sending data. - * b is the delay between end of data sent and rts signal in milliseconds - it corresponds to the delay after sending data and actual release of the line. - If this property is not specified, <0 0> is assumed. -- rs485-rts-active-low: drive RTS low when sending (default is high). -- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 - feature at boot time. It can be disabled later with proper ioctl. -- rs485-rx-during-tx: empty property that enables the receiving of data even - while sending data. - -RS485 example for Atmel USART: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - atmel,use-dma-rx; - atmel,use-dma-tx; - linux,rs485-enabled-at-boot-time; - rs485-rts-delay = <0 200>; // in milliseconds - }; - +See rs485.yaml diff --git a/dts/Bindings/serial/rs485.yaml b/dts/Bindings/serial/rs485.yaml new file mode 100644 index 0000000000..d4beaf1122 --- /dev/null +++ b/dts/Bindings/serial/rs485.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/rs485.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RS485 serial communications Bindings + +description: The RTS signal is capable of automatically controlling + line direction for the built-in half-duplex mode. + The properties described hereafter shall be given to a + half-duplex capable UART node. + +maintainers: + - Rob Herring + +properties: + rs485-rts-delay: + description: prop-encoded-array + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + items: + - description: + Delay between rts signal and beginning of data sent in milliseconds. + It corresponds to the delay before sending data. + default: 0 + maximum: 1000 + - description: + Delay between end of data sent and rts signal in milliseconds. + It corresponds to the delay after sending data and actual release of the line. + default: 0 + maximum: 1000 + + rs485-rts-active-low: + description: drive RTS low when sending (default is high). + $ref: /schemas/types.yaml#/definitions/flag + + linux,rs485-enabled-at-boot-time: + description: enables the rs485 feature at boot time. It can be disabled later with proper ioctl. + $ref: /schemas/types.yaml#/definitions/flag + + rs485-rx-during-tx: + description: enables the receiving of data even while sending data. + $ref: /schemas/types.yaml#/definitions/flag diff --git a/dts/Bindings/serial/st,stm32-uart.yaml b/dts/Bindings/serial/st,stm32-uart.yaml new file mode 100644 index 0000000000..238c44192d --- /dev/null +++ b/dts/Bindings/serial/st,stm32-uart.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Erwan Le Ray + +title: STMicroelectronics STM32 USART bindings + +allOf: + - $ref: rs485.yaml + +properties: + compatible: + enum: + - st,stm32-uart + - st,stm32f7-uart + - st,stm32h7-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + label: + description: label associated with this uart + + st,hw-flow-ctrl: + description: enable hardware flow control + $ref: /schemas/types.yaml#/definitions/flag + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + items: + enum: [ rx, tx ] + minItems: 1 + maxItems: 2 + + wakeup-source: true + + rs485-rts-delay: true + rs485-rts-active-low: true + linux,rs485-enabled-at-boot-time: true + rs485-rx-during-tx: true + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + usart1: serial@40011000 { + compatible = "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + dmas = <&dma2 2 4 0x414 0x0>, + <&dma2 7 4 0x414 0x0>; + dma-names = "rx", "tx"; + rs485-rts-active-low; + }; + +... diff --git a/dts/Bindings/serial/st,stm32-usart.txt b/dts/Bindings/serial/st,stm32-usart.txt deleted file mode 100644 index 8620f7fcbd..0000000000 --- a/dts/Bindings/serial/st,stm32-usart.txt +++ /dev/null @@ -1,57 +0,0 @@ -* STMicroelectronics STM32 USART - -Required properties: -- compatible: can be either: - - "st,stm32-uart", - - "st,stm32f7-uart", - - "st,stm32h7-uart". - depending is compatible with stm32(f4), stm32f7 or stm32h7. -- reg: The address and length of the peripheral registers space -- interrupts: - - The interrupt line for the USART instance, - - An optional wake-up interrupt. -- clocks: The input clock of the USART instance - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- pinctrl: The reference on the pins configuration -- st,hw-flow-ctrl: bool flag to enable hardware flow control. -- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low, - linux,rs485-enabled-at-boot-time: see rs485.txt. -- dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt -- dma-names: "rx" and/or "tx" -- wakeup-source: bool flag to indicate this device has wakeup capabilities -- interrupt-names, if optional wake-up interrupt is used, should be: - - "event": the name for the interrupt line of the USART instance - - "wakeup" the name for the optional wake-up interrupt - - -Examples: -usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&clk_pclk1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart4>; -}; - -usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&clk_pclk1>; - st,hw-flow-ctrl; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rtscts>; -}; - -usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 164>; - dmas = <&dma2 2 4 0x414 0x0>, - <&dma2 7 4 0x414 0x0>; - dma-names = "rx", "tx"; -}; -- cgit v1.2.3