From d14b844b08635c717fb52a294ed8d6872e260315 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 31 Jul 2017 20:03:05 +0200 Subject: dts: update to v4.13-rc2 Signed-off-by: Lucas Stach --- dts/Bindings/spi/spi-meson.txt | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'dts/Bindings/spi/spi-meson.txt') diff --git a/dts/Bindings/spi/spi-meson.txt b/dts/Bindings/spi/spi-meson.txt index dc6d031332..825c39cae7 100644 --- a/dts/Bindings/spi/spi-meson.txt +++ b/dts/Bindings/spi/spi-meson.txt @@ -20,3 +20,34 @@ Required properties: #address-cells = <1>; #size-cells = <0>; }; + +* SPICC (SPI Communication Controller) + +The Meson SPICC is generic SPI controller for general purpose Full-Duplex +communications with dedicated 16 words RX/TX PIO FIFOs. + +Required properties: + - compatible: should be "amlogic,meson-gx-spicc" on Amlogic GX SoCs. + - reg: physical base address and length of the controller registers + - interrupts: The interrupt specifier + - clock-names: Must contain "core" + - clocks: phandle of the input clock for the baud rate generator + - #address-cells: should be 1 + - #size-cells: should be 0 + +Optional properties: + - resets: phandle of the internal reset line + +See ../spi/spi-bus.txt for more details on SPI bus master and slave devices +required and optional properties. + +Example : + spi@c1108d80 { + compatible = "amlogic,meson-gx-spicc"; + reg = <0xc1108d80 0x80>; + interrupts = ; + clock-names = "core"; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + }; -- cgit v1.2.3