From 3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 17 Nov 2021 07:36:09 +0100 Subject: dts: update to v5.16-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/Makefile | 20 +- dts/Bindings/arm/amlogic.yaml | 3 + dts/Bindings/arm/arm,cci-400.yaml | 216 ++++++++++ dts/Bindings/arm/arm,vexpress-juno.yaml | 46 ++- dts/Bindings/arm/atmel-at91.yaml | 24 ++ dts/Bindings/arm/bcm/bcm2835.yaml | 1 + dts/Bindings/arm/bcm/brcm,nsp.yaml | 65 ++- dts/Bindings/arm/cci-control-port.yaml | 38 ++ dts/Bindings/arm/cci.txt | 224 ----------- dts/Bindings/arm/coresight.txt | 5 + dts/Bindings/arm/cpus.yaml | 10 +- .../arm/firmware/tlm,trusted-foundations.txt | 20 - .../arm/firmware/tlm,trusted-foundations.yaml | 46 +++ dts/Bindings/arm/fsl.yaml | 99 +++-- dts/Bindings/arm/mediatek.yaml | 1 + dts/Bindings/arm/mediatek/mediatek,mmsys.yaml | 4 + .../arm/mediatek/mediatek,mt8195-clock.yaml | 254 ++++++++++++ .../arm/mediatek/mediatek,mt8195-sys-clock.yaml | 73 ++++ dts/Bindings/arm/qcom.yaml | 23 ++ dts/Bindings/arm/renesas.yaml | 61 +++ dts/Bindings/arm/rockchip.yaml | 48 ++- dts/Bindings/arm/rockchip/pmu.yaml | 4 + dts/Bindings/arm/samsung/exynos-chipid.yaml | 5 +- dts/Bindings/arm/samsung/samsung-boards.yaml | 6 + dts/Bindings/arm/sprd/sprd.yaml | 5 + dts/Bindings/arm/sti.yaml | 2 +- dts/Bindings/arm/stm32/st,mlahb.yaml | 4 +- dts/Bindings/arm/stm32/st,stm32-syscon.yaml | 4 +- dts/Bindings/arm/stm32/stm32.yaml | 6 +- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 1 + .../arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml | 38 ++ .../arm/sunxi/allwinner,sun9i-a80-prcm.yaml | 33 ++ dts/Bindings/arm/ti/k3.yaml | 15 +- dts/Bindings/arm/toshiba.yaml | 1 + dts/Bindings/arm/xilinx.yaml | 17 + dts/Bindings/auxdisplay/holtek,ht16k33.yaml | 32 +- dts/Bindings/bus/palmbus.yaml | 79 ++++ dts/Bindings/bus/ti-sysc.txt | 139 ------- dts/Bindings/bus/ti-sysc.yaml | 216 ++++++++++ .../clock/allwinner,sun8i-a83t-de2-clk.yaml | 2 +- dts/Bindings/clock/arm,syscon-icst.yaml | 5 + dts/Bindings/clock/fixed-mmio-clock.txt | 24 -- dts/Bindings/clock/fixed-mmio-clock.yaml | 47 +++ dts/Bindings/clock/imx8ulp-cgc-clock.yaml | 43 ++ dts/Bindings/clock/imx8ulp-pcc-clock.yaml | 50 +++ dts/Bindings/clock/ingenic,cgu.yaml | 2 +- dts/Bindings/clock/maxim,max77686.txt | 4 +- dts/Bindings/clock/qcom,dispcc-sm8x50.yaml | 13 + dts/Bindings/clock/qcom,gcc-msm8994.yaml | 70 ++++ dts/Bindings/clock/qcom,gcc-msm8998.yaml | 26 +- dts/Bindings/clock/qcom,gcc-qcm2290.yaml | 72 ++++ dts/Bindings/clock/qcom,gcc.yaml | 2 - dts/Bindings/clock/qcom,rpmcc.txt | 1 + dts/Bindings/clock/qcom,sc7280-camcc.yaml | 71 ++++ dts/Bindings/clock/qcom,sc7280-lpasscc.yaml | 68 ++++ dts/Bindings/clock/qcom,videocc.yaml | 13 + dts/Bindings/clock/samsung,exynos850-clock.yaml | 185 +++++++++ dts/Bindings/clock/samsung,s2mps11.txt | 49 --- dts/Bindings/clock/samsung,s2mps11.yaml | 45 +++ dts/Bindings/clock/sifive/fu740-prci.yaml | 4 + dts/Bindings/clock/silabs,si5351.txt | 2 +- dts/Bindings/clock/socionext,uniphier-clock.yaml | 6 + dts/Bindings/clock/st,stm32mp1-rcc.yaml | 2 +- dts/Bindings/clock/stericsson,u8500-clks.yaml | 121 ++++++ dts/Bindings/clock/ux500.txt | 64 --- dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml | 47 +++ dts/Bindings/crypto/st,stm32-crc.yaml | 2 +- dts/Bindings/crypto/st,stm32-cryp.yaml | 2 +- dts/Bindings/crypto/st,stm32-hash.yaml | 2 +- dts/Bindings/ddr/lpddr2-timings.txt | 52 --- dts/Bindings/ddr/lpddr2.txt | 102 ----- dts/Bindings/ddr/lpddr3-timings.txt | 58 --- dts/Bindings/ddr/lpddr3.txt | 106 ----- dts/Bindings/devfreq/rk3399_dmc.txt | 2 +- dts/Bindings/display/brcm,bcm2835-dsi0.yaml | 3 + dts/Bindings/display/brcm,bcm2835-hdmi.yaml | 3 + dts/Bindings/display/brcm,bcm2835-v3d.yaml | 3 + dts/Bindings/display/brcm,bcm2835-vec.yaml | 3 + dts/Bindings/display/bridge/lvds-codec.yaml | 33 +- dts/Bindings/display/bridge/ps8640.yaml | 19 +- dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml | 2 +- dts/Bindings/display/bridge/toshiba,tc358767.txt | 54 --- dts/Bindings/display/bridge/toshiba,tc358767.yaml | 158 ++++++++ dts/Bindings/display/ingenic,ipu.yaml | 2 +- dts/Bindings/display/ingenic,lcd.yaml | 4 +- dts/Bindings/display/mediatek/mediatek,dsi.txt | 6 + dts/Bindings/display/msm/dp-controller.yaml | 16 +- dts/Bindings/display/msm/dpu-sc7280.yaml | 232 +++++++++++ dts/Bindings/display/msm/dsi-phy-14nm.yaml | 1 + dts/Bindings/display/msm/gpu.txt | 157 -------- dts/Bindings/display/msm/gpu.yaml | 288 +++++++++++++ dts/Bindings/display/panel/boe,tv101wum-nl6.yaml | 7 + dts/Bindings/display/panel/orisetech,otm8009a.yaml | 2 +- dts/Bindings/display/panel/panel-edp.yaml | 188 +++++++++ dts/Bindings/display/panel/panel-simple.yaml | 5 + dts/Bindings/display/panel/raydium,rm68200.yaml | 2 +- dts/Bindings/display/panel/samsung,s6d27a1.yaml | 98 +++++ dts/Bindings/display/panel/sharp,ls060t1sx01.yaml | 56 +++ dts/Bindings/display/renesas,du.yaml | 51 +++ dts/Bindings/display/st,stm32-dsi.yaml | 4 +- dts/Bindings/display/st,stm32-ltdc.yaml | 4 +- dts/Bindings/display/tilcdc/tilcdc.txt | 4 +- dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml | 4 +- dts/Bindings/display/xylon,logicvc-display.yaml | 301 ++++++++++++++ dts/Bindings/dma/ingenic,dma.yaml | 2 +- dts/Bindings/dma/qcom_bam_dma.txt | 2 + dts/Bindings/dma/st,stm32-dma.yaml | 2 +- dts/Bindings/dma/st,stm32-dmamux.yaml | 2 +- dts/Bindings/dma/st,stm32-mdma.yaml | 2 +- dts/Bindings/dsp/fsl,dsp.yaml | 123 +++++- dts/Bindings/eeprom/at24.yaml | 6 + dts/Bindings/example-schema.yaml | 14 +- dts/Bindings/extcon/extcon-usbc-tusb320.yaml | 4 +- dts/Bindings/firmware/qcom,scm.txt | 4 +- dts/Bindings/gnss/u-blox,neo-6m.yaml | 62 +++ dts/Bindings/gnss/u-blox.txt | 45 --- dts/Bindings/gpio/gpio-axp209.txt | 75 ---- dts/Bindings/gpio/gpio-xlp.txt | 49 --- dts/Bindings/gpio/rockchip,gpio-bank.yaml | 2 + dts/Bindings/gpio/x-powers,axp209-gpio.yaml | 55 +++ dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 43 ++ dts/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml | 106 +++++ dts/Bindings/hwlock/st,stm32-hwspinlock.yaml | 3 +- dts/Bindings/hwmon/dps650ab.txt | 11 - dts/Bindings/hwmon/hih6130.txt | 12 - dts/Bindings/hwmon/ibm,cffps1.txt | 26 -- dts/Bindings/hwmon/iio-hwmon.yaml | 37 ++ dts/Bindings/hwmon/jc42.txt | 46 --- dts/Bindings/hwmon/jedec,jc42.yaml | 78 ++++ dts/Bindings/hwmon/lltc,ltc4151.yaml | 41 ++ dts/Bindings/hwmon/lm70.txt | 22 - dts/Bindings/hwmon/lm90.txt | 51 --- dts/Bindings/hwmon/ltc4151.txt | 18 - dts/Bindings/hwmon/mcp3021.txt | 21 - dts/Bindings/hwmon/microchip,mcp3021.yaml | 43 ++ dts/Bindings/hwmon/national,lm90.yaml | 78 ++++ dts/Bindings/hwmon/ntc-thermistor.yaml | 141 +++++++ dts/Bindings/hwmon/ntc_thermistor.txt | 44 -- dts/Bindings/hwmon/nuvoton,nct7802.yaml | 145 +++++++ dts/Bindings/hwmon/pmbus/ti,lm25066.yaml | 54 +++ dts/Bindings/hwmon/sensirion,sht15.yaml | 43 ++ dts/Bindings/hwmon/sht15.txt | 19 - dts/Bindings/hwmon/ti,tmp102.yaml | 47 +++ dts/Bindings/hwmon/ti,tmp108.yaml | 50 +++ dts/Bindings/hwmon/ti,tmp421.yaml | 110 +++++ dts/Bindings/hwmon/tmp108.txt | 18 - dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml | 2 +- dts/Bindings/i2c/apple,i2c.yaml | 61 +++ dts/Bindings/i2c/i2c-imx.yaml | 4 +- dts/Bindings/i2c/i2c-xlp9xx.txt | 22 - dts/Bindings/i2c/ingenic,i2c.yaml | 2 +- dts/Bindings/i2c/st,stm32-i2c.yaml | 2 +- dts/Bindings/iio/accel/adi,adxl313.yaml | 86 ++++ dts/Bindings/iio/accel/adi,adxl355.yaml | 88 ++++ dts/Bindings/iio/accel/kionix,kxcjk1013.yaml | 3 + dts/Bindings/iio/adc/adi,ad7949.yaml | 51 ++- dts/Bindings/iio/adc/adi,ad799x.yaml | 73 ++++ dts/Bindings/iio/adc/aspeed,ast2600-adc.yaml | 100 +++++ dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 + dts/Bindings/iio/adc/ingenic,adc.yaml | 2 +- dts/Bindings/iio/adc/nxp,imx8qxp-adc.yaml | 78 ++++ dts/Bindings/iio/adc/sigma-delta-modulator.yaml | 2 +- dts/Bindings/iio/adc/st,stm32-adc.yaml | 110 ++++- dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 +- dts/Bindings/iio/adc/ti,am3359-adc.yaml | 70 ++++ dts/Bindings/iio/chemical/senseair,sunrise.yaml | 55 +++ dts/Bindings/iio/chemical/sensirion,scd4x.yaml | 46 +++ dts/Bindings/iio/dac/adi,ad5766.yaml | 2 +- dts/Bindings/iio/dac/st,stm32-dac.yaml | 2 +- dts/Bindings/iio/frequency/adi,adrf6780.yaml | 131 ++++++ dts/Bindings/iio/light/liteon,ltr501.yaml | 51 +++ .../iio/magnetometer/asahi-kasei,ak8975.yaml | 7 + dts/Bindings/iio/multiplexer/io-channel-mux.yaml | 13 +- dts/Bindings/iio/temperature/maxim,max31865.yaml | 52 +++ dts/Bindings/input/cap11xx.txt | 78 ---- dts/Bindings/input/cypress-sf.yaml | 61 +++ dts/Bindings/input/elan,ekth3000.yaml | 81 ++++ dts/Bindings/input/elan_i2c.txt | 44 -- dts/Bindings/input/microchip,cap11xx.yaml | 149 +++++++ dts/Bindings/input/touchscreen/silead,gsl1680.yaml | 91 +++++ dts/Bindings/input/touchscreen/silead_gsl1680.txt | 44 -- dts/Bindings/input/touchscreen/ti,am3359-tsc.yaml | 76 ++++ dts/Bindings/input/touchscreen/ti-tsc-adc.txt | 91 ----- .../interrupt-controller/microchip,eic.yaml | 73 ++++ .../interrupt-controller/msi-controller.yaml | 46 +++ .../interrupt-controller/renesas,irqc.yaml | 1 + .../interrupt-controller/st,stm32-exti.yaml | 4 +- dts/Bindings/iommu/arm,smmu.yaml | 2 + dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml | 1 + dts/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 1 + dts/Bindings/ipmi/ipmi-ipmb.yaml | 59 +++ dts/Bindings/leds/register-bit-led.txt | 94 ----- dts/Bindings/leds/register-bit-led.yaml | 95 +++++ dts/Bindings/mailbox/apple,mailbox.yaml | 77 ++++ dts/Bindings/mailbox/fsl,mu.yaml | 1 + dts/Bindings/mailbox/mtk-gce.txt | 4 +- dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml | 3 +- dts/Bindings/mailbox/st,stm32-ipcc.yaml | 4 +- dts/Bindings/media/i2c/adv7604.yaml | 13 +- dts/Bindings/media/i2c/aptina,mt9p031.yaml | 108 +++++ dts/Bindings/media/i2c/hynix,hi846.yaml | 120 ++++++ dts/Bindings/media/i2c/mt9p031.txt | 40 -- dts/Bindings/media/i2c/ov5640.txt | 92 ----- dts/Bindings/media/i2c/ovti,ov5640.yaml | 154 +++++++ dts/Bindings/media/mediatek-vcodec.txt | 2 + dts/Bindings/media/qcom,sc7280-venus.yaml | 161 ++++++++ dts/Bindings/media/qcom,sdm660-venus.yaml | 186 +++++++++ dts/Bindings/media/renesas,csi2.yaml | 1 + dts/Bindings/media/renesas,imr.txt | 31 -- dts/Bindings/media/renesas,imr.yaml | 67 ++++ dts/Bindings/media/rockchip-isp1.yaml | 114 +++++- dts/Bindings/media/st,stm32-cec.yaml | 3 +- dts/Bindings/media/st,stm32-dcmi.yaml | 2 +- dts/Bindings/media/ti,cal.yaml | 4 +- .../memory-controllers/ddr/jedec,lpddr2.yaml | 223 +++++++++++ .../memory-controllers/ddr/lpddr2-timings.txt | 52 +++ .../memory-controllers/ddr/lpddr3-timings.txt | 58 +++ dts/Bindings/memory-controllers/ddr/lpddr3.txt | 107 +++++ dts/Bindings/memory-controllers/fsl/ddr.txt | 29 -- dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml | 83 ++++ dts/Bindings/memory-controllers/ingenic,nemc.yaml | 2 +- .../memory-controllers/mediatek,mt7621-memc.yaml | 30 ++ .../memory-controllers/mediatek,smi-common.yaml | 34 +- .../memory-controllers/mediatek,smi-larb.yaml | 3 + .../memory-controllers/nvidia,tegra20-emc.yaml | 23 +- dts/Bindings/memory-controllers/omap-gpmc.txt | 157 -------- .../memory-controllers/renesas,rpc-if.yaml | 1 + .../memory-controllers/samsung,exynos5422-dmc.yaml | 3 +- .../memory-controllers/st,stm32-fmc2-ebi.yaml | 2 +- dts/Bindings/memory-controllers/ti,gpmc-child.yaml | 245 ++++++++++++ dts/Bindings/memory-controllers/ti,gpmc.yaml | 172 ++++++++ dts/Bindings/mfd/ac100.txt | 50 --- dts/Bindings/mfd/aspeed-lpc.txt | 157 -------- dts/Bindings/mfd/aspeed-lpc.yaml | 199 +++++++++ dts/Bindings/mfd/axp20x.txt | 273 ------------- dts/Bindings/mfd/brcm,cru.yaml | 21 + dts/Bindings/mfd/brcm,misc.yaml | 60 +++ dts/Bindings/mfd/max14577.txt | 4 +- dts/Bindings/mfd/max77686.txt | 2 +- dts/Bindings/mfd/max77693.txt | 2 +- dts/Bindings/mfd/qcom,spmi-pmic.txt | 39 +- dts/Bindings/mfd/qcom,tcsr.txt | 1 + dts/Bindings/mfd/qcom-pm8xxx.yaml | 1 + dts/Bindings/mfd/samsung,s2mpa01.yaml | 91 +++++ dts/Bindings/mfd/samsung,s2mps11.yaml | 267 +++++++++++++ dts/Bindings/mfd/samsung,s5m8767.yaml | 307 ++++++++++++++ dts/Bindings/mfd/samsung,sec-core.txt | 86 ---- dts/Bindings/mfd/st,stm32-lptimer.yaml | 2 +- dts/Bindings/mfd/st,stm32-timers.yaml | 3 +- dts/Bindings/mfd/st,stmfx.yaml | 2 +- dts/Bindings/mfd/st,stpmic1.yaml | 2 +- dts/Bindings/mfd/syscon.yaml | 3 + dts/Bindings/mfd/ti,am3359-tscadc.yaml | 84 ++++ dts/Bindings/mfd/x-powers,ac100.yaml | 116 ++++++ dts/Bindings/mfd/x-powers,axp152.yaml | 400 ++++++++++++++++++ dts/Bindings/mfd/xylon,logicvc.yaml | 3 + dts/Bindings/mips/ingenic/ingenic,cpu.yaml | 2 +- dts/Bindings/mips/ralink.txt | 32 -- dts/Bindings/mips/ralink.yaml | 87 ++++ dts/Bindings/mmc/arasan,sdhci.yaml | 26 +- dts/Bindings/mmc/cdns,sdhci.yaml | 1 + dts/Bindings/mmc/fsl-imx-esdhc.yaml | 1 + dts/Bindings/mmc/ingenic,mmc.yaml | 2 +- dts/Bindings/mmc/mmc-card.txt | 30 -- dts/Bindings/mmc/mmc-card.yaml | 48 +++ dts/Bindings/mmc/mmc-controller.yaml | 6 - dts/Bindings/mmc/mtk-sd.yaml | 12 + dts/Bindings/mmc/sdhci-msm.txt | 1 + dts/Bindings/mmc/sdhci-omap.txt | 9 +- dts/Bindings/mtd/gpmc-nand.txt | 147 ------- dts/Bindings/mtd/gpmc-nor.txt | 98 ----- dts/Bindings/mtd/gpmc-onenand.txt | 48 --- dts/Bindings/mtd/ingenic,nand.yaml | 2 +- dts/Bindings/mtd/st,stm32-fmc2-nand.yaml | 2 +- dts/Bindings/mtd/ti,gpmc-nand.yaml | 121 ++++++ dts/Bindings/mtd/ti,gpmc-onenand.yaml | 81 ++++ dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml | 4 +- dts/Bindings/net/asix,ax88796c.yaml | 73 ++++ dts/Bindings/net/brcm,bcmgenet.txt | 3 +- dts/Bindings/net/broadcom-bluetooth.yaml | 17 +- dts/Bindings/net/dsa/dsa.yaml | 12 +- dts/Bindings/net/dsa/nxp,sja1105.yaml | 43 ++ dts/Bindings/net/dsa/qca8k.txt | 215 ---------- dts/Bindings/net/dsa/qca8k.yaml | 362 +++++++++++++++++ dts/Bindings/net/dsa/realtek-smi.txt | 87 ++++ dts/Bindings/net/gpmc-eth.txt | 97 ----- dts/Bindings/net/ingenic,mac.yaml | 2 +- dts/Bindings/net/lantiq,etop-xway.yaml | 69 ++++ dts/Bindings/net/lantiq,xrx200-net.txt | 21 - dts/Bindings/net/lantiq,xrx200-net.yaml | 59 +++ dts/Bindings/net/macb.txt | 4 + dts/Bindings/net/marvell-bluetooth.txt | 25 -- dts/Bindings/net/marvell-bluetooth.yaml | 31 ++ dts/Bindings/net/nfc/marvell,nci.yaml | 170 ++++++++ dts/Bindings/net/nfc/nfcmrvl.txt | 84 ---- dts/Bindings/net/nfc/nxp,nci.yaml | 61 +++ dts/Bindings/net/nfc/nxp,pn532.yaml | 65 +++ dts/Bindings/net/nfc/nxp,pn544.yaml | 58 +++ dts/Bindings/net/nfc/nxp-nci.txt | 33 -- dts/Bindings/net/nfc/pn532.txt | 46 --- dts/Bindings/net/nfc/pn544.txt | 33 -- dts/Bindings/net/nfc/st,st-nci.yaml | 106 +++++ dts/Bindings/net/nfc/st,st21nfca.yaml | 64 +++ dts/Bindings/net/nfc/st,st95hf.yaml | 57 +++ dts/Bindings/net/nfc/st-nci-i2c.txt | 38 -- dts/Bindings/net/nfc/st-nci-spi.txt | 36 -- dts/Bindings/net/nfc/st21nfca.txt | 37 -- dts/Bindings/net/nfc/st95hf.txt | 45 --- dts/Bindings/net/nfc/ti,trf7970a.yaml | 98 +++++ dts/Bindings/net/nfc/trf7970a.txt | 43 -- dts/Bindings/net/qcom,ipa.yaml | 3 +- dts/Bindings/net/qcom,ipq8064-mdio.yaml | 5 +- dts/Bindings/net/realtek-bluetooth.yaml | 2 + dts/Bindings/net/renesas,ether.yaml | 17 +- dts/Bindings/net/renesas,etheravb.yaml | 3 + dts/Bindings/net/snps,dwmac.yaml | 8 +- dts/Bindings/net/socionext,uniphier-ave4.yaml | 1 + dts/Bindings/net/stm32-dwmac.yaml | 4 +- dts/Bindings/net/ti,bluetooth.yaml | 92 +++++ dts/Bindings/net/ti-bluetooth.txt | 60 --- dts/Bindings/net/wireless/esp,esp8089.txt | 30 -- dts/Bindings/net/wireless/esp,esp8089.yaml | 43 ++ dts/Bindings/net/wireless/mediatek,mt76.yaml | 5 + dts/Bindings/net/wireless/qca,ath9k.txt | 48 --- dts/Bindings/net/wireless/qca,ath9k.yaml | 90 +++++ dts/Bindings/net/wireless/ti,wlcore,spi.txt | 57 --- dts/Bindings/net/wireless/ti,wlcore.txt | 45 --- dts/Bindings/net/wireless/ti,wlcore.yaml | 134 +++++++ dts/Bindings/numa.txt | 46 ++- dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml | 2 +- dts/Bindings/nvmem/st,stm32-romem.yaml | 2 +- dts/Bindings/opp/opp-v2-base.yaml | 2 +- dts/Bindings/pci/apple,pcie.yaml | 160 ++++++++ dts/Bindings/pci/brcm,stb-pcie.yaml | 1 + dts/Bindings/pci/mediatek,mt7621-pcie.yaml | 142 +++++++ dts/Bindings/pci/microchip,pcie-host.yaml | 1 + dts/Bindings/pci/nvidia,tegra194-pcie.txt | 2 +- dts/Bindings/pci/qcom,pcie-ep.yaml | 158 ++++++++ dts/Bindings/pci/qcom,pcie.txt | 5 +- dts/Bindings/pci/rcar-pci-ep.yaml | 1 + dts/Bindings/pci/rockchip-dw-pcie.yaml | 141 +++++++ dts/Bindings/phy/bcm-ns-usb2-phy.yaml | 25 +- dts/Bindings/phy/ingenic,phy-usb.yaml | 2 +- dts/Bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- dts/Bindings/phy/nvidia,tegra20-usb-phy.yaml | 373 +++++++++++++++++ dts/Bindings/phy/phy-stm32-usbphyc.yaml | 131 +++++- dts/Bindings/phy/qcom,qmp-phy.yaml | 84 ++-- dts/Bindings/phy/qcom,qusb2-phy.yaml | 7 + dts/Bindings/phy/rockchip-usb-phy.yaml | 11 +- dts/Bindings/pinctrl/apple,pinctrl.yaml | 10 + dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 363 +++++++++++++++++ dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml | 7 + dts/Bindings/pinctrl/pinctrl-mt8195.yaml | 86 +++- dts/Bindings/pinctrl/qcom,pmic-gpio.yaml | 4 + dts/Bindings/pinctrl/qcom,pmic-mpp.txt | 187 --------- dts/Bindings/pinctrl/qcom,pmic-mpp.yaml | 188 +++++++++ dts/Bindings/pinctrl/qcom,qcm2290-pinctrl.yaml | 165 ++++++++ dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml | 148 +++++++ dts/Bindings/pinctrl/rockchip,pinctrl.txt | 114 ------ dts/Bindings/pinctrl/rockchip,pinctrl.yaml | 184 +++++++++ dts/Bindings/pinctrl/samsung-pinctrl.txt | 1 + .../pinctrl/socionext,uniphier-pinctrl.yaml | 1 + dts/Bindings/pinctrl/st,stm32-pinctrl.yaml | 2 +- dts/Bindings/power/qcom,rpmpd.yaml | 2 + dts/Bindings/power/supply/maxim,max17040.yaml | 2 +- dts/Bindings/power/supply/samsung,battery.yaml | 56 +++ .../power/supply/stericsson,ab8500-btemp.yaml | 10 +- .../power/supply/stericsson,ab8500-chargalg.yaml | 10 +- .../power/supply/stericsson,ab8500-charger.yaml | 10 +- .../power/supply/stericsson,ab8500-fg.yaml | 10 +- dts/Bindings/pwm/renesas,tpu-pwm.yaml | 2 + dts/Bindings/regulator/max77686.txt | 2 +- dts/Bindings/regulator/max8952.txt | 52 --- dts/Bindings/regulator/max8973-regulator.txt | 52 --- dts/Bindings/regulator/max8997-regulator.txt | 145 ------- dts/Bindings/regulator/maxim,max8952.yaml | 109 +++++ dts/Bindings/regulator/maxim,max8973.yaml | 139 +++++++ dts/Bindings/regulator/maxim,max8997.yaml | 445 +++++++++++++++++++++ dts/Bindings/regulator/qcom,rpmh-regulator.yaml | 2 + dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml | 4 + dts/Bindings/regulator/samsung,s2mpa01.txt | 79 ---- dts/Bindings/regulator/samsung,s2mpa01.yaml | 62 +++ dts/Bindings/regulator/samsung,s2mps11.txt | 102 ----- dts/Bindings/regulator/samsung,s2mps11.yaml | 44 ++ dts/Bindings/regulator/samsung,s2mps13.yaml | 44 ++ dts/Bindings/regulator/samsung,s2mps14.yaml | 44 ++ dts/Bindings/regulator/samsung,s2mps15.yaml | 44 ++ dts/Bindings/regulator/samsung,s2mpu02.yaml | 44 ++ dts/Bindings/regulator/samsung,s5m8767.txt | 145 ------- dts/Bindings/regulator/samsung,s5m8767.yaml | 74 ++++ dts/Bindings/regulator/silergy,sy8106a.yaml | 52 +++ .../regulator/socionext,uniphier-regulator.yaml | 1 + dts/Bindings/regulator/st,stm32-booster.yaml | 2 +- dts/Bindings/regulator/st,stm32-vrefbuf.yaml | 2 +- dts/Bindings/regulator/st,stm32mp1-pwr-reg.yaml | 2 +- dts/Bindings/regulator/sy8106a-regulator.txt | 23 -- .../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 ++++ dts/Bindings/remoteproc/ingenic,vpu.yaml | 2 +- dts/Bindings/remoteproc/mtk,scp.txt | 36 -- dts/Bindings/remoteproc/mtk,scp.yaml | 92 +++++ dts/Bindings/remoteproc/qcom,adsp.yaml | 59 ++- dts/Bindings/remoteproc/qcom,q6v5.txt | 39 +- dts/Bindings/remoteproc/st,stm32-rproc.yaml | 4 +- dts/Bindings/remoteproc/ti,k3-dsp-rproc.yaml | 4 +- dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml | 4 +- dts/Bindings/reserved-memory/memory-region.yaml | 40 ++ dts/Bindings/reserved-memory/ramoops.txt | 66 --- dts/Bindings/reserved-memory/ramoops.yaml | 145 +++++++ dts/Bindings/reserved-memory/reserved-memory.txt | 172 +------- dts/Bindings/reserved-memory/reserved-memory.yaml | 100 +++++ dts/Bindings/reserved-memory/shared-dma-pool.yaml | 87 ++++ dts/Bindings/reset/microchip,rst.yaml | 4 +- .../reset/socionext,uniphier-glue-reset.yaml | 1 + dts/Bindings/reset/socionext,uniphier-reset.yaml | 3 + dts/Bindings/riscv/cpus.yaml | 8 +- dts/Bindings/rng/ingenic,trng.yaml | 2 +- dts/Bindings/rng/omap_rng.txt | 38 -- dts/Bindings/rng/omap_rng.yaml | 92 +++++ dts/Bindings/rng/st,stm32-rng.yaml | 2 +- dts/Bindings/rtc/ingenic,rtc.yaml | 2 +- dts/Bindings/rtc/mstar,msc313-rtc.yaml | 49 +++ dts/Bindings/rtc/nxp,pcf85063.txt | 9 + dts/Bindings/rtc/st,stm32-rtc.yaml | 2 +- dts/Bindings/serial/8250_omap.yaml | 2 +- dts/Bindings/serial/brcm,bcm6345-uart.txt | 36 -- dts/Bindings/serial/brcm,bcm6345-uart.yaml | 47 +++ dts/Bindings/serial/fsl,s32-linflexuart.txt | 22 - dts/Bindings/serial/fsl,s32-linflexuart.yaml | 48 +++ dts/Bindings/serial/ingenic,uart.yaml | 2 +- dts/Bindings/serial/samsung_uart.yaml | 1 + dts/Bindings/serial/sprd-uart.yaml | 1 + dts/Bindings/serial/st,stm32-uart.yaml | 2 +- dts/Bindings/serial/xlnx,opb-uartlite.txt | 23 -- dts/Bindings/serial/xlnx,opb-uartlite.yaml | 89 +++++ dts/Bindings/soc/aspeed/uart-routing.yaml | 56 +++ dts/Bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml | 94 +++++ dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 76 ++++ dts/Bindings/soc/qcom/qcom,aoss-qmp.yaml | 12 +- dts/Bindings/soc/qcom/qcom,apr.txt | 134 ------- dts/Bindings/soc/qcom/qcom,apr.yaml | 177 ++++++++ dts/Bindings/soc/qcom/qcom,smd-rpm.yaml | 3 + dts/Bindings/soc/qcom/qcom,smem.yaml | 34 +- dts/Bindings/soc/qcom/qcom,spm.yaml | 81 ++++ dts/Bindings/soc/qcom/qcom-stats.yaml | 47 +++ dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml | 3 + dts/Bindings/sound/amlogic,t9015.yaml | 6 + dts/Bindings/sound/audio-graph-card2.yaml | 57 +++ dts/Bindings/sound/bt-sco.txt | 13 - dts/Bindings/sound/cirrus,cs35l41.yaml | 157 ++++++++ dts/Bindings/sound/cirrus,cs42l51.yaml | 2 +- dts/Bindings/sound/cs42l42.txt | 13 +- dts/Bindings/sound/ingenic,aic.yaml | 2 +- dts/Bindings/sound/ingenic,codec.yaml | 2 +- dts/Bindings/sound/linux,bt-sco.yaml | 38 ++ dts/Bindings/sound/linux,spdif-dit.yaml | 32 ++ dts/Bindings/sound/max9892x.txt | 3 + dts/Bindings/sound/maxim,max98520.yaml | 36 ++ dts/Bindings/sound/mt8192-afe-pcm.yaml | 100 +++++ .../sound/mt8195-mt6359-rt1011-rt5682.yaml | 47 +++ dts/Bindings/sound/name-prefix.txt | 24 -- dts/Bindings/sound/name-prefix.yaml | 21 + dts/Bindings/sound/nau8821.txt | 55 +++ dts/Bindings/sound/nvidia,tegra186-dspk.yaml | 9 +- dts/Bindings/sound/nvidia,tegra210-adx.yaml | 76 ++++ dts/Bindings/sound/nvidia,tegra210-ahub.yaml | 20 + dts/Bindings/sound/nvidia,tegra210-amx.yaml | 76 ++++ dts/Bindings/sound/nvidia,tegra210-dmic.yaml | 9 +- dts/Bindings/sound/nvidia,tegra210-i2s.yaml | 9 +- dts/Bindings/sound/nvidia,tegra210-mixer.yaml | 74 ++++ dts/Bindings/sound/nvidia,tegra210-mvc.yaml | 76 ++++ dts/Bindings/sound/nvidia,tegra210-sfc.yaml | 73 ++++ dts/Bindings/sound/nxp,tfa989x.yaml | 9 +- dts/Bindings/sound/qcom,lpass-rx-macro.yaml | 4 +- dts/Bindings/sound/qcom,lpass-tx-macro.yaml | 4 +- dts/Bindings/sound/qcom,lpass-va-macro.yaml | 4 +- dts/Bindings/sound/qcom,lpass-wsa-macro.yaml | 4 +- dts/Bindings/sound/qcom,q6afe.txt | 181 --------- dts/Bindings/sound/qcom,q6apm-dai.yaml | 53 +++ dts/Bindings/sound/qcom,q6asm.txt | 2 +- dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml | 77 ++++ dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml | 205 ++++++++++ dts/Bindings/sound/realtek,rt5682s.yaml | 117 ++++++ dts/Bindings/sound/richtek,rt9120.yaml | 59 +++ dts/Bindings/sound/rockchip,i2s-tdm.yaml | 182 +++++++++ dts/Bindings/sound/rockchip,pdm.txt | 46 --- dts/Bindings/sound/rockchip,pdm.yaml | 120 ++++++ dts/Bindings/sound/rt5659.txt | 2 +- dts/Bindings/sound/simple-amplifier.txt | 17 - dts/Bindings/sound/simple-audio-amplifier.yaml | 45 +++ dts/Bindings/sound/simple-audio-mux.yaml | 9 +- dts/Bindings/sound/socionext,uniphier-aio.yaml | 22 +- dts/Bindings/sound/socionext,uniphier-evea.yaml | 6 +- dts/Bindings/sound/spdif-transmitter.txt | 10 - dts/Bindings/sound/st,stm32-i2s.yaml | 2 +- dts/Bindings/sound/st,stm32-sai.yaml | 2 +- dts/Bindings/sound/st,stm32-spdifrx.yaml | 2 +- dts/Bindings/sound/test-component.yaml | 33 ++ dts/Bindings/sound/wlf,wm8962.yaml | 118 ++++++ dts/Bindings/sound/wlf,wm8978.yaml | 58 +++ dts/Bindings/sound/wm8962.txt | 43 -- dts/Bindings/spi/cdns,qspi-nor.yaml | 12 + dts/Bindings/spi/cdns,xspi.yaml | 77 ++++ dts/Bindings/spi/ingenic,spi.yaml | 72 ++++ dts/Bindings/spi/qcom,spi-qcom-qspi.yaml | 6 +- dts/Bindings/spi/spi-nxp-fspi.txt | 44 -- dts/Bindings/spi/spi-nxp-fspi.yaml | 86 ++++ dts/Bindings/spi/spi-xlp.txt | 38 -- dts/Bindings/spi/st,stm32-qspi.yaml | 4 +- dts/Bindings/spi/st,stm32-spi.yaml | 4 +- dts/Bindings/sram/sram.yaml | 7 +- dts/Bindings/submitting-patches.rst | 3 + dts/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 149 +++++++ dts/Bindings/thermal/rockchip-thermal.yaml | 23 +- .../thermal/socionext,uniphier-thermal.yaml | 1 + dts/Bindings/thermal/st,stm32-thermal.yaml | 2 +- dts/Bindings/timer/ingenic,sysost.yaml | 2 +- dts/Bindings/timer/ingenic,tcu.yaml | 2 +- dts/Bindings/timer/st,stm32-timer.yaml | 3 +- dts/Bindings/trivial-devices.yaml | 26 +- dts/Bindings/ufs/samsung,exynos-ufs.yaml | 10 + dts/Bindings/usb/atmel-usb.txt | 4 + dts/Bindings/usb/dwc2.yaml | 16 +- dts/Bindings/usb/ingenic,musb.yaml | 2 +- dts/Bindings/usb/qcom,dwc3.yaml | 1 + dts/Bindings/usb/smsc,usb3503.yaml | 108 +++++ dts/Bindings/usb/snps,dwc3.yaml | 18 +- dts/Bindings/usb/st,stusb160x.yaml | 2 +- dts/Bindings/usb/ti,tps6598x.yaml | 4 + dts/Bindings/usb/udc-xilinx.txt | 18 - dts/Bindings/usb/usb3503.txt | 39 -- dts/Bindings/usb/xlnx,usb2.yaml | 47 +++ dts/Bindings/vendor-prefixes.yaml | 24 ++ dts/Bindings/w1/w1-gpio.txt | 27 -- dts/Bindings/w1/w1-gpio.yaml | 43 ++ dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 46 ++- dts/Bindings/watchdog/mtk-wdt.txt | 2 + dts/Bindings/watchdog/st,stm32-iwdg.yaml | 4 +- dts/Bindings/writing-bindings.rst | 2 +- dts/Bindings/writing-schema.rst | 29 +- 539 files changed, 20719 insertions(+), 6655 deletions(-) create mode 100644 dts/Bindings/arm/arm,cci-400.yaml create mode 100644 dts/Bindings/arm/cci-control-port.yaml delete mode 100644 dts/Bindings/arm/cci.txt delete mode 100644 dts/Bindings/arm/firmware/tlm,trusted-foundations.txt create mode 100644 dts/Bindings/arm/firmware/tlm,trusted-foundations.yaml create mode 100644 dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml create mode 100644 dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml create mode 100644 dts/Bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml create mode 100644 dts/Bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml create mode 100644 dts/Bindings/bus/palmbus.yaml delete mode 100644 dts/Bindings/bus/ti-sysc.txt create mode 100644 dts/Bindings/bus/ti-sysc.yaml delete mode 100644 dts/Bindings/clock/fixed-mmio-clock.txt create mode 100644 dts/Bindings/clock/fixed-mmio-clock.yaml create mode 100644 dts/Bindings/clock/imx8ulp-cgc-clock.yaml create mode 100644 dts/Bindings/clock/imx8ulp-pcc-clock.yaml create mode 100644 dts/Bindings/clock/qcom,gcc-msm8994.yaml create mode 100644 dts/Bindings/clock/qcom,gcc-qcm2290.yaml create mode 100644 dts/Bindings/clock/qcom,sc7280-camcc.yaml create mode 100644 dts/Bindings/clock/qcom,sc7280-lpasscc.yaml create mode 100644 dts/Bindings/clock/samsung,exynos850-clock.yaml delete mode 100644 dts/Bindings/clock/samsung,s2mps11.txt create mode 100644 dts/Bindings/clock/samsung,s2mps11.yaml create mode 100644 dts/Bindings/clock/stericsson,u8500-clks.yaml delete mode 100644 dts/Bindings/clock/ux500.txt create mode 100644 dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml delete mode 100644 dts/Bindings/ddr/lpddr2-timings.txt delete mode 100644 dts/Bindings/ddr/lpddr2.txt delete mode 100644 dts/Bindings/ddr/lpddr3-timings.txt delete mode 100644 dts/Bindings/ddr/lpddr3.txt delete mode 100644 dts/Bindings/display/bridge/toshiba,tc358767.txt create mode 100644 dts/Bindings/display/bridge/toshiba,tc358767.yaml create mode 100644 dts/Bindings/display/msm/dpu-sc7280.yaml delete mode 100644 dts/Bindings/display/msm/gpu.txt create mode 100644 dts/Bindings/display/msm/gpu.yaml create mode 100644 dts/Bindings/display/panel/panel-edp.yaml create mode 100644 dts/Bindings/display/panel/samsung,s6d27a1.yaml create mode 100644 dts/Bindings/display/panel/sharp,ls060t1sx01.yaml create mode 100644 dts/Bindings/display/xylon,logicvc-display.yaml create mode 100644 dts/Bindings/gnss/u-blox,neo-6m.yaml delete mode 100644 dts/Bindings/gnss/u-blox.txt delete mode 100644 dts/Bindings/gpio/gpio-axp209.txt delete mode 100644 dts/Bindings/gpio/gpio-xlp.txt create mode 100644 dts/Bindings/gpio/x-powers,axp209-gpio.yaml create mode 100644 dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml create mode 100644 dts/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml delete mode 100644 dts/Bindings/hwmon/dps650ab.txt delete mode 100644 dts/Bindings/hwmon/hih6130.txt delete mode 100644 dts/Bindings/hwmon/ibm,cffps1.txt create mode 100644 dts/Bindings/hwmon/iio-hwmon.yaml delete mode 100644 dts/Bindings/hwmon/jc42.txt create mode 100644 dts/Bindings/hwmon/jedec,jc42.yaml create mode 100644 dts/Bindings/hwmon/lltc,ltc4151.yaml delete mode 100644 dts/Bindings/hwmon/lm70.txt delete mode 100644 dts/Bindings/hwmon/lm90.txt delete mode 100644 dts/Bindings/hwmon/ltc4151.txt delete mode 100644 dts/Bindings/hwmon/mcp3021.txt create mode 100644 dts/Bindings/hwmon/microchip,mcp3021.yaml create mode 100644 dts/Bindings/hwmon/national,lm90.yaml create mode 100644 dts/Bindings/hwmon/ntc-thermistor.yaml delete mode 100644 dts/Bindings/hwmon/ntc_thermistor.txt create mode 100644 dts/Bindings/hwmon/nuvoton,nct7802.yaml create mode 100644 dts/Bindings/hwmon/pmbus/ti,lm25066.yaml create mode 100644 dts/Bindings/hwmon/sensirion,sht15.yaml delete mode 100644 dts/Bindings/hwmon/sht15.txt create mode 100644 dts/Bindings/hwmon/ti,tmp102.yaml create mode 100644 dts/Bindings/hwmon/ti,tmp108.yaml create mode 100644 dts/Bindings/hwmon/ti,tmp421.yaml delete mode 100644 dts/Bindings/hwmon/tmp108.txt create mode 100644 dts/Bindings/i2c/apple,i2c.yaml delete mode 100644 dts/Bindings/i2c/i2c-xlp9xx.txt create mode 100644 dts/Bindings/iio/accel/adi,adxl313.yaml create mode 100644 dts/Bindings/iio/accel/adi,adxl355.yaml create mode 100644 dts/Bindings/iio/adc/adi,ad799x.yaml create mode 100644 dts/Bindings/iio/adc/aspeed,ast2600-adc.yaml create mode 100644 dts/Bindings/iio/adc/nxp,imx8qxp-adc.yaml create mode 100644 dts/Bindings/iio/adc/ti,am3359-adc.yaml create mode 100644 dts/Bindings/iio/chemical/senseair,sunrise.yaml create mode 100644 dts/Bindings/iio/chemical/sensirion,scd4x.yaml create mode 100644 dts/Bindings/iio/frequency/adi,adrf6780.yaml create mode 100644 dts/Bindings/iio/light/liteon,ltr501.yaml create mode 100644 dts/Bindings/iio/temperature/maxim,max31865.yaml delete mode 100644 dts/Bindings/input/cap11xx.txt create mode 100644 dts/Bindings/input/cypress-sf.yaml create mode 100644 dts/Bindings/input/elan,ekth3000.yaml delete mode 100644 dts/Bindings/input/elan_i2c.txt create mode 100644 dts/Bindings/input/microchip,cap11xx.yaml create mode 100644 dts/Bindings/input/touchscreen/silead,gsl1680.yaml delete mode 100644 dts/Bindings/input/touchscreen/silead_gsl1680.txt create mode 100644 dts/Bindings/input/touchscreen/ti,am3359-tsc.yaml delete mode 100644 dts/Bindings/input/touchscreen/ti-tsc-adc.txt create mode 100644 dts/Bindings/interrupt-controller/microchip,eic.yaml create mode 100644 dts/Bindings/interrupt-controller/msi-controller.yaml create mode 100644 dts/Bindings/ipmi/ipmi-ipmb.yaml delete mode 100644 dts/Bindings/leds/register-bit-led.txt create mode 100644 dts/Bindings/leds/register-bit-led.yaml create mode 100644 dts/Bindings/mailbox/apple,mailbox.yaml create mode 100644 dts/Bindings/media/i2c/aptina,mt9p031.yaml create mode 100644 dts/Bindings/media/i2c/hynix,hi846.yaml delete mode 100644 dts/Bindings/media/i2c/mt9p031.txt delete mode 100644 dts/Bindings/media/i2c/ov5640.txt create mode 100644 dts/Bindings/media/i2c/ovti,ov5640.yaml create mode 100644 dts/Bindings/media/qcom,sc7280-venus.yaml create mode 100644 dts/Bindings/media/qcom,sdm660-venus.yaml delete mode 100644 dts/Bindings/media/renesas,imr.txt create mode 100644 dts/Bindings/media/renesas,imr.yaml create mode 100644 dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml create mode 100644 dts/Bindings/memory-controllers/ddr/lpddr2-timings.txt create mode 100644 dts/Bindings/memory-controllers/ddr/lpddr3-timings.txt create mode 100644 dts/Bindings/memory-controllers/ddr/lpddr3.txt delete mode 100644 dts/Bindings/memory-controllers/fsl/ddr.txt create mode 100644 dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml create mode 100644 dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml delete mode 100644 dts/Bindings/memory-controllers/omap-gpmc.txt create mode 100644 dts/Bindings/memory-controllers/ti,gpmc-child.yaml create mode 100644 dts/Bindings/memory-controllers/ti,gpmc.yaml delete mode 100644 dts/Bindings/mfd/ac100.txt delete mode 100644 dts/Bindings/mfd/aspeed-lpc.txt create mode 100644 dts/Bindings/mfd/aspeed-lpc.yaml delete mode 100644 dts/Bindings/mfd/axp20x.txt create mode 100644 dts/Bindings/mfd/brcm,misc.yaml create mode 100644 dts/Bindings/mfd/samsung,s2mpa01.yaml create mode 100644 dts/Bindings/mfd/samsung,s2mps11.yaml create mode 100644 dts/Bindings/mfd/samsung,s5m8767.yaml delete mode 100644 dts/Bindings/mfd/samsung,sec-core.txt create mode 100644 dts/Bindings/mfd/ti,am3359-tscadc.yaml create mode 100644 dts/Bindings/mfd/x-powers,ac100.yaml create mode 100644 dts/Bindings/mfd/x-powers,axp152.yaml delete mode 100644 dts/Bindings/mips/ralink.txt create mode 100644 dts/Bindings/mips/ralink.yaml delete mode 100644 dts/Bindings/mmc/mmc-card.txt create mode 100644 dts/Bindings/mmc/mmc-card.yaml delete mode 100644 dts/Bindings/mtd/gpmc-nand.txt delete mode 100644 dts/Bindings/mtd/gpmc-nor.txt delete mode 100644 dts/Bindings/mtd/gpmc-onenand.txt create mode 100644 dts/Bindings/mtd/ti,gpmc-nand.yaml create mode 100644 dts/Bindings/mtd/ti,gpmc-onenand.yaml create mode 100644 dts/Bindings/net/asix,ax88796c.yaml delete mode 100644 dts/Bindings/net/dsa/qca8k.txt create mode 100644 dts/Bindings/net/dsa/qca8k.yaml delete mode 100644 dts/Bindings/net/gpmc-eth.txt create mode 100644 dts/Bindings/net/lantiq,etop-xway.yaml delete mode 100644 dts/Bindings/net/lantiq,xrx200-net.txt create mode 100644 dts/Bindings/net/lantiq,xrx200-net.yaml delete mode 100644 dts/Bindings/net/marvell-bluetooth.txt create mode 100644 dts/Bindings/net/marvell-bluetooth.yaml create mode 100644 dts/Bindings/net/nfc/marvell,nci.yaml delete mode 100644 dts/Bindings/net/nfc/nfcmrvl.txt create mode 100644 dts/Bindings/net/nfc/nxp,nci.yaml create mode 100644 dts/Bindings/net/nfc/nxp,pn532.yaml create mode 100644 dts/Bindings/net/nfc/nxp,pn544.yaml delete mode 100644 dts/Bindings/net/nfc/nxp-nci.txt delete mode 100644 dts/Bindings/net/nfc/pn532.txt delete mode 100644 dts/Bindings/net/nfc/pn544.txt create mode 100644 dts/Bindings/net/nfc/st,st-nci.yaml create mode 100644 dts/Bindings/net/nfc/st,st21nfca.yaml create mode 100644 dts/Bindings/net/nfc/st,st95hf.yaml delete mode 100644 dts/Bindings/net/nfc/st-nci-i2c.txt delete mode 100644 dts/Bindings/net/nfc/st-nci-spi.txt delete mode 100644 dts/Bindings/net/nfc/st21nfca.txt delete mode 100644 dts/Bindings/net/nfc/st95hf.txt create mode 100644 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dts/Bindings/soc/qcom/qcom,spm.yaml create mode 100644 dts/Bindings/soc/qcom/qcom-stats.yaml create mode 100644 dts/Bindings/sound/audio-graph-card2.yaml delete mode 100644 dts/Bindings/sound/bt-sco.txt create mode 100644 dts/Bindings/sound/cirrus,cs35l41.yaml create mode 100644 dts/Bindings/sound/linux,bt-sco.yaml create mode 100644 dts/Bindings/sound/linux,spdif-dit.yaml create mode 100644 dts/Bindings/sound/maxim,max98520.yaml create mode 100644 dts/Bindings/sound/mt8192-afe-pcm.yaml create mode 100644 dts/Bindings/sound/mt8195-mt6359-rt1011-rt5682.yaml delete mode 100644 dts/Bindings/sound/name-prefix.txt create mode 100644 dts/Bindings/sound/name-prefix.yaml create mode 100644 dts/Bindings/sound/nau8821.txt create mode 100644 dts/Bindings/sound/nvidia,tegra210-adx.yaml create mode 100644 dts/Bindings/sound/nvidia,tegra210-amx.yaml create mode 100644 dts/Bindings/sound/nvidia,tegra210-mixer.yaml create mode 100644 dts/Bindings/sound/nvidia,tegra210-mvc.yaml create mode 100644 dts/Bindings/sound/nvidia,tegra210-sfc.yaml create mode 100644 dts/Bindings/sound/qcom,q6apm-dai.yaml create mode 100644 dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml create mode 100644 dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml create mode 100644 dts/Bindings/sound/realtek,rt5682s.yaml create mode 100644 dts/Bindings/sound/richtek,rt9120.yaml create mode 100644 dts/Bindings/sound/rockchip,i2s-tdm.yaml delete mode 100644 dts/Bindings/sound/rockchip,pdm.txt create mode 100644 dts/Bindings/sound/rockchip,pdm.yaml delete mode 100644 dts/Bindings/sound/simple-amplifier.txt create mode 100644 dts/Bindings/sound/simple-audio-amplifier.yaml delete mode 100644 dts/Bindings/sound/spdif-transmitter.txt create mode 100644 dts/Bindings/sound/test-component.yaml create mode 100644 dts/Bindings/sound/wlf,wm8962.yaml create mode 100644 dts/Bindings/sound/wlf,wm8978.yaml delete mode 100644 dts/Bindings/sound/wm8962.txt create mode 100644 dts/Bindings/spi/cdns,xspi.yaml create mode 100644 dts/Bindings/spi/ingenic,spi.yaml delete mode 100644 dts/Bindings/spi/spi-nxp-fspi.txt create mode 100644 dts/Bindings/spi/spi-nxp-fspi.yaml delete mode 100644 dts/Bindings/spi/spi-xlp.txt create mode 100644 dts/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml create mode 100644 dts/Bindings/usb/smsc,usb3503.yaml delete mode 100644 dts/Bindings/usb/udc-xilinx.txt delete mode 100644 dts/Bindings/usb/usb3503.txt create mode 100644 dts/Bindings/usb/xlnx,usb2.yaml delete mode 100644 dts/Bindings/w1/w1-gpio.txt create mode 100644 dts/Bindings/w1/w1-gpio.yaml (limited to 'dts/Bindings') diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile index a072e95de6..c9abfbe3f0 100644 --- a/dts/Bindings/Makefile +++ b/dts/Bindings/Makefile @@ -9,6 +9,11 @@ DT_SCHEMA_MIN_VERSION = 2021.2.1 PHONY += check_dtschema_version check_dtschema_version: + @which $(DT_DOC_CHECKER) >/dev/null || \ + { echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \ + echo "Ensure dtschema python package is installed and in your PATH." >&2; \ + echo "Current PATH is:" >&2; \ + echo "$$PATH" >&2; false; } @{ echo $(DT_SCHEMA_MIN_VERSION); \ $(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \ { echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; } @@ -22,13 +27,20 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE # Use full schemas when checking %.example.dts DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json -find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ +find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ -name 'processed-schema*' ! \ -name '*.example.dt.yaml' \) +ifeq ($(DT_SCHEMA_FILES),) +find_cmd = $(find_all_cmd) +else +find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES)) +endif + quiet_cmd_yamllint = LINT $(src) cmd_yamllint = ($(find_cmd) | \ - xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true + xargs -n200 -P$$(nproc) \ + $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true quiet_cmd_chk_bindings = CHKDT $@ cmd_chk_bindings = ($(find_cmd) | \ @@ -38,7 +50,7 @@ quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ $(if $(DT_MK_SCHEMA_FLAGS), \ printf '%s\n' $(real-prereqs), \ - $(find_cmd)) > $$f ; \ + $(find_all_cmd)) > $$f ; \ $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ rm -f $$f @@ -48,7 +60,7 @@ define rule_chkdt $(call cmd,mk_schema) endef -DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd))) +DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd))) override DTC_FLAGS := \ -Wno-avoid_unnecessary_addr_size \ diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml index 6423377710..36081734f7 100644 --- a/dts/Bindings/arm/amlogic.yaml +++ b/dts/Bindings/arm/amlogic.yaml @@ -86,6 +86,7 @@ properties: - enum: - amlogic,p281 - oranth,tx3-mini + - jethome,jethub-j80 - const: amlogic,s905w - const: amlogic,meson-gxl @@ -133,6 +134,7 @@ properties: items: - enum: - amlogic,s400 + - jethome,jethub-j100 - const: amlogic,a113d - const: amlogic,meson-axg @@ -141,6 +143,7 @@ properties: - enum: - amediatech,x96-max - amlogic,u200 + - radxa,zero - seirobotics,sei510 - const: amlogic,g12a diff --git a/dts/Bindings/arm/arm,cci-400.yaml b/dts/Bindings/arm/arm,cci-400.yaml new file mode 100644 index 0000000000..4682f991a5 --- /dev/null +++ b/dts/Bindings/arm/arm,cci-400.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CCI Cache Coherent Interconnect Device Tree Binding + +maintainers: + - Lorenzo Pieralisi + +description: > + ARM multi-cluster systems maintain intra-cluster coherency through a cache + coherent interconnect (CCI) that is capable of monitoring bus transactions + and manage coherency, TLB invalidations and memory barriers. + + It allows snooping and distributed virtual memory message broadcast across + clusters, through memory mapped interface, with a global control register + space and multiple sets of interface control registers, one per slave + interface. + +properties: + $nodename: + pattern: "^cci(@[0-9a-f]+)?$" + + compatible: + enum: + - arm,cci-400 + - arm,cci-500 + - arm,cci-550 + + reg: + maxItems: 1 + description: > + Specifies base physical address of CCI control registers common to all + interfaces. + + "#address-cells": true + "#size-cells": true + ranges: true + +patternProperties: + "^slave-if@[0-9a-f]+$": + type: object + + properties: + compatible: + const: arm,cci-400-ctrl-if + + interface-type: + enum: + - ace + - ace-lite + + reg: + maxItems: 1 + + required: + - compatible + - interface-type + - reg + + additionalProperties: false + + "^pmu@[0-9a-f]+$": + type: object + + properties: + compatible: + oneOf: + - const: arm,cci-400-pmu,r0 + - const: arm,cci-400-pmu,r1 + - const: arm,cci-400-pmu + deprecated: true + description: > + Permitted only where OS has secure access to CCI registers + - const: arm,cci-500-pmu,r0 + - const: arm,cci-550-pmu,r0 + + interrupts: + minItems: 1 + maxItems: 8 + description: > + List of counter overflow interrupts, one per counter. The interrupts + must be specified starting with the cycle counter overflow interrupt, + followed by counter0 overflow interrupt, counter1 overflow + interrupt,... ,counterN overflow interrupt. + + The CCI PMU has an interrupt signal for each counter. The number of + interrupts must be equal to the number of counters. + + reg: + maxItems: 1 + + required: + - compatible + - interrupts + - reg + + additionalProperties: false + +required: + - "#address-cells" + - "#size-cells" + - compatible + - ranges + - reg + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; + model = "V2P-CA15_CA7"; + arm,hbi = <0x249>; + interrupt-parent = <&gic>; + + /* + * This CCI node corresponds to a CCI component whose control + * registers sits at address 0x000000002c090000. + * + * CCI slave interface @0x000000002c091000 is connected to dma + * controller dma0. + * + * CCI slave interface @0x000000002c094000 is connected to CPUs + * {CPU0, CPU1}; + * + * CCI slave interface @0x000000002c095000 is connected to CPUs + * {CPU2, CPU3}; + */ + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x1>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x100>; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x101>; + }; + }; + + dma0: dma@3000000 { + /* compatible = "arm,pl330", "arm,primecell"; */ + cci-control-port = <&cci_control0>; + reg = <0x0 0x3000000 0x0 0x1000>; + interrupts = <10>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu"; + reg = <0x9000 0x5000>; + interrupts = <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>, + <0 105 4>; + }; + }; + }; + +... diff --git a/dts/Bindings/arm/arm,vexpress-juno.yaml b/dts/Bindings/arm/arm,vexpress-juno.yaml index 55ef656d11..a4b4452afc 100644 --- a/dts/Bindings/arm/arm,vexpress-juno.yaml +++ b/dts/Bindings/arm/arm,vexpress-juno.yaml @@ -119,22 +119,6 @@ properties: - const: arm,foundation-aarch64 - const: arm,vexpress - arm,hbi: - $ref: '/schemas/types.yaml#/definitions/uint32' - description: This indicates the ARM HBI (Hardware Board ID), this is - ARM's unique board model ID, visible on the PCB's silkscreen. - - arm,vexpress,site: - description: As Versatile Express can be configured in number of physically - different setups, the device tree should describe platform topology. - For this reason the root node and main motherboard node must define this - property, describing the physical location of the children nodes. - 0 means motherboard site, while 1 and 2 are daughterboard sites, and - 0xf means "sisterboard" which is the site containing the main CPU tile. - $ref: '/schemas/types.yaml#/definitions/uint32' - minimum: 0 - maximum: 15 - arm,vexpress,position: description: When daughterboards are stacked on one site, their position in the stack be be described this attribute. @@ -154,9 +138,9 @@ patternProperties: description: Static Memory Bus (SMB) node, if this exists it describes the connection between the motherboard and any tiles. Sometimes the compatible is placed directly under this node, sometimes it is placed - in a subnode named "motherboard". Sometimes the compatible includes + in a subnode named "motherboard-bus". Sometimes the compatible includes "arm,vexpress,v2?-p1" sometimes (on software models) is is just - "simple-bus". If the compatible is placed in the "motherboard" node, + "simple-bus". If the compatible is placed in the "motherboard-bus" node, it is stricter and always has two compatibles. type: object $ref: '/schemas/simple-bus.yaml' @@ -170,7 +154,9 @@ patternProperties: - arm,vexpress,v2p-p1 - const: simple-bus - const: simple-bus - motherboard: + + patternProperties: + '^motherboard-bus@': type: object description: The motherboard description provides a single "motherboard" node using 2 address cells corresponding to the Static Memory Bus @@ -183,6 +169,8 @@ patternProperties: const: 2 "#size-cells": const: 1 + ranges: true + compatible: items: - enum: @@ -196,8 +184,28 @@ patternProperties: - rs1 - rs2 + arm,hbi: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: This indicates the ARM HBI (Hardware Board ID), this is + ARM's unique board model ID, visible on the PCB's silkscreen. + + arm,vexpress,site: + description: As Versatile Express can be configured in number of physically + different setups, the device tree should describe platform topology. + For this reason the root node and main motherboard node must define this + property, describing the physical location of the children nodes. + 0 means motherboard site, while 1 and 2 are daughterboard sites, and + 0xf means "sisterboard" which is the site containing the main CPU tile. + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 15 + required: - compatible + + additionalProperties: + type: object + required: - compatible diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml index fba071b9af..c612e1f48d 100644 --- a/dts/Bindings/arm/atmel-at91.yaml +++ b/dts/Bindings/arm/atmel-at91.yaml @@ -126,6 +126,18 @@ properties: - const: atmel,sama5d3 - const: atmel,sama5 + - description: CalAmp LMU5000 board + items: + - const: calamp,lmu5000 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + + - description: Exegin Q5xR5 board + items: + - const: exegin,q5xr5 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + - items: - enum: - atmel,sama5d31 @@ -150,6 +162,18 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 + - description: Microchip LAN9662 PCB8291 Evaluation Board. + items: + - const: microchip,lan9662-pcb8291 + - const: microchip,lan9662 + - const: microchip,lan966 + + - description: Microchip LAN9668 PCB8290 Evaluation Board. + items: + - const: microchip,lan9668-pcb8290 + - const: microchip,lan9668 + - const: microchip,lan966 + - items: - enum: - atmel,sams70j19 diff --git a/dts/Bindings/arm/bcm/bcm2835.yaml b/dts/Bindings/arm/bcm/bcm2835.yaml index 230b80d9d6..5dc48241ef 100644 --- a/dts/Bindings/arm/bcm/bcm2835.yaml +++ b/dts/Bindings/arm/bcm/bcm2835.yaml @@ -19,6 +19,7 @@ properties: items: - enum: - raspberrypi,400 + - raspberrypi,4-compute-module - raspberrypi,4-model-b - const: brcm,bcm2711 diff --git a/dts/Bindings/arm/bcm/brcm,nsp.yaml b/dts/Bindings/arm/bcm/brcm,nsp.yaml index 476bc23a7f..7d184ba7d1 100644 --- a/dts/Bindings/arm/bcm/brcm,nsp.yaml +++ b/dts/Bindings/arm/bcm/brcm,nsp.yaml @@ -22,16 +22,61 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - brcm,bcm58522 - - brcm,bcm58525 - - brcm,bcm58535 - - brcm,bcm58622 - - brcm,bcm58623 - - brcm,bcm58625 - - brcm,bcm88312 - - const: brcm,nsp + oneOf: + - description: BCM58522 based boards + items: + - enum: + - brcm,bcm958522er + - const: brcm,bcm58522 + - const: brcm,nsp + + - description: BCM58525 based boards + items: + - enum: + - brcm,bcm958525er + - brcm,bcm958525xmc + - const: brcm,bcm58525 + - const: brcm,nsp + + - description: BCM58535 based boards + items: + - const: brcm,bcm58535 + - const: brcm,nsp + + - description: BCM58622 based boards + items: + - enum: + - brcm,bcm958622hr + - const: brcm,bcm58622 + - const: brcm,nsp + + - description: BCM58623 based boards + items: + - enum: + - brcm,bcm958623hr + - const: brcm,bcm58623 + - const: brcm,nsp + + - description: BCM58625 based boards + items: + - enum: + - brcm,bcm958625hr + - brcm,bcm958625k + - meraki,mx64 + - meraki,mx64-a0 + - meraki,mx64w + - meraki,mx64w-a0 + - meraki,mx65 + - meraki,mx65w + - const: brcm,bcm58625 + - const: brcm,nsp + + - description: BCM88312 based boards + items: + - enum: + - brcm,bcm988312hr + - const: brcm,bcm88312 + - const: brcm,nsp additionalProperties: true diff --git a/dts/Bindings/arm/cci-control-port.yaml b/dts/Bindings/arm/cci-control-port.yaml new file mode 100644 index 0000000000..c911486621 --- /dev/null +++ b/dts/Bindings/arm/cci-control-port.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cci-control-port.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CCI Interconnect Bus Masters binding + +maintainers: + - Lorenzo Pieralisi + +description: | + Masters in the device tree connected to a CCI port (inclusive of CPUs + and their cpu nodes). + +select: true + +properties: + cci-control-port: + $ref: /schemas/types.yaml#/definitions/phandle + +additionalProperties: true + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + reg = <0>; + }; + }; + +... diff --git a/dts/Bindings/arm/cci.txt b/dts/Bindings/arm/cci.txt deleted file mode 100644 index 9600761f2d..0000000000 --- a/dts/Bindings/arm/cci.txt +++ /dev/null @@ -1,224 +0,0 @@ -======================================================= -ARM CCI cache coherent interconnect binding description -======================================================= - -ARM multi-cluster systems maintain intra-cluster coherency through a -cache coherent interconnect (CCI) that is capable of monitoring bus -transactions and manage coherency, TLB invalidations and memory barriers. - -It allows snooping and distributed virtual memory message broadcast across -clusters, through memory mapped interface, with a global control register -space and multiple sets of interface control registers, one per slave -interface. - -* CCI interconnect node - - Description: Describes a CCI cache coherent Interconnect component - - Node name must be "cci". - Node's parent must be the root node /, and the address space visible - through the CCI interconnect is the same as the one seen from the - root node (ie from CPUs perspective as per DT standard). - Every CCI node has to define the following properties: - - - compatible - Usage: required - Value type: - Definition: must contain one of the following: - "arm,cci-400" - "arm,cci-500" - "arm,cci-550" - - - reg - Usage: required - Value type: Integer cells. A register entry, expressed as a pair - of cells, containing base and size. - Definition: A standard property. Specifies base physical - address of CCI control registers common to all - interfaces. - - - ranges: - Usage: required - Value type: Integer cells. An array of range entries, expressed - as a tuple of cells, containing child address, - parent address and the size of the region in the - child address space. - Definition: A standard property. Follow rules in the Devicetree - Specification for hierarchical bus addressing. CCI - interfaces addresses refer to the parent node - addressing scheme to declare their register bases. - - CCI interconnect node can define the following child nodes: - - - CCI control interface nodes - - Node name must be "slave-if". - Parent node must be CCI interconnect node. - - A CCI control interface node must contain the following - properties: - - - compatible - Usage: required - Value type: - Definition: must be set to - "arm,cci-400-ctrl-if" - - - interface-type: - Usage: required - Value type: - Definition: must be set to one of {"ace", "ace-lite"} - depending on the interface type the node - represents. - - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - CCI PMU node - - Parent node must be CCI interconnect node. - - A CCI pmu node must contain the following properties: - - - compatible - Usage: required - Value type: - Definition: Must contain one of: - "arm,cci-400-pmu,r0" - "arm,cci-400-pmu,r1" - "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has - secure access to CCI registers - "arm,cci-500-pmu,r0" - "arm,cci-550-pmu,r0" - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - interrupts: - Usage: required - Value type: Integer cells. Array of interrupt specifier - entries, as defined in - ../interrupt-controller/interrupts.txt. - Definition: list of counter overflow interrupts, one per - counter. The interrupts must be specified - starting with the cycle counter overflow - interrupt, followed by counter0 overflow - interrupt, counter1 overflow interrupt,... - ,counterN overflow interrupt. - - The CCI PMU has an interrupt signal for each - counter. The number of interrupts must be - equal to the number of counters. - -* CCI interconnect bus masters - - Description: masters in the device tree connected to a CCI port - (inclusive of CPUs and their cpu nodes). - - A CCI interconnect bus master node must contain the following - properties: - - - cci-control-port: - Usage: required - Value type: - Definition: a phandle containing the CCI control interface node - the master is connected to. - -Example: - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x1>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x100>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x101>; - }; - - }; - - dma0: dma@3000000 { - compatible = "arm,pl330", "arm,primecell"; - cci-control-port = <&cci_control0>; - reg = <0x0 0x3000000 0x0 0x1000>; - interrupts = <10>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu"; - reg = <0x9000 0x5000>; - interrupts = <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>, - <0 105 4>; - }; - }; - -This CCI node corresponds to a CCI component whose control registers sits -at address 0x000000002c090000. -CCI slave interface @0x000000002c091000 is connected to dma controller dma0. -CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1}; -CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3}; diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt index 7f9c1ca874..c68d93a35b 100644 --- a/dts/Bindings/arm/coresight.txt +++ b/dts/Bindings/arm/coresight.txt @@ -127,6 +127,11 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * arm,max-burst-size: The maximum burst size initiated by TMC on the + AXI master interface. The burst size can be in the range [0..15], + the setting supports one data transfer per burst up to a maximum of + 16 data transfers per burst. + * Optional property for CATU : * interrupts : Exactly one SPI may be listed for reporting the address error diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml index 9a2432a880..f2ab6423b4 100644 --- a/dts/Bindings/arm/cpus.yaml +++ b/dts/Bindings/arm/cpus.yaml @@ -171,6 +171,8 @@ properties: - qcom,kryo385 - qcom,kryo468 - qcom,kryo485 + - qcom,kryo560 + - qcom,kryo570 - qcom,kryo685 - qcom,scorpion @@ -209,6 +211,9 @@ properties: - qcom,gcc-msm8660 - qcom,kpss-acc-v1 - qcom,kpss-acc-v2 + - qcom,msm8226-smp + # Only valid on ARM 32-bit, see above for ARM v8 64-bit + - qcom,msm8916-smp - renesas,apmu - renesas,r9a06g032-smp - rockchip,rk3036-smp @@ -240,6 +245,8 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + cci-control-port: true + dynamic-power-coefficient: $ref: '/schemas/types.yaml#/definitions/uint32' description: @@ -293,7 +300,8 @@ properties: Specifies the ACC* node associated with this CPU. Required for systems that have an "enable-method" property - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" + value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or + "qcom,msm8916-smp". * arm/msm/qcom,kpss-acc.txt diff --git a/dts/Bindings/arm/firmware/tlm,trusted-foundations.txt b/dts/Bindings/arm/firmware/tlm,trusted-foundations.txt deleted file mode 100644 index 780d0392a6..0000000000 --- a/dts/Bindings/arm/firmware/tlm,trusted-foundations.txt +++ /dev/null @@ -1,20 +0,0 @@ -Trusted Foundations -------------------- - -Boards that use the Trusted Foundations secure monitor can signal its -presence by declaring a node compatible with "tlm,trusted-foundations" -under the /firmware/ node - -Required properties: -- compatible: "tlm,trusted-foundations" -- tlm,version-major: major version number of Trusted Foundations firmware -- tlm,version-minor: minor version number of Trusted Foundations firmware - -Example: - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; diff --git a/dts/Bindings/arm/firmware/tlm,trusted-foundations.yaml b/dts/Bindings/arm/firmware/tlm,trusted-foundations.yaml new file mode 100644 index 0000000000..9d1857c0aa --- /dev/null +++ b/dts/Bindings/arm/firmware/tlm,trusted-foundations.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Trusted Foundations + +description: | + Boards that use the Trusted Foundations secure monitor can signal its + presence by declaring a node compatible under the /firmware/ node + +maintainers: + - Stephen Warren + +properties: + $nodename: + const: trusted-foundations + + compatible: + const: tlm,trusted-foundations + + tlm,version-major: + $ref: /schemas/types.yaml#/definitions/uint32 + description: major version number of Trusted Foundations firmware + + tlm,version-minor: + $ref: /schemas/types.yaml#/definitions/uint32 + description: minor version number of Trusted Foundations firmware + +required: + - compatible + - tlm,version-major + - tlm,version-minor + +additionalProperties: false + +examples: + - | + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml index 60f4862ba1..0b595b2606 100644 --- a/dts/Bindings/arm/fsl.yaml +++ b/dts/Bindings/arm/fsl.yaml @@ -235,7 +235,7 @@ properties: - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - - toradex,apalis_imx6q # Apalis iMX6 Module + - toradex,apalis_imx6q # Apalis iMX6 Modules - udoo,imx6q-udoo # Udoo i.MX6 Quad Board - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard @@ -314,18 +314,12 @@ properties: - const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad - const: fsl,imx6q - - description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module + - description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Modules items: - enum: - - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board - - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board - - const: toradex,apalis_imx6q - - const: fsl,imx6q - - - description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1 - items: - - const: toradex,apalis_imx6q-ixora-v1.1 - - const: toradex,apalis_imx6q-ixora + - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board + - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board + - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board - const: toradex,apalis_imx6q - const: fsl,imx6q @@ -393,6 +387,8 @@ properties: - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 + - toradex,colibri_imx6dl # Colibri iMX6 Modules + - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -466,20 +462,18 @@ properties: - const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad - const: fsl,imx6dl - - description: i.MX6DL Toradex Colibri iMX6 Module on Colibri - Evaluation Board V3 + - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules items: - - const: toradex,colibri_imx6dl-eval-v3 - - const: toradex,colibri_imx6dl # Colibri iMX6 Module + - enum: + - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3 + - const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module - const: fsl,imx6dl - - description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri - Evaluation Board V3 + - description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules items: - - const: toradex,colibri_imx6dl-v1_1-eval-v3 - - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1 - - const: toradex,colibri_imx6dl-eval-v3 - - const: toradex,colibri_imx6dl # Colibri iMX6 Module + - enum: + - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3 + - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module - const: fsl,imx6dl - description: i.MX6S DHCOM DRC02 Board @@ -494,6 +488,7 @@ properties: - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board - kobo,tolino-shine2hd - kobo,tolino-shine3 + - kobo,tolino-vision5 - revotics,imx6sl-warp # Revotics WaRP Board - const: fsl,imx6sl @@ -502,6 +497,7 @@ properties: - enum: - fsl,imx6sll-evk - kobo,clarahd + - kobo,librah2o - const: fsl,imx6sll - description: i.MX6SX based Boards @@ -586,8 +582,9 @@ properties: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board + - toradex,colibri-imx6ull # Colibri iMX6ULL Modules + - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module + - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules - const: fsl,imx6ull - description: i.MX6ULL Armadeus Systems OPOS6ULDev Board @@ -605,6 +602,27 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules + items: + - enum: + - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board + - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module + - const: fsl,imx6dl + + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module + items: + - enum: + - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board + - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module + - const: fsl,imx6dl + + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules + items: + - enum: + - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board + - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module + - const: fsl,imx6dl + - description: Kontron N6411 S Board items: - const: kontron,imx6ull-n6411-s @@ -622,6 +640,7 @@ properties: items: - enum: - element14,imx7s-warp # Element14 Warp i.MX7 Board + - toradex,colibri-imx7s # Colibri iMX7S Module - const: fsl,imx7s - description: i.MX7S Boards with Toradex Colibri iMX7S Module @@ -653,15 +672,8 @@ properties: - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi - - toradex,colibri-imx7d # Colibri iMX7 Dual Module - - toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board - - toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module - - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on - # Aster Carrier Board - - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on - # Colibri Evaluation Board V3 - - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on - # Colibri Evaluation Board V3 + - toradex,colibri-imx7d # Colibri iMX7D Module + - toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d @@ -686,12 +698,12 @@ properties: - description: i.MX7D Boards with Toradex Colibri i.MX7D Module items: - enum: - - toradex,colibri-imx7d-aster # Module on Aster Carrier Board - - toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board + - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3 - const: toradex,colibri-imx7d - const: fsl,imx7d - - description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module + - description: i.MX7D Boards with Toradex Colibri i.MX7D 1GB (eMMC) Module items: - enum: - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board @@ -812,10 +824,10 @@ properties: - enum: - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board - fsl,imx8qxp-mek # i.MX8QXP MEK Board - - toradex,colibri-imx8x # Colibri iMX8X Module + - toradex,colibri-imx8x # Colibri iMX8X Modules - const: fsl,imx8qxp - - description: Toradex Colibri i.MX8 Evaluation Board + - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules items: - enum: - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 @@ -847,9 +859,10 @@ properties: - description: VF610 based Boards items: - enum: + - fsl,vf610-twr # VF610 Tower Board - lwn,bk4 # Liebherr BK4 controller - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board - - fsl,vf610-twr # VF610 Tower Board + - toradex,vf610-colibri_vf61 # Colibri VF61 Modules - const: fsl,vf610 - description: Toradex Colibri VF61 Module on Colibri Evaluation Board @@ -886,6 +899,7 @@ properties: - enum: - fsl,ls1021a-moxa-uc-8410a - fsl,ls1021a-qds + - fsl,ls1021a-tsn - fsl,ls1021a-twr - const: fsl,ls1021a @@ -977,6 +991,8 @@ properties: - description: LX2160A based Boards items: - enum: + - fsl,lx2160a-bluebox3 + - fsl,lx2160a-bluebox3-rev-a - fsl,lx2160a-qds - fsl,lx2160a-rdb - fsl,lx2162a-qds @@ -990,6 +1006,13 @@ properties: - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a + - description: S32G2 based Boards + items: + - enum: + - nxp,s32g274a-evb + - nxp,s32g274a-rdb2 + - const: nxp,s32g2 + - description: S32V234 based Boards items: - enum: diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml index 80a05f6fee..0fa55497b9 100644 --- a/dts/Bindings/arm/mediatek.yaml +++ b/dts/Bindings/arm/mediatek.yaml @@ -32,6 +32,7 @@ properties: - const: mediatek,mt6580 - items: - enum: + - fairphone,fp1 - mundoreader,bq-aquaris5 - const: mediatek,mt6589 - items: diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml index f9ffa5b703..763c62323a 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml @@ -43,6 +43,9 @@ properties: "#clock-cells": const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg @@ -56,4 +59,5 @@ examples: compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0x14000000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml new file mode 100644 index 0000000000..17fcbb45d1 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml @@ -0,0 +1,254 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Functional Clock Controller for MT8195 + +maintainers: + - Chun-Jie Chen + +description: + The clock architecture in Mediatek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices except apusys_pll provide clock gate control in different IP blocks. + The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-scp_adsp + - mediatek,mt8195-imp_iic_wrap_s + - mediatek,mt8195-imp_iic_wrap_w + - mediatek,mt8195-mfgcfg + - mediatek,mt8195-vppsys0 + - mediatek,mt8195-wpesys + - mediatek,mt8195-wpesys_vpp0 + - mediatek,mt8195-wpesys_vpp1 + - mediatek,mt8195-vppsys1 + - mediatek,mt8195-imgsys + - mediatek,mt8195-imgsys1_dip_top + - mediatek,mt8195-imgsys1_dip_nr + - mediatek,mt8195-imgsys1_wpe + - mediatek,mt8195-ipesys + - mediatek,mt8195-camsys + - mediatek,mt8195-camsys_rawa + - mediatek,mt8195-camsys_yuva + - mediatek,mt8195-camsys_rawb + - mediatek,mt8195-camsys_yuvb + - mediatek,mt8195-camsys_mraw + - mediatek,mt8195-ccusys + - mediatek,mt8195-vdecsys_soc + - mediatek,mt8195-vdecsys + - mediatek,mt8195-vdecsys_core1 + - mediatek,mt8195-vencsys + - mediatek,mt8195-vencsys_core1 + - mediatek,mt8195-apusys_pll + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8195-scp_adsp"; + reg = <0x10720000 0x1000>; + #clock-cells = <1>; + }; + + - | + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8195-imp_iic_wrap_s"; + reg = <0x11d03000 0x1000>; + #clock-cells = <1>; + }; + + - | + imp_iic_wrap_w: clock-controller@11e05000 { + compatible = "mediatek,mt8195-imp_iic_wrap_w"; + reg = <0x11e05000 0x1000>; + #clock-cells = <1>; + }; + + - | + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8195-mfgcfg"; + reg = <0x13fbf000 0x1000>; + #clock-cells = <1>; + }; + + - | + vppsys0: clock-controller@14000000 { + compatible = "mediatek,mt8195-vppsys0"; + reg = <0x14000000 0x1000>; + #clock-cells = <1>; + }; + + - | + wpesys: clock-controller@14e00000 { + compatible = "mediatek,mt8195-wpesys"; + reg = <0x14e00000 0x1000>; + #clock-cells = <1>; + }; + + - | + wpesys_vpp0: clock-controller@14e02000 { + compatible = "mediatek,mt8195-wpesys_vpp0"; + reg = <0x14e02000 0x1000>; + #clock-cells = <1>; + }; + + - | + wpesys_vpp1: clock-controller@14e03000 { + compatible = "mediatek,mt8195-wpesys_vpp1"; + reg = <0x14e03000 0x1000>; + #clock-cells = <1>; + }; + + - | + vppsys1: clock-controller@14f00000 { + compatible = "mediatek,mt8195-vppsys1"; + reg = <0x14f00000 0x1000>; + #clock-cells = <1>; + }; + + - | + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8195-imgsys"; + reg = <0x15000000 0x1000>; + #clock-cells = <1>; + }; + + - | + imgsys1_dip_top: clock-controller@15110000 { + compatible = "mediatek,mt8195-imgsys1_dip_top"; + reg = <0x15110000 0x1000>; + #clock-cells = <1>; + }; + + - | + imgsys1_dip_nr: clock-controller@15130000 { + compatible = "mediatek,mt8195-imgsys1_dip_nr"; + reg = <0x15130000 0x1000>; + #clock-cells = <1>; + }; + + - | + imgsys1_wpe: clock-controller@15220000 { + compatible = "mediatek,mt8195-imgsys1_wpe"; + reg = <0x15220000 0x1000>; + #clock-cells = <1>; + }; + + - | + ipesys: clock-controller@15330000 { + compatible = "mediatek,mt8195-ipesys"; + reg = <0x15330000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys: clock-controller@16000000 { + compatible = "mediatek,mt8195-camsys"; + reg = <0x16000000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys_rawa: clock-controller@1604f000 { + compatible = "mediatek,mt8195-camsys_rawa"; + reg = <0x1604f000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys_yuva: clock-controller@1606f000 { + compatible = "mediatek,mt8195-camsys_yuva"; + reg = <0x1606f000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys_rawb: clock-controller@1608f000 { + compatible = "mediatek,mt8195-camsys_rawb"; + reg = <0x1608f000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys_yuvb: clock-controller@160af000 { + compatible = "mediatek,mt8195-camsys_yuvb"; + reg = <0x160af000 0x1000>; + #clock-cells = <1>; + }; + + - | + camsys_mraw: clock-controller@16140000 { + compatible = "mediatek,mt8195-camsys_mraw"; + reg = <0x16140000 0x1000>; + #clock-cells = <1>; + }; + + - | + ccusys: clock-controller@17200000 { + compatible = "mediatek,mt8195-ccusys"; + reg = <0x17200000 0x1000>; + #clock-cells = <1>; + }; + + - | + vdecsys_soc: clock-controller@1800f000 { + compatible = "mediatek,mt8195-vdecsys_soc"; + reg = <0x1800f000 0x1000>; + #clock-cells = <1>; + }; + + - | + vdecsys: clock-controller@1802f000 { + compatible = "mediatek,mt8195-vdecsys"; + reg = <0x1802f000 0x1000>; + #clock-cells = <1>; + }; + + - | + vdecsys_core1: clock-controller@1803f000 { + compatible = "mediatek,mt8195-vdecsys_core1"; + reg = <0x1803f000 0x1000>; + #clock-cells = <1>; + }; + + - | + vencsys: clock-controller@1a000000 { + compatible = "mediatek,mt8195-vencsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + }; + + - | + vencsys_core1: clock-controller@1b000000 { + compatible = "mediatek,mt8195-vencsys_core1"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + }; + + - | + apusys_pll: clock-controller@190f3000 { + compatible = "mediatek,mt8195-apusys_pll"; + reg = <0x190f3000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml new file mode 100644 index 0000000000..57a1503d95 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek System Clock Controller for MT8195 + +maintainers: + - Chun-Jie Chen + +description: + The clock architecture in Mediatek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8195-topckgen + - mediatek,mt8195-infracfg_ao + - mediatek,mt8195-apmixedsys + - mediatek,mt8195-pericfg_ao + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + - | + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg_ao", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + }; + + - | + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0x1000c000 0x1000>; + #clock-cells = <1>; + }; + + - | + pericfg_ao: syscon@11003000 { + compatible = "mediatek,mt8195-pericfg_ao", "syscon"; + reg = <0x11003000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml index 880ddafc63..c8808e0f9e 100644 --- a/dts/Bindings/arm/qcom.yaml +++ b/dts/Bindings/arm/qcom.yaml @@ -25,6 +25,7 @@ description: | The 'SoC' element must be one of the following strings: apq8016 + apq8026 apq8074 apq8084 apq8096 @@ -44,6 +45,8 @@ description: | sdm660 sdm845 sdx55 + sdx65 + sm7225 sm8150 sm8250 sm8350 @@ -94,6 +97,14 @@ properties: - items: - enum: + - lg,lenok + - const: qcom,apq8026 + + - items: + - enum: + - asus,nexus7-flo + - lg,nexus4-mako + - sony,xperia-yuga - qcom,apq8064-cm-qs600 - qcom,apq8064-ifc6410 - const: qcom,apq8064 @@ -129,6 +140,7 @@ properties: - enum: - fairphone,fp2 - lge,hammerhead + - samsung,klte - sony,xperia-amami - sony,xperia-castor - sony,xperia-honami @@ -163,6 +175,7 @@ properties: - items: - enum: + - qcom,ipq4019-ap-dk01.1-c1 - qcom,ipq4019-ap-dk04.1-c3 - qcom,ipq4019-ap-dk07.1-c1 - qcom,ipq4019-ap-dk07.1-c2 @@ -206,6 +219,11 @@ properties: - qcom,sdx55-t55 - const: qcom,sdx55 + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + - items: - enum: - qcom,ipq6018-cp01 @@ -217,6 +235,11 @@ properties: - qcom,sa8155p-adp - const: qcom,sa8155p + - items: + - enum: + - fairphone,fp4 + - const: qcom,sm7225 + - items: - enum: - qcom,sm8150-mtp diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml index 8a11918866..5172065078 100644 --- a/dts/Bindings/arm/renesas.yaml +++ b/dts/Bindings/arm/renesas.yaml @@ -255,12 +255,19 @@ properties: - enum: - renesas,h3ulcb - renesas,m3ulcb + - renesas,m3nulcb - enum: + - renesas,r8a779m0 - renesas,r8a779m1 + - renesas,r8a779m2 - renesas,r8a779m3 + - renesas,r8a779m4 + - renesas,r8a779m5 + - renesas,r8a779m8 - enum: - renesas,r8a7795 - renesas,r8a77961 + - renesas,r8a77965 - description: R-Car M3-N (R8A77965) items: @@ -308,6 +315,14 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car H3e (R8A779M0) + items: + - enum: + - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779m0 + - const: renesas,r8a7795 + - description: R-Car H3e-2G (R8A779M1) items: - enum: @@ -316,6 +331,14 @@ properties: - const: renesas,r8a779m1 - const: renesas,r8a7795 + - description: R-Car M3e (R8A779M2) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779m2 + - const: renesas,r8a77961 + - description: R-Car M3e-2G (R8A779M3) items: - enum: @@ -324,6 +347,44 @@ properties: - const: renesas,r8a779m3 - const: renesas,r8a77961 + - description: R-Car M3Ne (R8A779M4) + items: + - enum: + - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779m4 + - const: renesas,r8a77965 + + - description: R-Car M3Ne-2G (R8A779M5) + items: + - enum: + - renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779m5 + - const: renesas,r8a77965 + + - description: R-Car E3e (R8A779M6) + items: + - enum: + - renesas,ebisu # Ebisu + - const: renesas,r8a779m6 + - const: renesas,r8a77990 + + - description: R-Car D3e (R8A779M7) + items: + - enum: + - renesas,draak # Draak + - const: renesas,r8a779m7 + - const: renesas,r8a77995 + + - description: R-Car H3Ne (R8A779M8) + items: + - enum: + - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779m8 + - const: renesas,r8a7795 + - description: RZ/N1D (R9A06G032) items: - enum: diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml index 6546b015fc..4aed161764 100644 --- a/dts/Bindings/arm/rockchip.yaml +++ b/dts/Bindings/arm/rockchip.yaml @@ -115,6 +115,11 @@ properties: - const: firefly,roc-rk3328-cc - const: rockchip,rk3328 + - description: Firefly ROC-RK3328-PC + items: + - const: firefly,roc-rk3328-pc + - const: rockchip,rk3328 + - description: Firefly ROC-RK3399-PC items: - enum: @@ -122,6 +127,12 @@ properties: - firefly,roc-rk3399-pc-mezzanine - const: rockchip,rk3399 + - description: Firefly ROC-RK3399-PC-PLUS + items: + - enum: + - firefly,roc-rk3399-pc-plus + - const: rockchip,rk3399 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s @@ -287,6 +298,34 @@ properties: - const: google,veyron - const: rockchip,rk3288 + - description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100) + items: + - const: google,scarlet-rev15-sku0 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku0 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku0 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku0 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku0 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku0 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku0 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku0 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku0 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku0 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku0 + - const: google,scarlet-rev5 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) items: - const: google,scarlet-rev15-sku7 @@ -455,16 +494,23 @@ properties: - const: pine64,rockpro64 - const: rockchip,rk3399 + - description: Pine64 Quartz64 Model A + items: + - const: pine64,quartz64-a + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock - const: rockchip,rk3188 - - description: Radxa ROCK Pi 4A/B/C + - description: Radxa ROCK Pi 4A/A+/B/B+/C items: - enum: - radxa,rockpi4a + - radxa,rockpi4a-plus - radxa,rockpi4b + - radxa,rockpi4b-plus - radxa,rockpi4c - const: radxa,rockpi4 - const: rockchip,rk3399 diff --git a/dts/Bindings/arm/rockchip/pmu.yaml b/dts/Bindings/arm/rockchip/pmu.yaml index 53115b92d1..5ece38065e 100644 --- a/dts/Bindings/arm/rockchip/pmu.yaml +++ b/dts/Bindings/arm/rockchip/pmu.yaml @@ -22,7 +22,9 @@ select: - rockchip,px30-pmu - rockchip,rk3066-pmu - rockchip,rk3288-pmu + - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3568-pmu required: - compatible @@ -34,7 +36,9 @@ properties: - rockchip,px30-pmu - rockchip,rk3066-pmu - rockchip,rk3288-pmu + - rockchip,rk3368-pmu - rockchip,rk3399-pmu + - rockchip,rk3568-pmu - const: syscon - const: simple-mfd diff --git a/dts/Bindings/arm/samsung/exynos-chipid.yaml b/dts/Bindings/arm/samsung/exynos-chipid.yaml index f99c0c6df2..bfc352a2fd 100644 --- a/dts/Bindings/arm/samsung/exynos-chipid.yaml +++ b/dts/Bindings/arm/samsung/exynos-chipid.yaml @@ -11,8 +11,9 @@ maintainers: properties: compatible: - items: - - const: samsung,exynos4210-chipid + enum: + - samsung,exynos4210-chipid + - samsung,exynos850-chipid reg: maxItems: 1 diff --git a/dts/Bindings/arm/samsung/samsung-boards.yaml b/dts/Bindings/arm/samsung/samsung-boards.yaml index 0796f0c877..ef6dc14be4 100644 --- a/dts/Bindings/arm/samsung/samsung-boards.yaml +++ b/dts/Bindings/arm/samsung/samsung-boards.yaml @@ -199,6 +199,12 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos Auto v9 based boards + items: + - enum: + - samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK + - const: samsung,exynosautov9 + required: - compatible diff --git a/dts/Bindings/arm/sprd/sprd.yaml b/dts/Bindings/arm/sprd/sprd.yaml index 7b6ae30703..2c12e57139 100644 --- a/dts/Bindings/arm/sprd/sprd.yaml +++ b/dts/Bindings/arm/sprd/sprd.yaml @@ -30,6 +30,11 @@ properties: - sprd,sp9863a-1h10 - const: sprd,sc9863a + - items: + - enum: + - sprd,ums512-1h10 + - const: sprd,ums512 + additionalProperties: true ... diff --git a/dts/Bindings/arm/sti.yaml b/dts/Bindings/arm/sti.yaml index b1f28d16d3..a41cd87648 100644 --- a/dts/Bindings/arm/sti.yaml +++ b/dts/Bindings/arm/sti.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST STi Platforms Device Tree Bindings maintainers: - - Patrice Chotard + - Patrice Chotard properties: $nodename: diff --git a/dts/Bindings/arm/stm32/st,mlahb.yaml b/dts/Bindings/arm/stm32/st,mlahb.yaml index 8e711bd202..ecb28e90fd 100644 --- a/dts/Bindings/arm/stm32/st,mlahb.yaml +++ b/dts/Bindings/arm/stm32/st,mlahb.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 ML-AHB interconnect bindings maintainers: - - Fabien Dessenne - - Arnaud Pouliquen + - Fabien Dessenne + - Arnaud Pouliquen description: | These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects diff --git a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml index 149afb5df5..6f846d69c5 100644 --- a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml +++ b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml @@ -7,8 +7,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 Platforms System Controller bindings maintainers: - - Alexandre Torgue - - Christophe Roullier + - Alexandre Torgue + - Christophe Roullier properties: compatible: diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml index 9a77ab74be..bcaf7be3ab 100644 --- a/dts/Bindings/arm/stm32/stm32.yaml +++ b/dts/Bindings/arm/stm32/stm32.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Platforms Device Tree Bindings maintainers: - - Alexandre Torgue + - Alexandre Torgue properties: $nodename: @@ -55,6 +55,10 @@ properties: - enum: - st,stm32h750i-art-pi - const: st,stm32h750 + - items: + - enum: + - st,stm32mp135f-dk + - const: st,stm32mp135 - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box diff --git a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index e713a6fe4c..29c9961ee2 100644 --- a/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/dts/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -30,6 +30,7 @@ properties: enum: - allwinner,sun5i-a13-mbus - allwinner,sun8i-h3-mbus + - allwinner,sun8i-r40-mbus - allwinner,sun50i-a64-mbus reg: diff --git a/dts/Bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml b/dts/Bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml new file mode 100644 index 0000000000..f3878e0b3c --- /dev/null +++ b/dts/Bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner CPU Configuration Controller Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + enum: + - allwinner,sun6i-a31-cpuconfig + - allwinner,sun8i-a23-cpuconfig + - allwinner,sun8i-a83t-cpucfg + - allwinner,sun8i-a83t-r-cpucfg + - allwinner,sun9i-a80-cpucfg + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cpucfg@1f01c00 { + compatible = "allwinner,sun6i-a31-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + +... diff --git a/dts/Bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml b/dts/Bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml new file mode 100644 index 0000000000..668aadbfe4 --- /dev/null +++ b/dts/Bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun9i-a80-prcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 PRCM Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + compatible: + const: allwinner,sun9i-a80-prcm + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + prcm@8001400 { + compatible = "allwinner,sun9i-a80-prcm"; + reg = <0x08001400 0x200>; + }; + +... diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml index c5aa362e40..cf327230fc 100644 --- a/dts/Bindings/arm/ti/k3.yaml +++ b/dts/Bindings/arm/ti/k3.yaml @@ -24,16 +24,27 @@ properties: - enum: - ti,am654-evm - siemens,iot2050-basic + - siemens,iot2050-basic-pg2 - siemens,iot2050-advanced + - siemens,iot2050-advanced-pg2 - const: ti,am654 - description: K3 J721E SoC - items: + oneOf: - const: ti,j721e + - items: + - enum: + - ti,j721e-evm + - ti,j721e-sk + - const: ti,j721e - description: K3 J7200 SoC - items: + oneOf: - const: ti,j7200 + - items: + - enum: + - ti,j7200-evm + - const: ti,j7200 - description: K3 AM642 SoC items: diff --git a/dts/Bindings/arm/toshiba.yaml b/dts/Bindings/arm/toshiba.yaml index 001bbbcd14..9c1cacbdc9 100644 --- a/dts/Bindings/arm/toshiba.yaml +++ b/dts/Bindings/arm/toshiba.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board + - toshiba,tmpv7708-visrobo-vrb # TMPV7708 VisROBO VRB board - const: toshiba,tmpv7708 additionalProperties: true diff --git a/dts/Bindings/arm/xilinx.yaml b/dts/Bindings/arm/xilinx.yaml index f52c7e8ce6..4dc0e01959 100644 --- a/dts/Bindings/arm/xilinx.yaml +++ b/dts/Bindings/arm/xilinx.yaml @@ -87,6 +87,7 @@ properties: - xlnx,zynqmp-zcu102-revA - xlnx,zynqmp-zcu102-revB - xlnx,zynqmp-zcu102-rev1.0 + - xlnx,zynqmp-zcu102-rev1.1 - const: xlnx,zynqmp-zcu102 - const: xlnx,zynqmp @@ -115,6 +116,22 @@ properties: - const: xlnx,zynqmp-zcu111 - const: xlnx,zynqmp + - description: Xilinx Kria SOMs + items: + - const: xlnx,zynqmp-sm-k26-rev1 + - const: xlnx,zynqmp-sm-k26-revB + - const: xlnx,zynqmp-sm-k26-revA + - const: xlnx,zynqmp-sm-k26 + - const: xlnx,zynqmp + + - description: Xilinx Kria SOMs (starter) + items: + - const: xlnx,zynqmp-smk-k26-rev1 + - const: xlnx,zynqmp-smk-k26-revB + - const: xlnx,zynqmp-smk-k26-revA + - const: xlnx,zynqmp-smk-k26 + - const: xlnx,zynqmp + additionalProperties: true ... diff --git a/dts/Bindings/auxdisplay/holtek,ht16k33.yaml b/dts/Bindings/auxdisplay/holtek,ht16k33.yaml index 64ffff4600..fc4873deb7 100644 --- a/dts/Bindings/auxdisplay/holtek,ht16k33.yaml +++ b/dts/Bindings/auxdisplay/holtek,ht16k33.yaml @@ -14,14 +14,21 @@ allOf: properties: compatible: - const: holtek,ht16k33 + oneOf: + - items: + - enum: + - adafruit,3108 # 0.56" 4-Digit 7-Segment FeatherWing Display (Red) + - adafruit,3130 # 0.54" Quad Alphanumeric FeatherWing Display (Red) + - const: holtek,ht16k33 + + - const: holtek,ht16k33 # Generic 16*8 LED controller with dot-matrix display reg: maxItems: 1 refresh-rate-hz: maxItems: 1 - description: Display update interval in Hertz + description: Display update interval in Hertz for dot-matrix displays interrupts: maxItems: 1 @@ -41,10 +48,22 @@ properties: default: 16 description: Initial brightness level + led: + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + required: - compatible - reg - - refresh-rate-hz + +if: + properties: + compatible: + const: holtek,ht16k33 +then: + required: + - refresh-rate-hz additionalProperties: false @@ -52,6 +71,7 @@ examples: - | #include #include + #include i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -73,5 +93,11 @@ examples: , , ; + + led { + color = ; + function = LED_FUNCTION_BACKLIGHT; + linux,default-trigger = "backlight"; + }; }; }; diff --git a/dts/Bindings/bus/palmbus.yaml b/dts/Bindings/bus/palmbus.yaml new file mode 100644 index 0000000000..f5cbfaf52d --- /dev/null +++ b/dts/Bindings/bus/palmbus.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/palmbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink PalmBus Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The ralink palmbus controller can be found in all ralink MIPS + SoCs. It provides an external bus for connecting multiple + external devices to the SoC. + +properties: + $nodename: + pattern: "^palmbus(@[0-9a-f]+)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + const: palmbus + + reg: + maxItems: 1 + + ranges: true + +patternProperties: + # All other properties should be child nodes with unit-address and 'reg' + "@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000000 0x0fffff>; + + gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + +... diff --git a/dts/Bindings/bus/ti-sysc.txt b/dts/Bindings/bus/ti-sysc.txt deleted file mode 100644 index c984143d08..0000000000 --- a/dts/Bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,139 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-dra7-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - "ti,sysc-pruss" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -- ti,no-idle interconnect target module should not be idled - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = , - , - ; - ti,sysc-sidle = , - , - , - ; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = , - ; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multiple child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnect target module. diff --git a/dts/Bindings/bus/ti-sysc.yaml b/dts/Bindings/bus/ti-sysc.yaml new file mode 100644 index 0000000000..bd40213302 --- /dev/null +++ b/dts/Bindings/bus/ti-sysc.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interconnect target module binding + +maintainers: + - Tony Lindgren + +description: + Texas Instruments SoCs can have a generic interconnect target module + for devices connected to various interconnects such as L3 interconnect + using Arteris NoC, and L4 interconnect using Sonics s3220. This module + is mostly used for interaction between module and Power, Reset and Clock + Manager PRCM. It participates in the OCP Disconnect Protocol, but other + than that it is mostly independent of the interconnect. + + Each interconnect target module can have one or more devices connected to + it. There is a set of control registers for managing the interconnect target + module clocks, idle modes and interconnect level resets. + + The interconnect target module control registers are sprinkled into the + unused register address space of the first child device IP block managed by + the interconnect target module. Typically the register names are REVISION, + SYSCONFIG and SYSSTATUS. + +properties: + $nodename: + pattern: "^target-module(@[0-9a-f]+)?$" + + compatible: + oneOf: + - items: + - enum: + - ti,sysc-omap2 + - ti,sysc-omap2 + - ti,sysc-omap4 + - ti,sysc-omap4-simple + - ti,sysc-omap2-timer + - ti,sysc-omap4-timer + - ti,sysc-omap3430-sr + - ti,sysc-omap3630-sr + - ti,sysc-omap4-sr + - ti,sysc-omap3-sham + - ti,sysc-omap-aes + - ti,sysc-mcasp + - ti,sysc-dra7-mcasp + - ti,sysc-usb-host-fs + - ti,sysc-dra7-mcan + - ti,sysc-pruss + - const: ti,sysc + - items: + - const: ti,sysc + + reg: + description: + Interconnect target module control registers consisting of + REVISION, SYSCONFIG and SYSSTATUS registers as defined in the + Technical Reference Manual for the SoC. + minItems: 1 + maxItems: 3 + + reg-names: + description: + Interconnect target module control register names consisting + of "rev", "sysc" and "syss". + oneOf: + - minItems: 1 + items: + - const: rev + - const: sysc + - const: syss + - items: + - const: rev + - const: syss + - enum: [ sysc, syss ] + + power-domains: + description: Target module power domain if available. + maxItems: 1 + + clocks: + description: + Target module clocks consisting of one functional clock, one + interface clock, and up to 8 module specific optional clocks. + Some modules may have only the functional clock, and some have + no configurable clocks. + minItems: 1 + maxItems: 4 + + clock-names: + description: + Target module clock names like "fck", "ick", "optck1", "optck2" + if the clocks are configurable. + oneOf: + - enum: [ ick, fck, sys_clk ] + - items: + - const: fck + - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ] + - items: + - const: fck + - const: phy-clk + - const: phy-clk-div + - items: + - const: fck + - const: hdmi_clk + - const: sys_clk + - const: tv_clk + - items: + - const: fck + - const: ahclkx + - const: ahclkr + + resets: + description: + Target module reset bit in the RSTCTRL register if wired for the module. + Note that the other reset bits should be mapped for the child device + driver to use. + maxItems: 1 + + reset-names: + description: + Target module reset names in the RSTCTRL register, typically named + "rstctrl" if only one reset bit is wired for the module. + items: + - const: rstctrl + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + dma-ranges: true + + ti,sysc-mask: + description: Mask of supported register bits for the SYSCONFIG register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-midle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,sysc-sidle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,syss-mask: + description: Mask of supported register bits for the SYSSTATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-delay-us: + description: Delay needed after OCP softreset before accessing SYCONFIG + default: 0 + minimum: 0 + maximum: 2 + + ti,no-reset-on-init: + description: Interconnect target module shall not be reset at init + type: boolean + + ti,no-idle-on-init: + description: Interconnect target module shall not be idled at init + type: boolean + + ti,no-idle: + description: Interconnect target module shall not be idled + type: boolean + + ti,hwmods: + description: Interconnect module name to use with legacy hwmod data + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: + type: object + +examples: + - | + #include + #include + + target-module@2b000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + }; diff --git a/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 3f995d2b30..e79eeac5f0 100644 --- a/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -24,7 +24,7 @@ properties: - const: allwinner,sun8i-v3s-de2-clk - const: allwinner,sun50i-a64-de2-clk - const: allwinner,sun50i-h5-de2-clk - - const: allwinner,sun50i-h6-de2-clk + - const: allwinner,sun50i-h6-de3-clk - items: - const: allwinner,sun8i-r40-de2-clk - const: allwinner,sun8i-h3-de2-clk diff --git a/dts/Bindings/clock/arm,syscon-icst.yaml b/dts/Bindings/clock/arm,syscon-icst.yaml index 118c5543e0..90eadf6869 100644 --- a/dts/Bindings/clock/arm,syscon-icst.yaml +++ b/dts/Bindings/clock/arm,syscon-icst.yaml @@ -69,6 +69,10 @@ properties: - arm,impd1-vco1 - arm,impd1-vco2 + reg: + maxItems: 1 + description: The VCO register + clocks: description: Parent clock for the ICST VCO maxItems: 1 @@ -83,6 +87,7 @@ properties: vco-offset: $ref: '/schemas/types.yaml#/definitions/uint32' description: Offset to the VCO register for the oscillator + deprecated: true required: - "#clock-cells" diff --git a/dts/Bindings/clock/fixed-mmio-clock.txt b/dts/Bindings/clock/fixed-mmio-clock.txt deleted file mode 100644 index c359367fd1..0000000000 --- a/dts/Bindings/clock/fixed-mmio-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for simple memory mapped io fixed-rate clock sources. -The driver reads a clock frequency value from a single 32-bit memory mapped -I/O register and registers it as a fixed rate clock. - -It was designed for test systems, like FPGA, not for complete, finished SoCs. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-mmio-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- reg : Address and length of the clock value register set. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: -sysclock: sysclock@fd020004 { - #clock-cells = <0>; - compatible = "fixed-mmio-clock"; - reg = <0xfd020004 0x4>; -}; diff --git a/dts/Bindings/clock/fixed-mmio-clock.yaml b/dts/Bindings/clock/fixed-mmio-clock.yaml new file mode 100644 index 0000000000..1453ac849a --- /dev/null +++ b/dts/Bindings/clock/fixed-mmio-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for simple memory mapped IO fixed-rate clock sources + +description: + This binding describes a fixed-rate clock for which the frequency can + be read from a single 32-bit memory mapped I/O register. + + It was designed for test systems, like FPGA, not for complete, + finished SoCs. + +maintainers: + - Jan Kotas + +properties: + compatible: + const: fixed-mmio-clock + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + sysclock: sysclock@fd020004 { + compatible = "fixed-mmio-clock"; + #clock-cells = <0>; + reg = <0xfd020004 0x4>; + clock-output-names = "sysclk"; + }; +... diff --git a/dts/Bindings/clock/imx8ulp-cgc-clock.yaml b/dts/Bindings/clock/imx8ulp-cgc-clock.yaml new file mode 100644 index 0000000000..71f7186b13 --- /dev/null +++ b/dts/Bindings/clock/imx8ulp-cgc-clock.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding + +maintainers: + - Jacky Bai + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The CGC modules generate + and distribute clocks on the device. + +properties: + compatible: + enum: + - fsl,imx8ulp-cgc1 + - fsl,imx8ulp-cgc2 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Generation & Control Module node: + - | + clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/imx8ulp-pcc-clock.yaml b/dts/Bindings/clock/imx8ulp-pcc-clock.yaml new file mode 100644 index 0000000000..00612725bf --- /dev/null +++ b/dts/Bindings/clock/imx8ulp-pcc-clock.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding + +maintainers: + - Jacky Bai + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The PCC modules control + software reset, clock selection, optional division and clock gating mode + for peripherals. + +properties: + compatible: + enum: + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + # Peripheral Clock Control Module node: + - | + clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/ingenic,cgu.yaml b/dts/Bindings/clock/ingenic,cgu.yaml index 6e80dbc8b8..aa1df03ef4 100644 --- a/dts/Bindings/clock/ingenic,cgu.yaml +++ b/dts/Bindings/clock/ingenic,cgu.yaml @@ -104,7 +104,7 @@ additionalProperties: false examples: - | - #include + #include cgu: clock-controller@10000000 { compatible = "ingenic,jz4770-cgu", "simple-mfd"; reg = <0x10000000 0x100>; diff --git a/dts/Bindings/clock/maxim,max77686.txt b/dts/Bindings/clock/maxim,max77686.txt index 3472b461ca..c10849efb4 100644 --- a/dts/Bindings/clock/maxim,max77686.txt +++ b/dts/Bindings/clock/maxim,max77686.txt @@ -49,7 +49,7 @@ Example: max77686: max77686@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; #clock-cells = <1>; @@ -74,7 +74,7 @@ Example: max77802: max77802@9 { compatible = "maxim,max77802"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; #clock-cells = <1>; diff --git a/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml index 6667261dc6..31497677e8 100644 --- a/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml @@ -56,6 +56,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - reg @@ -70,6 +80,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -90,5 +101,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/dts/Bindings/clock/qcom,gcc-msm8994.yaml b/dts/Bindings/clock/qcom,gcc-msm8994.yaml new file mode 100644 index 0000000000..22e67b238b --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8994.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8994 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8994 and MSM8992. + + See also: + - dt-bindings/clock/qcom,gcc-msm8994.h + +properties: + compatible: + enum: + - qcom,gcc-msm8992 + - qcom,gcc-msm8994 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8994"; + reg = <0x00300000 0x90000>; + clocks = <&xo_board>, <&sleep_clk>; + clock-names = "xo", "sleep"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8998.yaml b/dts/Bindings/clock/qcom,gcc-msm8998.yaml index a0bb713929..8151c0a056 100644 --- a/dts/Bindings/clock/qcom,gcc-msm8998.yaml +++ b/dts/Bindings/clock/qcom,gcc-msm8998.yaml @@ -25,21 +25,17 @@ properties: items: - description: Board XO source - description: Sleep clock source - - description: USB 3.0 phy pipe clock - - description: UFS phy rx symbol clock for pipe 0 - - description: UFS phy rx symbol clock for pipe 1 - - description: UFS phy tx symbol clock - - description: PCIE phy pipe clock + - description: Audio reference clock (Optional clock) + - description: PLL test clock source (Optional clock) + minItems: 2 clock-names: items: - const: xo - const: sleep_clk - - const: usb3_pipe - - const: ufs_rx_symbol0 - - const: ufs_rx_symbol1 - - const: ufs_tx_symbol0 - - const: pcie0_pipe + - const: aud_ref_clk # Optional clock + - const: core_bi_pll_test_se # Optional clock + minItems: 2 '#clock-cells': const: 1 @@ -80,16 +76,10 @@ examples: clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep>, <0>, - <0>, - <0>, - <0>, <0>; clock-names = "xo", "sleep_clk", - "usb3_pipe", - "ufs_rx_symbol0", - "ufs_rx_symbol1", - "ufs_tx_symbol0", - "pcie0_pipe"; + "aud_ref_clk", + "core_bi_pll_test_se"; }; ... diff --git a/dts/Bindings/clock/qcom,gcc-qcm2290.yaml b/dts/Bindings/clock/qcom,gcc-qcm2290.yaml new file mode 100644 index 0000000000..5de9c82631 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-qcm2290.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for QCM2290 + +maintainers: + - Shawn Guo + +description: | + Qualcomm global clock control module which supports the clocks, resets + and power domains on QCM2290. + + See also: + - dt-bindings/clock/qcom,gcc-qcm2290.h + +properties: + compatible: + const: qcom,gcc-qcm2290 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@1400000 { + compatible = "qcom,gcc-qcm2290"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc.yaml b/dts/Bindings/clock/qcom,gcc.yaml index 2f20f8aa93..f66d703bd9 100644 --- a/dts/Bindings/clock/qcom,gcc.yaml +++ b/dts/Bindings/clock/qcom,gcc.yaml @@ -29,7 +29,6 @@ description: | - dt-bindings/reset/qcom,gcc-msm8660.h - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - - dt-bindings/clock/qcom,gcc-msm8994.h - dt-bindings/clock/qcom,gcc-mdm9607.h - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h @@ -52,7 +51,6 @@ properties: - qcom,gcc-msm8974 - qcom,gcc-msm8974pro - qcom,gcc-msm8974pro-ac - - qcom,gcc-msm8994 - qcom,gcc-mdm9615 - qcom,gcc-sdm630 - qcom,gcc-sdm660 diff --git a/dts/Bindings/clock/qcom,rpmcc.txt b/dts/Bindings/clock/qcom,rpmcc.txt index a4877881f1..da295c3c00 100644 --- a/dts/Bindings/clock/qcom,rpmcc.txt +++ b/dts/Bindings/clock/qcom,rpmcc.txt @@ -25,6 +25,7 @@ Required properties : "qcom,rpmcc-msm8994",·"qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-msm8998", "qcom,rpmcc" + "qcom,rpmcc-qcm2290", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" "qcom,rpmcc-sdm660", "qcom,rpmcc" "qcom,rpmcc-sm6115", "qcom,rpmcc" diff --git a/dts/Bindings/clock/qcom,sc7280-camcc.yaml b/dts/Bindings/clock/qcom,sc7280-camcc.yaml new file mode 100644 index 0000000000..f27ca6f03f --- /dev/null +++ b/dts/Bindings/clock/qcom,sc7280-camcc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SC7280 + +maintainers: + - Taniya Das + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SC7280. + + See also dt-bindings/clock/qcom,camcc-sc7280.h + +properties: + compatible: + const: qcom,sc7280-camcc + + clocks: + items: + - description: Board XO source + - description: Board XO active source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@ad00000 { + compatible = "qcom,sc7280-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml b/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml new file mode 100644 index 0000000000..47028d7b98 --- /dev/null +++ b/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpass-sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-lpasscc + + clocks: + items: + - description: gcc_cfg_noc_lpass_clk from GCC + + clock-names: + items: + - const: iface + + '#clock-cells': + const: 1 + + reg: + items: + - description: LPASS qdsp6ss register + - description: LPASS top-cc register + - description: LPASS cc register + + reg-names: + items: + - const: qdsp6ss + - const: top_cc + - const: cc + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,videocc.yaml b/dts/Bindings/clock/qcom,videocc.yaml index 0d224f114b..3cdbcebdc1 100644 --- a/dts/Bindings/clock/qcom,videocc.yaml +++ b/dts/Bindings/clock/qcom,videocc.yaml @@ -49,6 +49,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - reg @@ -63,6 +73,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -71,5 +82,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/dts/Bindings/clock/samsung,exynos850-clock.yaml b/dts/Bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index 0000000000..7f8c91a29b --- /dev/null +++ b/dts/Bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko + - Chanwoo Choi + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: + enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: eMMC clock (from CMU_TOP) + - description: SSS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_mmc_embd + - const: dout_core_sss + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_dpu + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-hsi + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI bus clock (from CMU_TOP) + - description: SD card clock (from CMU_TOP) + - description: "USB 2.0 DRD clock (from CMU_TOP)" + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: dout_hsi_bus + - const: dout_hsi_mmc_card + - const: dout_hsi_usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: UART clock (from CMU_TOP) + - description: Parent clock for HSI2C and SPI (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_uart + - const: dout_peri_ip + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + +... diff --git a/dts/Bindings/clock/samsung,s2mps11.txt b/dts/Bindings/clock/samsung,s2mps11.txt deleted file mode 100644 index 2726c1d58a..0000000000 --- a/dts/Bindings/clock/samsung,s2mps11.txt +++ /dev/null @@ -1,49 +0,0 @@ -Binding for Samsung S2M and S5M family clock generator block -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz -outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs. - -To register these as clocks with common clock framework instantiate under -main device node a sub-node named "clocks". - -It uses the common clock binding documented in: - - Documentation/devicetree/bindings/clock/clock-bindings.txt - - -Required properties of the "clocks" sub-node: - - #clock-cells: should be 1. - - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" - The S2MPS15 uses the same compatible as S2MPS13, as both provides similar - clocks. - - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - Clock ID Devices - ---------------------------------------------------------- - 32KhzAP 0 S2MPS11/13/14/15, S5M8767 - 32KhzCP 1 S2MPS11/13/15, S5M8767 - 32KhzBT 2 S2MPS11/13/14/15, S5M8767 - -Include dt-bindings/clock/samsung,s2mps11.h file to use preprocessor defines -in device tree sources. - - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - }; diff --git a/dts/Bindings/clock/samsung,s2mps11.yaml b/dts/Bindings/clock/samsung,s2mps11.yaml new file mode 100644 index 0000000000..1410c51e0e --- /dev/null +++ b/dts/Bindings/clock/samsung,s2mps11.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,s2mps11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2M and S5M family clock generator block + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz + outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs. + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/samsung,s2mps11.h header. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mps11-clk + - samsung,s2mps13-clk # S2MPS13 and S2MPS15 + - samsung,s2mps14-clk + - samsung,s5m8767-clk + + "#clock-cells": + const: 1 + + clock-output-names: + minItems: 3 + maxItems: 3 + description: Names for AP, CP and BT clocks. + +required: + - compatible + - "#clock-cells" + +additionalProperties: false diff --git a/dts/Bindings/clock/sifive/fu740-prci.yaml b/dts/Bindings/clock/sifive/fu740-prci.yaml index e17143cac3..252085a0cf 100644 --- a/dts/Bindings/clock/sifive/fu740-prci.yaml +++ b/dts/Bindings/clock/sifive/fu740-prci.yaml @@ -42,6 +42,9 @@ properties: "#clock-cells": const: 1 + "#reset-cells": + const: 1 + required: - compatible - reg @@ -57,4 +60,5 @@ examples: reg = <0x10000000 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; diff --git a/dts/Bindings/clock/silabs,si5351.txt b/dts/Bindings/clock/silabs,si5351.txt index 8fe6f80afa..bfda6af76b 100644 --- a/dts/Bindings/clock/silabs,si5351.txt +++ b/dts/Bindings/clock/silabs,si5351.txt @@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. Reference [1] Si5351A/B/C Data Sheet - https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf The Si5351a/b/c are programmable i2c clock generators with up to 8 output clocks. Si5351a also has a reduced pin-count package (MSOP10) where only diff --git a/dts/Bindings/clock/socionext,uniphier-clock.yaml b/dts/Bindings/clock/socionext,uniphier-clock.yaml index c3930edc41..9a0cc73416 100644 --- a/dts/Bindings/clock/socionext,uniphier-clock.yaml +++ b/dts/Bindings/clock/socionext,uniphier-clock.yaml @@ -23,6 +23,7 @@ properties: - socionext,uniphier-ld11-clock - socionext,uniphier-ld20-clock - socionext,uniphier-pxs3-clock + - socionext,uniphier-nx1-clock - description: Media I/O (MIO) clock, SD clock enum: - socionext,uniphier-ld4-mio-clock @@ -33,6 +34,7 @@ properties: - socionext,uniphier-ld11-mio-clock - socionext,uniphier-ld20-sd-clock - socionext,uniphier-pxs3-sd-clock + - socionext,uniphier-nx1-sd-clock - description: Peripheral clock enum: - socionext,uniphier-ld4-peri-clock @@ -43,6 +45,10 @@ properties: - socionext,uniphier-ld11-peri-clock - socionext,uniphier-ld20-peri-clock - socionext,uniphier-pxs3-peri-clock + - socionext,uniphier-nx1-peri-clock + - description: SoC-glue clock + enum: + - socionext,uniphier-pro4-sg-clock "#clock-cells": const: 1 diff --git a/dts/Bindings/clock/st,stm32mp1-rcc.yaml b/dts/Bindings/clock/st,stm32mp1-rcc.yaml index 8b1ecb2ecd..a0ae4867ed 100644 --- a/dts/Bindings/clock/st,stm32mp1-rcc.yaml +++ b/dts/Bindings/clock/st,stm32mp1-rcc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Reset Clock Controller Binding maintainers: - - Gabriel Fernandez + - Gabriel Fernandez description: | The RCC IP is both a reset and a clock controller. diff --git a/dts/Bindings/clock/stericsson,u8500-clks.yaml b/dts/Bindings/clock/stericsson,u8500-clks.yaml new file mode 100644 index 0000000000..9bc95a3084 --- /dev/null +++ b/dts/Bindings/clock/stericsson,u8500-clks.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST-Ericsson DB8500 (U8500) clocks + +maintainers: + - Ulf Hansson + - Linus Walleij + +description: While named "U8500 clocks" these clocks are inside the + DB8500 digital baseband system-on-chip and its siblings such as + DB8520. These bindings consider the clocks present in the SoC + itself, not off-chip clocks. There are four different on-chip + clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and + control management unit) clocks and PRCC (peripheral reset and + clock controller) clocks. For some reason PRCC 4 does not exist so + the itemization can be a bit unintuitive. + +properties: + compatible: + enum: + - stericsson,u8500-clks + - stericsson,u8540-clks + - stericsson,u9540-clks + + reg: + items: + - description: PRCC 1 register area + - description: PRCC 2 register area + - description: PRCC 3 register area + - description: PRCC 5 register area + - description: PRCC 6 register area + + prcmu-clock: + description: A subnode with one clock cell for PRCMU (power, reset, control + management unit) clocks. The cell indicates which PRCMU clock in the + prcmu-clock node the consumer wants to use. + type: object + + properties: + '#clock-cells': + const: 1 + + additionalProperties: false + + prcc-periph-clock: + description: A subnode with two clock cells for PRCC (peripheral + reset and clock controller) peripheral clocks. The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3, + 5, 6. The second cell indicates which clock inside the PRCC block it + wants, possible values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-kernel-clock: + description: A subnode with two clock cells for PRCC (peripheral reset + and clock controller) kernel clocks. The first cell indicates which PRCC + block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The + second cell indicates which clock inside the PRCC block it wants, possible + values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-reset-controller: + description: A subnode with two reset cells for the reset portions of the + PRCC (peripheral reset and clock controller). The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3 + 5 and 6. The second cell indicates which reset line inside the PRCC block + it wants to control, possible values are 0 thru 31. + type: object + + properties: + '#reset-cells': + const: 2 + + additionalProperties: false + + rtc32k-clock: + description: A subnode with zero clock cells for the 32kHz RTC clock. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + + smp-twd-clock: + description: A subnode for the ARM SMP Timer Watchdog cluster with zero + clock cells. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + +required: + - compatible + - reg + - prcmu-clock + - prcc-periph-clock + - prcc-kernel-clock + - rtc32k-clock + - smp-twd-clock + +additionalProperties: false diff --git a/dts/Bindings/clock/ux500.txt b/dts/Bindings/clock/ux500.txt deleted file mode 100644 index e52bd4b723..0000000000 --- a/dts/Bindings/clock/ux500.txt +++ /dev/null @@ -1,64 +0,0 @@ -Clock bindings for ST-Ericsson Ux500 clocks - -Required properties : -- compatible : shall contain only one of the following: - "stericsson,u8500-clks" - "stericsson,u8540-clks" - "stericsson,u9540-clks" -- reg : shall contain base register location and length for - CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of - CLKRST4, which does not exist. - -Required subnodes: -- prcmu-clock: a subnode with one clock cell for PRCMU (power, - reset, control unit) clocks. The cell indicates which PRCMU - clock in the prcmu-clock node the consumer wants to use. -- prcc-periph-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) peripheral clocks. - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- prcc-kernel-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) kernel clocks - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- rtc32k-clock: a subnode with zero clock cells for the 32kHz - RTC clock. -- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster - with zero clock cells. - -Example: - -clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; -}; diff --git a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml new file mode 100644 index 0000000000..a3c16451b1 --- /dev/null +++ b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay OCS ECC Device Tree Bindings + +maintainers: + - Daniele Alessandrelli + - Prabhjot Khurana + +description: + The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve + Cryptography (ECC) device provides hardware acceleration for elliptic curve + cryptography using the NIST P-256 and NIST P-384 elliptic curves. + +properties: + compatible: + const: intel,keembay-ocs-ecc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + crypto@30001000 { + compatible = "intel,keembay-ocs-ecc"; + reg = <0x30001000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 95>; + }; diff --git a/dts/Bindings/crypto/st,stm32-crc.yaml b/dts/Bindings/crypto/st,stm32-crc.yaml index cee624c14f..b72e4858f9 100644 --- a/dts/Bindings/crypto/st,stm32-crc.yaml +++ b/dts/Bindings/crypto/st,stm32-crc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRC bindings maintainers: - - Lionel Debieve + - Lionel Debieve properties: compatible: diff --git a/dts/Bindings/crypto/st,stm32-cryp.yaml b/dts/Bindings/crypto/st,stm32-cryp.yaml index a457455250..ed23bf94a8 100644 --- a/dts/Bindings/crypto/st,stm32-cryp.yaml +++ b/dts/Bindings/crypto/st,stm32-cryp.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CRYP bindings maintainers: - - Lionel Debieve + - Lionel Debieve properties: compatible: diff --git a/dts/Bindings/crypto/st,stm32-hash.yaml b/dts/Bindings/crypto/st,stm32-hash.yaml index 6dd658f091..10ba94792d 100644 --- a/dts/Bindings/crypto/st,stm32-hash.yaml +++ b/dts/Bindings/crypto/st,stm32-hash.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 HASH bindings maintainers: - - Lionel Debieve + - Lionel Debieve properties: compatible: diff --git a/dts/Bindings/ddr/lpddr2-timings.txt b/dts/Bindings/ddr/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7..0000000000 --- a/dts/Bindings/ddr/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; diff --git a/dts/Bindings/ddr/lpddr2.txt b/dts/Bindings/ddr/lpddr2.txt deleted file mode 100644 index ddd40121e6..0000000000 --- a/dts/Bindings/ddr/lpddr2.txt +++ /dev/null @@ -1,102 +0,0 @@ -* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 - -Required properties: -- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", - "jedec,lpddr2-s4" - - "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type - - "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type - - "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type - -- density : representing density in Mb (Mega bits) - -- io-width : representing bus width. Possible values are 8, 16, and 32 - -Optional properties: - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRRD-min-tck -- tWTR-min-tck -- tXP-min-tck -- tRTP-min-tck -- tCKE-min-tck -- tRPab-min-tck -- tRCD-min-tck -- tWR-min-tck -- tRASmin-min-tck -- tCKESR-min-tck -- tFAW-min-tck - -Child nodes: -- The lpddr2 node may have one or more child nodes of type "lpddr2-timings". - "lpddr2-timings" provides AC timing parameters of the device for - a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings" - -Example: - -elpida_ECB240ABACN : lpddr2 { - compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; - density = <2048>; - io-width = <32>; - - tRPab-min-tck = <3>; - tRCD-min-tck = <3>; - tWR-min-tck = <3>; - tRASmin-min-tck = <3>; - tRRD-min-tck = <2>; - tWTR-min-tck = <2>; - tXP-min-tck = <2>; - tRTP-min-tck = <2>; - tCKE-min-tck = <3>; - tCKESR-min-tck = <3>; - tFAW-min-tck = <8>; - - timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - - timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <200000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <10000>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; - }; - -} diff --git a/dts/Bindings/ddr/lpddr3-timings.txt b/dts/Bindings/ddr/lpddr3-timings.txt deleted file mode 100644 index 84705e50a3..0000000000 --- a/dts/Bindings/ddr/lpddr3-timings.txt +++ /dev/null @@ -1,58 +0,0 @@ -* AC timing parameters of LPDDR3 memories for a given speed-bin. - -The structures are based on LPDDR2 and extended where needed. - -Required properties: -- compatible : Should be "jedec,lpddr3-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- reg : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). -- tRFC -- tRRD -- tRPab -- tRPpb -- tRCD -- tRC -- tRAS -- tWTR -- tWR -- tRTP -- tW2W-C2C -- tR2R-C2C -- tFAW -- tXSR -- tXP -- tCKE -- tCKESR -- tMRD - -Example: - -timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; -}; diff --git a/dts/Bindings/ddr/lpddr3.txt b/dts/Bindings/ddr/lpddr3.txt deleted file mode 100644 index b221e653d3..0000000000 --- a/dts/Bindings/ddr/lpddr3.txt +++ /dev/null @@ -1,106 +0,0 @@ -* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C - -Required properties: -- compatible : Should be ",", and generic value "jedec,lpddr3". - Example "," values: - "samsung,K3QF2F20DB" - -- density : representing density in Mb (Mega bits) -- io-width : representing bus width. Possible values are 8, 16, 32, 64 -- #address-cells: Must be set to 1 -- #size-cells: Must be set to 0 - -Optional properties: - -- manufacturer-id : Manufacturer ID value read from Mode Register 5 -- revision-id : Revision IDs read from Mode Registers 6 and 7 - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRFC-min-tck -- tRRD-min-tck -- tRPab-min-tck -- tRPpb-min-tck -- tRCD-min-tck -- tRC-min-tck -- tRAS-min-tck -- tWTR-min-tck -- tWR-min-tck -- tRTP-min-tck -- tW2W-C2C-min-tck -- tR2R-C2C-min-tck -- tWL-min-tck -- tDQSCK-min-tck -- tRL-min-tck -- tFAW-min-tck -- tXSR-min-tck -- tXP-min-tck -- tCKE-min-tck -- tCKESR-min-tck -- tMRD-min-tck - -Child nodes: -- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". - "lpddr3-timings" provides AC timing parameters of the device for - a given speed-bin. Please see Documentation/devicetree/ - bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" - -Example: - -samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - manufacturer-id = <1>; - revision-id = <123 234>; - #address-cells = <1>; - #size-cells = <0>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; -} diff --git a/dts/Bindings/devfreq/rk3399_dmc.txt b/dts/Bindings/devfreq/rk3399_dmc.txt index 3fbeb3733c..58fc8a6ceb 100644 --- a/dts/Bindings/devfreq/rk3399_dmc.txt +++ b/dts/Bindings/devfreq/rk3399_dmc.txt @@ -174,7 +174,7 @@ Example: compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = ; - clocks = <&cru SCLK_DDRCLK>; + clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; diff --git a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml index 32608578a3..c8b2459d64 100644 --- a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml +++ b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml @@ -47,6 +47,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + required: - "#clock-cells" - compatible diff --git a/dts/Bindings/display/brcm,bcm2835-hdmi.yaml b/dts/Bindings/display/brcm,bcm2835-hdmi.yaml index 031e35e76d..48c8cad0d9 100644 --- a/dts/Bindings/display/brcm,bcm2835-hdmi.yaml +++ b/dts/Bindings/display/brcm,bcm2835-hdmi.yaml @@ -51,6 +51,9 @@ properties: dma-names: const: audio-rx + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/display/brcm,bcm2835-v3d.yaml b/dts/Bindings/display/brcm,bcm2835-v3d.yaml index 8a73780f57..c55a8217de 100644 --- a/dts/Bindings/display/brcm,bcm2835-v3d.yaml +++ b/dts/Bindings/display/brcm,bcm2835-v3d.yaml @@ -24,6 +24,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/display/brcm,bcm2835-vec.yaml b/dts/Bindings/display/brcm,bcm2835-vec.yaml index 9b24081a0d..5d921e3039 100644 --- a/dts/Bindings/display/brcm,bcm2835-vec.yaml +++ b/dts/Bindings/display/brcm,bcm2835-vec.yaml @@ -24,6 +24,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml index 304a1367fa..1faae3e323 100644 --- a/dts/Bindings/display/bridge/lvds-codec.yaml +++ b/dts/Bindings/display/bridge/lvds-codec.yaml @@ -49,11 +49,26 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base description: | For LVDS encoders, port 0 is the parallel input For LVDS decoders, port 0 is the LVDS input + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-mapping: + enum: + - jeida-18 + - jeida-24 + - vesa-24 + description: | + The color signals mapping order. See details in + Documentation/devicetree/bindings/display/panel/lvds.yaml + port@1: $ref: /schemas/graph.yaml#/properties/port description: | @@ -71,6 +86,22 @@ properties: power-supply: true +if: + not: + properties: + compatible: + contains: + const: lvds-decoder +then: + properties: + ports: + properties: + port@0: + properties: + endpoint: + properties: + data-mapping: false + required: - compatible - ports diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml index fce82b605c..cdaf7a7a8f 100644 --- a/dts/Bindings/display/bridge/ps8640.yaml +++ b/dts/Bindings/display/bridge/ps8640.yaml @@ -40,6 +40,9 @@ properties: vdd33-supply: description: Regulator for 3.3V digital core power. + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -98,7 +101,21 @@ examples: reg = <1>; ps8640_out: endpoint { remote-endpoint = <&panel_in>; - }; + }; + }; + }; + + aux-bus { + panel { + compatible = "boe,nv133fhm-n62"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; }; }; }; diff --git a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml index 3c3e51af15..11fd68a70d 100644 --- a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml +++ b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MIPI DSI host controller maintainers: - - Philippe CORNU + - Philippe CORNU description: | This document defines device tree properties for the Synopsys DesignWare MIPI diff --git a/dts/Bindings/display/bridge/toshiba,tc358767.txt b/dts/Bindings/display/bridge/toshiba,tc358767.txt deleted file mode 100644 index 583c5e9dbe..0000000000 --- a/dts/Bindings/display/bridge/toshiba,tc358767.txt +++ /dev/null @@ -1,54 +0,0 @@ -Toshiba TC358767 eDP bridge bindings - -Required properties: - - compatible: "toshiba,tc358767" - - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins - - clock-names: should be "ref" - - clocks: OF device-tree clock specification for refclk input. The reference - clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. - -Optional properties: - - shutdown-gpios: OF device-tree gpio specification for SD pin - (active high shutdown input) - - reset-gpios: OF device-tree gpio specification for RSTX pin - (active low system reset) - - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1) - - ports: the ports node can contain video interface port nodes to connect - to a DPI/DSI source and to an eDP/DP sink according to [1][2]: - - port@0: DSI input port - - port@1: DPI input port - - port@2: eDP/DP output port - -[1]: Documentation/devicetree/bindings/graph.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - edp-bridge@68 { - compatible = "toshiba,tc358767"; - reg = <0x68>; - shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - clock-names = "ref"; - clocks = <&edp_refclk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - - port@2 { - reg = <2>; - - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/toshiba,tc358767.yaml b/dts/Bindings/display/bridge/toshiba,tc358767.yaml new file mode 100644 index 0000000000..f1541cc052 --- /dev/null +++ b/dts/Bindings/display/bridge/toshiba,tc358767.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC358767 eDP bridge bindings + +maintainers: + - Andrey Gusakov + +description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP + +properties: + compatible: + const: toshiba,tc358767 + + reg: + enum: + - 0x68 + - 0x0f + description: | + i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins + + clock-names: + const: "ref" + + clocks: + maxItems: 1 + description: | + OF device-tree clock specification for refclk input. The reference. + clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. + + shutdown-gpios: + maxItems: 1 + description: | + OF device-tree gpio specification for SD pin(active high shutdown input) + + reset-gpios: + maxItems: 1 + description: | + OF device-tree gpio specification for RSTX pin(active low system reset) + + toshiba,hpd-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 + - 1 + description: TC358767 GPIO pin number to which HPD is connected to (0 or 1) + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: | + DSI input port. The remote endpoint phandle should be a + reference to a valid DSI output endpoint node + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + DPI input port. The remote endpoint phandle should be a + reference to a valid DPI output endpoint node + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: | + eDP/DP output port. The remote endpoint phandle should be a + reference to a valid eDP panel input endpoint node. This port is + optional, treated as DP panel if not defined + + oneOf: + - required: + - port@0 + - required: + - port@1 + + +required: + - compatible + - reg + - clock-names + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + + /* DPI input and eDP output */ + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + edp-bridge@68 { + compatible = "toshiba,tc358767"; + reg = <0x68>; + shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + clock-names = "ref"; + clocks = <&edp_refclk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in_0: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@2 { + reg = <2>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + }; + - | + /* DPI input and DP output */ + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + edp-bridge@68 { + compatible = "toshiba,tc358767"; + reg = <0x68>; + shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + clock-names = "ref"; + clocks = <&edp_refclk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in_1: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/ingenic,ipu.yaml b/dts/Bindings/display/ingenic,ipu.yaml index e679f48a38..3f93def2c5 100644 --- a/dts/Bindings/display/ingenic,ipu.yaml +++ b/dts/Bindings/display/ingenic,ipu.yaml @@ -45,7 +45,7 @@ additionalProperties: false examples: - | - #include + #include ipu@13080000 { compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu"; reg = <0x13080000 0x800>; diff --git a/dts/Bindings/display/ingenic,lcd.yaml b/dts/Bindings/display/ingenic,lcd.yaml index 50d2b0a50e..0049010b37 100644 --- a/dts/Bindings/display/ingenic,lcd.yaml +++ b/dts/Bindings/display/ingenic,lcd.yaml @@ -88,7 +88,7 @@ additionalProperties: false examples: - | - #include + #include lcd-controller@13050000 { compatible = "ingenic,jz4740-lcd"; reg = <0x13050000 0x1000>; @@ -107,7 +107,7 @@ examples: }; - | - #include + #include lcd-controller@13050000 { compatible = "ingenic,jz4725b-lcd"; reg = <0x13050000 0x1000>; diff --git a/dts/Bindings/display/mediatek/mediatek,dsi.txt b/dts/Bindings/display/mediatek/mediatek,dsi.txt index d30428b9fb..36b01458f4 100644 --- a/dts/Bindings/display/mediatek/mediatek,dsi.txt +++ b/dts/Bindings/display/mediatek/mediatek,dsi.txt @@ -19,6 +19,11 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached DSI panel or DSI-to-eDP encoder chip. +Optional properties: +- resets: list of phandle + reset specifier pair, as described in [1]. + +[1] Documentation/devicetree/bindings/reset/reset.txt + MIPI TX Configuration Module ============================ @@ -45,6 +50,7 @@ dsi0: dsi@1401b000 { clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml index 64d8d9e5e4..63e585f487 100644 --- a/dts/Bindings/display/msm/dp-controller.yaml +++ b/dts/Bindings/display/msm/dp-controller.yaml @@ -17,9 +17,16 @@ properties: compatible: enum: - qcom,sc7180-dp + - qcom,sc8180x-dp + - qcom,sc8180x-edp reg: - maxItems: 1 + items: + - description: ahb register block + - description: aux register block + - description: link register block + - description: p0 register block + - description: p1 register block interrupts: maxItems: 1 @@ -95,12 +102,15 @@ examples: - | #include #include - #include #include displayport-controller@ae90000 { compatible = "qcom,sc7180-dp"; - reg = <0xae90000 0x1400>; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>, + <0xae91400 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, diff --git a/dts/Bindings/display/msm/dpu-sc7280.yaml b/dts/Bindings/display/msm/dpu-sc7280.yaml new file mode 100644 index 0000000000..fbeb931a02 --- /dev/null +++ b/dts/Bindings/display/msm/dpu-sc7280.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SC7280 + +maintainers: + - Krishna Manikandan + +description: | + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7280. + +properties: + compatible: + const: qcom,sc7280-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + + interconnects: + items: + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + const: mdp0-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + const: qcom,sc7280-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF5 (EDP) + + required: + - port@0 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7280-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/msm/dsi-phy-14nm.yaml b/dts/Bindings/display/msm/dsi-phy-14nm.yaml index 064df50e21..81dbee4803 100644 --- a/dts/Bindings/display/msm/dsi-phy-14nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-14nm.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,dsi-phy-14nm - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-14nm-8953 reg: items: diff --git a/dts/Bindings/display/msm/gpu.txt b/dts/Bindings/display/msm/gpu.txt deleted file mode 100644 index 090dcb3fc3..0000000000 --- a/dts/Bindings/display/msm/gpu.txt +++ /dev/null @@ -1,157 +0,0 @@ -Qualcomm adreno/snapdragon GPU - -Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or - "amd,imageon-XYZ.W", "amd,imageon" - for example: "qcom,adreno-306.0", "qcom,adreno" - Note that you need to list the less specific "qcom,adreno" (since this - is what the device is matched on), in addition to the more specific - with the chip-id. - If "amd,imageon" is used, there should be no top level msm device. -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the gpu. -- clocks: device clocks (if applicable) - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required by a3xx, a4xx and a5xx - cores: - * "core" - * "iface" - * "mem_iface" - For GMU attached devices the GPU clocks are not used and are not required. The - following devices should not list clocks: - - qcom,adreno-630.2 -- iommus: optional phandle to an adreno iommu instance -- operating-points-v2: optional phandle to the OPP operating points -- interconnects: optional phandle to an interconnect provider. See - ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms - will have two paths; all others will have one path. -- interconnect-names: The names of the interconnect paths that correspond to the - interconnects property. Values must be gfx-mem and ocmem. -- qcom,gmu: For GMU attached devices a phandle to the GMU device that will - control the power for the GPU. Applicable targets: - - qcom,adreno-630.2 -- zap-shader: For a5xx and a6xx devices this node contains a memory-region that - points to reserved memory to store the zap shader that can be used to help - bring the GPU out of secure mode. -- firmware-name: optional property of the 'zap-shader' node, listing the - relative path of the device specific zap firmware. -- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and - a4xx Snapdragon SoCs. See - Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. - -Optional properties: -- #cooling-cells: The value must be 2. For details, please refer - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. - -Example 3xx/4xx: - -/ { - ... - - gpu: adreno@fdb00000 { - compatible = "qcom,adreno-330.2", - "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = "core", - "iface", - "mem_iface"; - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - sram = <&gpu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 0>; - #cooling-cells = <2>; - }; - - gpu_sram: ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gpu_sram: gpu-sram@0 { - reg = <0x0 0x100000>; - ranges = <0 0 0xfec00000 0x100000>; - }; - }; -}; - -Example a6xx (with GMU): - -/ { - ... - - gpu@5000000 { - compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0x5000000 0x40000>, <0x509e000 0x10>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; - - #cooling-cells = <2>; - - /* - * Look ma, no clocks! The GPU clocks and power are - * controlled entirely by the GMU - */ - - interrupts = ; - - iommus = <&adreno_smmu 0>; - - operating-points-v2 = <&gpu_opp_table>; - - interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; - interconnect-names = "gfx-mem"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-430000000 { - opp-hz = /bits/ 64 <430000000>; - opp-level = ; - opp-peak-kBps = <5412000>; - }; - - opp-355000000 { - opp-hz = /bits/ 64 <355000000>; - opp-level = ; - opp-peak-kBps = <3072000>; - }; - - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-level = ; - opp-peak-kBps = <3072000>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - opp-level = ; - opp-peak-kBps = <1804000>; - }; - }; - - qcom,gmu = <&gmu>; - - zap-shader { - memory-region = <&zap_shader_region>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" - }; - }; -}; diff --git a/dts/Bindings/display/msm/gpu.yaml b/dts/Bindings/display/msm/gpu.yaml new file mode 100644 index 0000000000..99a1ba3ada --- /dev/null +++ b/dts/Bindings/display/msm/gpu.yaml @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Devicetree bindings for the Adreno or Snapdragon GPUs + +maintainers: + - Rob Clark + +properties: + compatible: + oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the gpu-id and patch level. + items: + - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' + - const: qcom,adreno + - description: | + The driver is parsing the compat string for Imageon to + figure out the gpu-id and patch level. + items: + - pattern: '^amd,imageon-200\.[0-1]$' + - const: amd,imageon + + clocks: true + + clock-names: true + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + interconnects: + minItems: 1 + maxItems: 2 + + interconnect-names: + minItems: 1 + items: + - const: gfx-mem + - const: ocmem + + iommus: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 4 + description: | + phandles to one or more reserved on-chip SRAM regions. + phandle to the On Chip Memory (OCMEM) that's present on some a3xx and + a4xx Snapdragon SoCs. See + Documentation/devicetree/bindings/sram/qcom,ocmem.yaml + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 1 + + zap-shader: + type: object + description: | + For a5xx and a6xx devices this node contains a memory-region that + points to reserved memory to store the zap shader that can be used to + help bring the GPU out of secure mode. + properties: + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + + firmware-name: + description: | + Default name of the firmware to load to the remote processor. + + "#cooling-cells": + const: 2 + + nvmem-cell-names: + maxItems: 1 + + nvmem-cells: + description: efuse registers + maxItems: 1 + + qcom,gmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + For GMU attached devices a phandle to the GMU device that will + control the power for the GPU. + + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + + then: + properties: + clocks: + minItems: 2 + maxItems: 7 + + clock-names: + items: + anyOf: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + minItems: 2 + maxItems: 7 + + required: + - clocks + - clock-names + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Since Adreno 6xx series clocks should be defined in GMU + properties: + clocks: false + clock-names: false + +examples: + - | + + // Example a3xx/4xx: + + #include + #include + #include + #include + + gpu: gpu@fdb00000 { + compatible = "qcom,adreno-330.2", "qcom,adreno"; + + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + + clock-names = "core", "iface", "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + sram = <&gpu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 0>; + #cooling-cells = <2>; + }; + + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfec00000 0x100000>; + + gpu_sram: gpu-sram@0 { + reg = <0x0 0x100000>; + }; + }; + - | + + // Example a6xx (with GMU): + + #include + #include + #include + #include + #include + #include + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; + }; + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + #cooling-cells = <2>; + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-peak-kBps = <1804000>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; + }; + }; diff --git a/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml index b87a2e28c8..a2384bd74c 100644 --- a/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/dts/Bindings/display/panel/boe,tv101wum-nl6.yaml @@ -26,6 +26,10 @@ properties: - auo,b101uan08.3 # BOE TV105WUM-NW0 10.5" WUXGA TFT LCD panel - boe,tv105wum-nw0 + # BOE TV110C9M-LL3 10.95" WUXGA TFT LCD panel + - boe,tv110c9m-ll3 + # INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel + - innolux,hj110iz-01a reg: description: the virtual channel number of a DSI peripheral @@ -36,6 +40,9 @@ properties: pp1800-supply: description: core voltage supply + pp3300-supply: + description: core voltage supply + avdd-supply: description: phandle of the regulator that provides positive voltage diff --git a/dts/Bindings/display/panel/orisetech,otm8009a.yaml b/dts/Bindings/display/panel/orisetech,otm8009a.yaml index 4b6dda6dbc..17cbd0ad32 100644 --- a/dts/Bindings/display/panel/orisetech,otm8009a.yaml +++ b/dts/Bindings/display/panel/orisetech,otm8009a.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) maintainers: - - Philippe CORNU + - Philippe CORNU description: | The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using diff --git a/dts/Bindings/display/panel/panel-edp.yaml b/dts/Bindings/display/panel/panel-edp.yaml new file mode 100644 index 0000000000..bb0cf6827e --- /dev/null +++ b/dts/Bindings/display/panel/panel-edp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-edp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Probeable (via DP AUX / EDID) eDP Panels with simple poweron sequences + +maintainers: + - Douglas Anderson + +description: | + This binding file can be used to indicate that an eDP panel is connected + to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without + actually specifying exactly what panel is connected. This is useful for + the case that more than one different panel could be connected to the + board, either for second-sourcing purposes or to support multiple SKUs + with different LCDs that hook up to a common board. + + As per above, a requirement for using this binding is that the panel is + represented under the DP AUX bus. This means that we can use any + information provided by the DP AUX bus (including the EDID) to identify + the panel. We can use this to identify display size, resolution, and + timings among other things. + + One piece of information about eDP panels that is typically _not_ + provided anywhere on the DP AUX bus is the power sequencing timings. + This is the reason why, historically, we've always had to explicitly + list eDP panels. We solve that here with two tricks. The "worst case" + power on timings for any panels expected to be connected to a board are + specified in these bindings. Once we've powered on, it's expected that + the operating system will lookup the panel in a table (based on EDID + information) to figure out other power sequencing timings. + + eDP panels in general can have somewhat arbitrary power sequencing + requirements. However, even though it's arbitrary in general, the + vast majority of panel datasheets have a power sequence diagram that + looks the exactly the same as every other panel. Each panel datasheet + cares about different timings in this diagram but the fact that the + diagram is so similar means we can come up with a single driver to + handle it. + + These diagrams all look roughly like this, sometimes labeled with + slightly different numbers / lines but all pretty much the same + sequence. This is because much of this diagram comes straight from + the eDP Standard. + + __________________________________________________ + Vdd ___/: :\____ / + _/ : : \_____/ + ::: :<--T10-->::: + : +-----------------------+---------+---------+ + eDP -----------+ Black video | Src vid | Blk vid + + Display : +-----------------------+---------+---------+ + : _______________________:_________:_________: + HPD :| : : | + ___________| : : |_____________ + : : : : + Sink +-----------------------:---------:---------+ + AUX CH -----------+ AUX Ch operational : : +------------- + +-----------------------:---------:---------+ + : : : : + :: :: : : + Src main +------+------+--------------+---------+ + lnk data----------------+LnkTrn| Idle |Valid vid data| Idle/off+------------- + +------+------+--------------+---------+ + : :<-T6->:<-T8->: : + :__:: + LED_EN | | + _____________________________________| |____________________________ + : : + __________:__:_ + PWM | : : | + __________________________| : : |__________________________ + : : : : + _____________:__________:__:_:______ + Bklight ____/: : : : : :\____ + power _______/ :<---T13---->: : : :: \______________ + (Vbl) ::<---------T14--------->: :<-T15->:: + + The above looks fairly complex but, as per above, each panel only cares + about a subset of those timings. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: edp-panel + + hpd-reliable-delay-ms: + description: + A fixed amount of time that must be waited after powering on the + panel's power-supply before the HPD signal is a reliable way to know + when the AUX channel is ready. This is useful for panels that glitch + the HPD at the start of power-on. This value is not needed if HPD is + always reliable for all panels that might be connected. + + hpd-absent-delay-ms: + description: + The panel specifies that HPD will be asserted this many milliseconds + from power on (timing T3 in the diagram above). If we have no way to + measure HPD then a fixed delay of this many milliseconds can be used. + This can also be used as a timeout when waiting for HPD. Does not + include the hpd-reliable-delay, so if hpd-reliable-delay was 80 ms + and hpd-absent-delay was 200 ms then we'd do a fixed 80 ms delay and + then we know HPD would assert in the next 120 ms. This value is not + needed if HPD hooked up, either through a GPIO in the panel node or + hooked up directly to the eDP controller. + + backlight: true + enable-gpios: true + port: true + power-supply: true + no-hpd: true + hpd-gpios: true + +additionalProperties: false + +required: + - compatible + - power-supply + +examples: + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + + interrupt-parent = <&tlmm>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&src_pp1800_s4a>; + vccio-supply = <&src_pp1800_s4a>; + vcca-supply = <&src_pp1200_l2a>; + vcc-supply = <&src_pp1200_l2a>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + clock-names = "refclk"; + + no-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + hpd-reliable-delay-ms = <15>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml index 335776c454..f3c9395d23 100644 --- a/dts/Bindings/display/panel/panel-simple.yaml +++ b/dts/Bindings/display/panel/panel-simple.yaml @@ -166,6 +166,8 @@ properties: - innolux,at070tn92 # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel - innolux,g070y2-l01 + # Innolux G070Y2-T02 7" WVGA (800x480) TFT LCD TTL panel + - innolux,g070y2-t02 # Innolux Corporation 10.1" G101ICE-L01 WXGA (1280x800) LVDS panel - innolux,g101ice-l01 # Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel @@ -309,6 +311,8 @@ properties: - urt,umsh-8596md-11t - urt,umsh-8596md-19t - urt,umsh-8596md-20t + # Vivax TPC-9150 tablet 9.0" WSVGA TFT LCD panel + - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel @@ -317,6 +321,7 @@ properties: - yes-optoelectronics,ytc700tlag-05-201c backlight: true + ddc-i2c-bus: true enable-gpios: true port: true power-supply: true diff --git a/dts/Bindings/display/panel/raydium,rm68200.yaml b/dts/Bindings/display/panel/raydium,rm68200.yaml index 39477793d2..e8ce231563 100644 --- a/dts/Bindings/display/panel/raydium,rm68200.yaml +++ b/dts/Bindings/display/panel/raydium,rm68200.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel maintainers: - - Philippe CORNU + - Philippe CORNU description: | The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD diff --git a/dts/Bindings/display/panel/samsung,s6d27a1.yaml b/dts/Bindings/display/panel/samsung,s6d27a1.yaml new file mode 100644 index 0000000000..26e3c820a2 --- /dev/null +++ b/dts/Bindings/display/panel/samsung,s6d27a1.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6d27a1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S6D27A1 display panel + +description: The S6D27A1 is a 480x800 DPI display panel from Samsung Mobile + Displays (SMD). The panel must obey the rules for a SPI slave device + as specified in spi/spi-controller.yaml + +maintainers: + - Markuss Broks + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,s6d27a1 + + reg: true + + interrupts: + description: provides an optional ESD (electrostatic discharge) + interrupt that signals abnormalities in the display hardware. + This can also be raised for other reasons like erroneous + configuration. + maxItems: 1 + + reset-gpios: true + + vci-supply: + description: regulator that supplies the VCI analog voltage + usually around 3.0 V + + vccio-supply: + description: regulator that supplies the VCCIO voltage usually + around 1.8 V + + backlight: true + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 1200000 + + port: true + +required: + - compatible + - reg + - vci-supply + - vccio-supply + - spi-cpha + - spi-cpol + - port + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + compatible = "spi-gpio"; + sck-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + spi-cpha; + spi-cpol; + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&lcd_1v8_reg>; + reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/sharp,ls060t1sx01.yaml b/dts/Bindings/display/panel/sharp,ls060t1sx01.yaml new file mode 100644 index 0000000000..271c097cc9 --- /dev/null +++ b/dts/Bindings/display/panel/sharp,ls060t1sx01.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ls060t1sx01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp Microelectronics 6.0" FullHD TFT LCD panel + +maintainers: + - Dmitry Baryskov + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ls060t1sx01 + + reg: true + backlight: true + reset-gpios: true + port: true + + avdd-supply: + description: handle of the regulator that provides the positive supply voltage + avee-supply: + description: handle of the regulator that provides the negative supply voltage + vddi-supply: + description: handle of the regulator that provides the I/O supply voltage + vddh-supply: + description: handle of the regulator that provides the analog supply voltage + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,ls060t1sx01"; + reg = <0>; + avdd-supply = <&pm8941_l22>; + backlight = <&backlight>; + reset-gpios = <&pm8916_gpios 25 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/dts/Bindings/display/renesas,du.yaml b/dts/Bindings/display/renesas,du.yaml index e3ca5389c1..13efea5745 100644 --- a/dts/Bindings/display/renesas,du.yaml +++ b/dts/Bindings/display/renesas,du.yaml @@ -39,6 +39,7 @@ properties: - renesas,du-r8a77980 # for R-Car V3H compatible DU - renesas,du-r8a77990 # for R-Car E3 compatible DU - renesas,du-r8a77995 # for R-Car D3 compatible DU + - renesas,du-r8a779a0 # for R-Car V3U compatible DU reg: maxItems: 1 @@ -773,6 +774,56 @@ allOf: - reset-names - renesas,vsps + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a779a0 + then: + properties: + clocks: + items: + - description: Functional clock + + clock-names: + maxItems: 1 + items: + - const: du.0 + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DSI 0 + port@1: + description: DSI 1 + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + renesas,vsps: + minItems: 2 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + additionalProperties: false examples: diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml index ed310bbe3a..ce1ef93cce 100644 --- a/dts/Bindings/display/st,stm32-dsi.yaml +++ b/dts/Bindings/display/st,stm32-dsi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DSI host controller maintainers: - - Philippe Cornu - - Yannick Fertre + - Philippe Cornu + - Yannick Fertre description: The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. diff --git a/dts/Bindings/display/st,stm32-ltdc.yaml b/dts/Bindings/display/st,stm32-ltdc.yaml index 4ae3d75492..01e2da2379 100644 --- a/dts/Bindings/display/st,stm32-ltdc.yaml +++ b/dts/Bindings/display/st,stm32-ltdc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 lcd-tft display controller maintainers: - - Philippe Cornu - - Yannick Fertre + - Philippe Cornu + - Yannick Fertre properties: compatible: diff --git a/dts/Bindings/display/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt index 3e64075ac7..3b3d0bbfcf 100644 --- a/dts/Bindings/display/tilcdc/tilcdc.txt +++ b/dts/Bindings/display/tilcdc/tilcdc.txt @@ -60,7 +60,7 @@ Example: blue-and-red-wiring = "crossed"; port { - lcdc_0: endpoint@0 { + lcdc_0: endpoint { remote-endpoint = <&hdmi_0>; }; }; @@ -75,7 +75,7 @@ Example: pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; port { - hdmi_0: endpoint@0 { + hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml index d88bd93f4b..10ec78ca1c 100644 --- a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml +++ b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml @@ -160,8 +160,8 @@ examples: <&xlnx_dpdma 2>, <&xlnx_dpdma 3>; - phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>, - <&psgtr 0 PHY_TYPE_DP 1 3 27000000>; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; phy-names = "dp-phy0", "dp-phy1"; }; diff --git a/dts/Bindings/display/xylon,logicvc-display.yaml b/dts/Bindings/display/xylon,logicvc-display.yaml new file mode 100644 index 0000000000..fc02c5d50c --- /dev/null +++ b/dts/Bindings/display/xylon,logicvc-display.yaml @@ -0,0 +1,301 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Bootlin +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xylon LogiCVC display controller + +maintainers: + - Paul Kocialkowski + +description: | + The Xylon LogiCVC is a display controller that supports multiple layers. + It is usually implemented as programmable logic and was optimized for use + with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. + + Because the controller is intended for use in a FPGA, most of the + configuration of the controller takes place at logic configuration bitstream + synthesis time. As a result, many of the device-tree bindings are meant to + reflect the synthesis configuration and must not be configured differently. + Matching synthesis parameters are provided when applicable. + + Layers are declared in the "layers" sub-node and have dedicated configuration. + In version 3 of the controller, each layer has fixed memory offset and address + starting from the video memory base address for its framebuffer. In version 4, + framebuffers are configured with a direct memory address instead. + +properties: + compatible: + enum: + - xylon,logicvc-3.02.a-display + - xylon,logicvc-4.01.a-display + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + # vclk is required and must be provided as first item. + - const: vclk + # Other clocks are optional and can be provided in any order. + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + xylon,display-interface: + enum: + # Parallel RGB interface (C_DISPLAY_INTERFACE == 0) + - parallel-rgb + # ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1) + - bt656 + # 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2) + - lvds-4bits + # 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4) + - lvds-3bits + # DVI interface (C_DISPLAY_INTERFACE == 5) + - dvi + description: Display output interface (C_DISPLAY_INTERFACE). + + xylon,display-colorspace: + enum: + # RGB colorspace (C_DISPLAY_COLOR_SPACE == 0) + - rgb + # YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1) + - yuv422 + # YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2) + - yuv444 + description: Display output colorspace (C_DISPLAY_COLOR_SPACE). + + xylon,display-depth: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Display output depth (C_PIXEL_DATA_WIDTH). + + xylon,row-stride: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE). + + xylon,dithering: + $ref: "/schemas/types.yaml#/definitions/flag" + description: Dithering module is enabled (C_XCOLOR) + + xylon,background-layer: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + The last layer is used to display a black background (C_USE_BACKGROUND). + The layer must still be registered. + + xylon,layers-configurable: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + Configuration of layers' size, position and offset is enabled + (C_USE_SIZE_POSITION). + + layers: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^layer@[0-9]+$": + type: object + + properties: + reg: + maxItems: 1 + + xylon,layer-depth: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Layer depth (C_LAYER_X_DATA_WIDTH). + + xylon,layer-colorspace: + enum: + # RGB colorspace (C_LAYER_X_TYPE == 0) + - rgb + # YUV packed colorspace (C_LAYER_X_TYPE == 0) + - yuv + description: Layer colorspace (C_LAYER_X_TYPE). + + xylon,layer-alpha-mode: + enum: + # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0) + - layer + # Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1) + - pixel + description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE). + + xylon,layer-base-offset: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Offset in number of lines (C_LAYER_X_OFFSET) starting from the + video RAM base (C_VMEM_BASEADDR), only for version 3. + + xylon,layer-buffer-offset: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Offset in number of lines (C_BUFFER_*_OFFSET) starting from the + layer base offset for the second buffer used in double-buffering. + + xylon,layer-primary: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + Layer should be registered as a primary plane (exactly one is + required). + + additionalProperties: false + + required: + - reg + - xylon,layer-depth + - xylon,layer-colorspace + - xylon,layer-alpha-mode + + required: + - "#address-cells" + - "#size-cells" + - layer@0 + + additionalProperties: false + + description: | + The description of the display controller layers, containing layer + sub-nodes that each describe a registered layer. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: | + Video output port, typically connected to a panel or bridge. + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - xylon,display-interface + - xylon,display-colorspace + - xylon,display-depth + - xylon,row-stride + - layers + - port + +examples: + - | + #include + + logicvc: logicvc@43c00000 { + compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd"; + reg = <0x43c00000 0x6000>; + + #address-cells = <1>; + #size-cells = <1>; + + logicvc_display: display@0 { + compatible = "xylon,logicvc-3.02.a-display"; + reg = <0x0 0x6000>; + + memory-region = <&logicvc_cma>; + + clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>; + clock-names = "vclk", "lvdsclk"; + + interrupt-parent = <&intc>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + + xylon,display-interface = "lvds-4bits"; + xylon,display-colorspace = "rgb"; + xylon,display-depth = <16>; + xylon,row-stride = <1024>; + + xylon,layers-configurable; + + layers { + #address-cells = <1>; + #size-cells = <0>; + + layer@0 { + reg = <0>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <0>; + xylon,layer-buffer-offset = <480>; + xylon,layer-primary; + }; + + layer@1 { + reg = <1>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <2400>; + xylon,layer-buffer-offset = <480>; + }; + + layer@2 { + reg = <2>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <960>; + xylon,layer-buffer-offset = <480>; + }; + + layer@3 { + reg = <3>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <480>; + xylon,layer-buffer-offset = <480>; + }; + + layer@4 { + reg = <4>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <8192>; + xylon,layer-buffer-offset = <480>; + }; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + logicvc_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; diff --git a/dts/Bindings/dma/ingenic,dma.yaml b/dts/Bindings/dma/ingenic,dma.yaml index ac4d59494f..dc059d6fd0 100644 --- a/dts/Bindings/dma/ingenic,dma.yaml +++ b/dts/Bindings/dma/ingenic,dma.yaml @@ -68,7 +68,7 @@ unevaluatedProperties: false examples: - | - #include + #include dma: dma-controller@13420000 { compatible = "ingenic,jz4780-dma"; reg = <0x13420000 0x400>, <0x13421000 0x40>; diff --git a/dts/Bindings/dma/qcom_bam_dma.txt b/dts/Bindings/dma/qcom_bam_dma.txt index cf5b9e4443..6e9a5497b3 100644 --- a/dts/Bindings/dma/qcom_bam_dma.txt +++ b/dts/Bindings/dma/qcom_bam_dma.txt @@ -15,6 +15,8 @@ Required properties: the secure world. - qcom,controlled-remotely : optional, indicates that the bam is controlled by remote proccessor i.e. execution environment. +- qcom,powered-remotely : optional, indicates that the bam is powered up by + a remote processor but must be initialized by the local processor. - num-channels : optional, indicates supported number of DMA channels in a remotely controlled bam. - qcom,num-ees : optional, indicates supported number of Execution Environments diff --git a/dts/Bindings/dma/st,stm32-dma.yaml b/dts/Bindings/dma/st,stm32-dma.yaml index 4bf676fd25..55faab6a46 100644 --- a/dts/Bindings/dma/st,stm32-dma.yaml +++ b/dts/Bindings/dma/st,stm32-dma.yaml @@ -50,7 +50,7 @@ description: | maintainers: - - Amelie Delaunay + - Amelie Delaunay allOf: - $ref: "dma-controller.yaml#" diff --git a/dts/Bindings/dma/st,stm32-dmamux.yaml b/dts/Bindings/dma/st,stm32-dmamux.yaml index c8d2b51d84..f751796531 100644 --- a/dts/Bindings/dma/st,stm32-dmamux.yaml +++ b/dts/Bindings/dma/st,stm32-dmamux.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings maintainers: - - Amelie Delaunay + - Amelie Delaunay allOf: - $ref: "dma-router.yaml#" diff --git a/dts/Bindings/dma/st,stm32-mdma.yaml b/dts/Bindings/dma/st,stm32-mdma.yaml index c30be840be..87b4afd2cf 100644 --- a/dts/Bindings/dma/st,stm32-mdma.yaml +++ b/dts/Bindings/dma/st,stm32-mdma.yaml @@ -50,7 +50,7 @@ description: | if no HW ack signal is used by the MDMA client maintainers: - - Amelie Delaunay + - Amelie Delaunay allOf: - $ref: "dma-controller.yaml#" diff --git a/dts/Bindings/dsp/fsl,dsp.yaml b/dts/Bindings/dsp/fsl,dsp.yaml index 7afc9f2be1..e66ef2da78 100644 --- a/dts/Bindings/dsp/fsl,dsp.yaml +++ b/dts/Bindings/dsp/fsl,dsp.yaml @@ -8,6 +8,7 @@ title: NXP i.MX8 DSP core maintainers: - Daniel Baluta + - Shengjiu Wang description: | Some boards from i.MX8 family contain a DSP core used for @@ -19,6 +20,10 @@ properties: - fsl,imx8qxp-dsp - fsl,imx8qm-dsp - fsl,imx8mp-dsp + - fsl,imx8qxp-hifi4 + - fsl,imx8qm-hifi4 + - fsl,imx8mp-hifi4 + - fsl,imx8ulp-hifi4 reg: maxItems: 1 @@ -28,37 +33,53 @@ properties: - description: ipg clock - description: ocram clock - description: core clock + - description: debug interface clock + - description: message unit clock + minItems: 3 clock-names: items: - const: ipg - const: ocram - const: core + - const: debug + - const: mu + minItems: 3 power-domains: description: List of phandle and PM domain specifier as documented in Documentation/devicetree/bindings/power/power_domain.txt + minItems: 1 maxItems: 4 mboxes: description: List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB + or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB (see mailbox/fsl,mu.txt) + minItems: 3 maxItems: 4 mbox-names: - items: - - const: txdb0 - - const: txdb1 - - const: rxdb0 - - const: rxdb1 + minItems: 3 + maxItems: 4 memory-region: description: phandle to a node describing reserved memory (System RAM memory) used by DSP (see bindings/reserved-memory/reserved-memory.txt) - maxItems: 1 + minItems: 1 + maxItems: 4 + + firmware-name: + description: | + Default name of the firmware to load to the remote processor. + + fsl,dsp-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to syscon block which provide access for processor enablement required: - compatible @@ -70,6 +91,58 @@ required: - mbox-names - memory-region +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-dsp + - fsl,imx8qm-dsp + - fsl,imx8qxp-hifi4 + - fsl,imx8qm-hifi4 + then: + properties: + power-domains: + minItems: 4 + else: + properties: + power-domains: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-hifi4 + - fsl,imx8qm-hifi4 + - fsl,imx8mp-hifi4 + - fsl,imx8ulp-hifi4 + then: + properties: + memory-region: + minItems: 4 + mboxes: + maxItems: 3 + mbox-names: + items: + - const: tx + - const: rx + - const: rxdb + else: + properties: + memory-region: + maxItems: 1 + mboxes: + minItems: 4 + mbox-names: + items: + - const: txdb0 + - const: txdb1 + - const: rxdb0 + - const: rxdb1 + additionalProperties: false examples: @@ -91,3 +164,41 @@ examples: mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; memory-region = <&dsp_reserved>; }; + - | + #include + dsp_reserved: dsp@92400000 { + reg = <0x92400000 0x1000000>; + no-map; + }; + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0x942f0000 0x8000>; + no-map; + }; + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0x942f8000 0x8000>; + no-map; + }; + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0x94300000 0x100000>; + no-map; + }; + + dsp: dsp@3b6e8000 { + compatible = "fsl,imx8mp-hifi4"; + reg = <0x3b6e8000 0x88000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; + clock-names = "ipg", "ocram", "core", "debug"; + firmware-name = "imx/dsp/hifi4.bin"; + power-domains = <&audiomix_pd>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu2 0 0>, + <&mu2 1 0>, + <&mu2 3 0>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + fsl,dsp-ctrl = <&audio_blk_ctrl>; + }; diff --git a/dts/Bindings/eeprom/at24.yaml b/dts/Bindings/eeprom/at24.yaml index 914a423ec4..4c5396a974 100644 --- a/dts/Bindings/eeprom/at24.yaml +++ b/dts/Bindings/eeprom/at24.yaml @@ -97,6 +97,12 @@ properties: - items: - const: nxp,se97b - const: atmel,24c02 + - items: + - const: onnn,cat24c04 + - const: atmel,24c04 + - items: + - const: onnn,cat24c05 + - const: atmel,24c04 - items: - const: renesas,r1ex24002 - const: atmel,24c02 diff --git a/dts/Bindings/example-schema.yaml b/dts/Bindings/example-schema.yaml index ff6ec65145..c078796ae1 100644 --- a/dts/Bindings/example-schema.yaml +++ b/dts/Bindings/example-schema.yaml @@ -119,7 +119,7 @@ properties: # valid for this binding. clock-frequency: - # The type is set in the core schema. Per device schema only need to set + # The type is set in the core schema. Per-device schema only need to set # constraints on the possible values. minimum: 100 maximum: 400000 @@ -133,24 +133,24 @@ properties: # *-supply is always a single phandle, so nothing more to define. foo-supply: true - # Vendor specific properties + # Vendor-specific properties # - # Vendor specific properties have slightly different schema requirements than + # Vendor-specific properties have slightly different schema requirements than # common properties. They must have at least a type definition and # 'description'. vendor,int-property: - description: Vendor specific properties must have a description + description: Vendor-specific properties must have a description $ref: /schemas/types.yaml#/definitions/uint32 enum: [2, 4, 6, 8, 10] vendor,bool-property: - description: Vendor specific properties must have a description. Boolean + description: Vendor-specific properties must have a description. Boolean properties are one case where the json-schema 'type' keyword can be used directly. type: boolean vendor,string-array-property: - description: Vendor specific properties should reference a type in the + description: Vendor-specific properties should reference a type in the core schema. $ref: /schemas/types.yaml#/definitions/string-array items: @@ -158,7 +158,7 @@ properties: - enum: [baz, boo] vendor,property-in-standard-units-microvolt: - description: Vendor specific properties having a standard unit suffix + description: Vendor-specific properties having a standard unit suffix don't need a type. enum: [ 100, 200, 300 ] diff --git a/dts/Bindings/extcon/extcon-usbc-tusb320.yaml b/dts/Bindings/extcon/extcon-usbc-tusb320.yaml index 9875b4d5c3..71a9f2e5d0 100644 --- a/dts/Bindings/extcon/extcon-usbc-tusb320.yaml +++ b/dts/Bindings/extcon/extcon-usbc-tusb320.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: ti,tusb320 + enum: + - ti,tusb320 + - ti,tusb320l reg: maxItems: 1 diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt index a7333ad938..d7e3cda892 100644 --- a/dts/Bindings/firmware/qcom,scm.txt +++ b/dts/Bindings/firmware/qcom,scm.txt @@ -13,8 +13,10 @@ Required properties: * "qcom,scm-ipq806x" * "qcom,scm-ipq8074" * "qcom,scm-mdm9607" + * "qcom,scm-msm8226" * "qcom,scm-msm8660" * "qcom,scm-msm8916" + * "qcom,scm-msm8953" * "qcom,scm-msm8960" * "qcom,scm-msm8974" * "qcom,scm-msm8994" @@ -33,7 +35,7 @@ Required properties: * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and "qcom,scm-msm8960" * core, iface and bus clocks required for "qcom,scm-apq8084", - "qcom,scm-msm8916" and "qcom,scm-msm8974" + "qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974" - clock-names: Must contain "core" for the core clock, "iface" for the interface clock and "bus" for the bus clock per the requirements of the compatible. - qcom,dload-mode: phandle to the TCSR hardware block and offset of the diff --git a/dts/Bindings/gnss/u-blox,neo-6m.yaml b/dts/Bindings/gnss/u-blox,neo-6m.yaml new file mode 100644 index 0000000000..396101a223 --- /dev/null +++ b/dts/Bindings/gnss/u-blox,neo-6m.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: U-blox GNSS Receiver Device Tree Bindings + +maintainers: + - Johan Hovold + +description: > + The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. + +properties: + compatible: + enum: + - u-blox,neo-6m + - u-blox,neo-8 + - u-blox,neo-m8 + + reg: + description: > + The DDC Slave Address, SPI chip select address, the number of the USB hub + port or the USB host-controller port to which this device is attached, + depending on the bus used. Required for the DDC, SPI or USB busses. + + vcc-supply: + description: > + Main voltage regulator + + timepulse-gpios: + maxItems: 1 + description: > + Time pulse GPIO + + u-blox,extint-gpios: + maxItems: 1 + description: > + GPIO connected to the "external interrupt" input pin + + v-bckp-supply: + description: > + Backup voltage regulator + + current-speed: true + +required: + - compatible + - vcc-supply + +additionalProperties: false + +examples: + - | + serial { + gnss { + compatible = "u-blox,neo-8"; + v-bckp-supply = <&gnss_v_bckp_reg>; + vcc-supply = <&gnss_vcc_reg>; + }; + }; diff --git a/dts/Bindings/gnss/u-blox.txt b/dts/Bindings/gnss/u-blox.txt deleted file mode 100644 index 7cdefd058f..0000000000 --- a/dts/Bindings/gnss/u-blox.txt +++ /dev/null @@ -1,45 +0,0 @@ -u-blox GNSS Receiver DT binding - -The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. - -Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic -properties. - -Required properties: - -- compatible : Must be one of - - "u-blox,neo-6m" - "u-blox,neo-8" - "u-blox,neo-m8" - -- vcc-supply : Main voltage regulator - -Required properties (DDC): -- reg : DDC (I2C) slave address - -Required properties (SPI): -- reg : SPI chip select address - -Required properties (USB): -- reg : Number of the USB hub port or the USB host-controller port - to which this device is attached - -Optional properties: - -- timepulse-gpios : Time pulse GPIO -- u-blox,extint-gpios : GPIO connected to the "external interrupt" input pin -- v-bckp-supply : Backup voltage regulator - -Example: - -serial@1234 { - compatible = "ns16550a"; - - gnss { - compatible = "u-blox,neo-8"; - - v-bckp-supply = <&gnss_v_bckp_reg>; - vcc-supply = <&gnss_vcc_reg>; - }; -}; diff --git a/dts/Bindings/gpio/gpio-axp209.txt b/dts/Bindings/gpio/gpio-axp209.txt deleted file mode 100644 index fc42b2caa0..0000000000 --- a/dts/Bindings/gpio/gpio-axp209.txt +++ /dev/null @@ -1,75 +0,0 @@ -AXP209 GPIO & pinctrl controller - -This driver follows the usual GPIO bindings found in -Documentation/devicetree/bindings/gpio/gpio.txt - -This driver follows the usual pinctrl bindings found in -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -This driver employs the per-pin muxing pattern. - -Required properties: -- compatible: Should be one of: - - "x-powers,axp209-gpio" - - "x-powers,axp813-gpio" -- #gpio-cells: Should be two. The first cell is the pin number and the - second is the GPIO flags. -- gpio-controller: Marks the device node as a GPIO controller. - -This node must be a subnode of the axp20x PMIC, documented in -Documentation/devicetree/bindings/mfd/axp20x.txt - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - axp_gpio: gpio { - compatible = "x-powers,axp209-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -The GPIOs can be muxed to other functions and therefore, must be a subnode of -axp_gpio. - -Example: - -&axp_gpio { - gpio0_adc: gpio0-adc { - pins = "GPIO0"; - function = "adc"; - }; -}; - -&example_node { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_adc>; -}; - -GPIOs and their functions -------------------------- - -Each GPIO is independent from the other (i.e. GPIO0 in gpio_in function does -not force GPIO1 and GPIO2 to be in gpio_in function as well). - -axp209 ------- -GPIO | Functions ------------------------- -GPIO0 | gpio_in, gpio_out, ldo, adc -GPIO1 | gpio_in, gpio_out, ldo, adc -GPIO2 | gpio_in, gpio_out - -axp813 ------- -GPIO | Functions ------------------------- -GPIO0 | gpio_in, gpio_out, ldo, adc -GPIO1 | gpio_in, gpio_out, ldo diff --git a/dts/Bindings/gpio/gpio-xlp.txt b/dts/Bindings/gpio/gpio-xlp.txt deleted file mode 100644 index 47fc64922f..0000000000 --- a/dts/Bindings/gpio/gpio-xlp.txt +++ /dev/null @@ -1,49 +0,0 @@ -Netlogic XLP Family GPIO -======================== - -This GPIO driver is used for following Netlogic XLP SoCs: - XLP832, XLP316, XLP208, XLP980, XLP532 -This GPIO driver is also compatible with GPIO controller found on -Broadcom Vulcan ARM64. - -Required properties: -------------------- - -- compatible: Should be one of the following: - - "netlogic,xlp832-gpio": For Netlogic XLP832 - - "netlogic,xlp316-gpio": For Netlogic XLP316 - - "netlogic,xlp208-gpio": For Netlogic XLP208 - - "netlogic,xlp980-gpio": For Netlogic XLP980 - - "netlogic,xlp532-gpio": For Netlogic XLP532 - - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64 -- reg: Physical base address and length of the controller's registers. -- #gpio-cells: Should be two. The first cell is the pin number and the second - cell is used to specify optional parameters (currently unused). -- gpio-controller: Marks the device node as a GPIO controller. -- nr-gpios: Number of GPIO pins supported by the controller. -- interrupt-cells: Should be two. The first cell is the GPIO Number. The - second cell is used to specify flags. The following subset of flags is - supported: - - trigger type: - 1 = low to high edge triggered. - 2 = high to low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- interrupts: Interrupt number for this device. -- interrupt-controller: Identifies the node as an interrupt controller. - -Example: - - gpio: xlp_gpio@34000 { - compatible = "netlogic,xlp316-gpio"; - reg = <0 0x34100 0x1000 - 0 0x35100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - nr-gpios = <57>; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; diff --git a/dts/Bindings/gpio/rockchip,gpio-bank.yaml b/dts/Bindings/gpio/rockchip,gpio-bank.yaml index 0d62c28fb5..d4e42c2b99 100644 --- a/dts/Bindings/gpio/rockchip,gpio-bank.yaml +++ b/dts/Bindings/gpio/rockchip,gpio-bank.yaml @@ -29,6 +29,8 @@ properties: gpio-controller: true + gpio-line-names: true + "#gpio-cells": const: 2 diff --git a/dts/Bindings/gpio/x-powers,axp209-gpio.yaml b/dts/Bindings/gpio/x-powers,axp209-gpio.yaml new file mode 100644 index 0000000000..0f628b088c --- /dev/null +++ b/dts/Bindings/gpio/x-powers,axp209-gpio.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: X-Powers AXP209 GPIO Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + +properties: + "#gpio-cells": + const: 2 + description: > + The first cell is the pin number and the second is the GPIO flags. + + compatible: + oneOf: + - enum: + - x-powers,axp209-gpio + - x-powers,axp813-gpio + - items: + - const: x-powers,axp803-gpio + - const: x-powers,axp813-gpio + + gpio-controller: true + +patternProperties: + "^.*-pins?$": + $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + items: + enum: + - GPIO0 + - GPIO1 + - GPIO2 + + function: + enum: + - adc + - ldo + - gpio_in + - gpio_out + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +... diff --git a/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml new file mode 100644 index 0000000000..31c0fc3459 --- /dev/null +++ b/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ZynqMP Mode Pin GPIO controller + +description: + PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin + GPIO controller with configurable from numbers of pins (from 0 to 3 per + PS_MODE). Every pin can be configured as input/output. + +maintainers: + - Piyush Mehta + +properties: + compatible: + const: xlnx,zynqmp-gpio-modepin + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + zynqmp-firmware { + gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +... diff --git a/dts/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml new file mode 100644 index 0000000000..3cf8629764 --- /dev/null +++ b/dts/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVDEC + +description: | + NVDEC is the hardware video decoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvdec@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvdec + - nvidia,tegra186-nvdec + - nvidia,tegra194-nvdec + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvdec + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvdec + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0xf0 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + nvdec@15480000 { + compatible = "nvidia,tegra186-nvdec"; + reg = <0x15480000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVDEC>; + clock-names = "nvdec"; + resets = <&bpmp TEGRA186_RESET_NVDEC>; + reset-names = "nvdec"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "read-1", "write"; + iommus = <&smmu TEGRA186_SID_NVDEC>; + }; diff --git a/dts/Bindings/hwlock/st,stm32-hwspinlock.yaml b/dts/Bindings/hwlock/st,stm32-hwspinlock.yaml index 47cf9c8d97..b18c616035 100644 --- a/dts/Bindings/hwlock/st,stm32-hwspinlock.yaml +++ b/dts/Bindings/hwlock/st,stm32-hwspinlock.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Hardware Spinlock bindings maintainers: - - Benjamin Gaignard - - Fabien Dessenne + - Fabien Dessenne properties: "#hwlock-cells": diff --git a/dts/Bindings/hwmon/dps650ab.txt b/dts/Bindings/hwmon/dps650ab.txt deleted file mode 100644 index 76780e7958..0000000000 --- a/dts/Bindings/hwmon/dps650ab.txt +++ /dev/null @@ -1,11 +0,0 @@ -Bindings for Delta Electronics DPS-650-AB power supply - -Required properties: -- compatible : "delta,dps650ab" -- reg : I2C address, one of 0x58, 0x59. - -Example: - dps650ab@58 { - compatible = "delta,dps650ab"; - reg = <0x58>; - }; diff --git a/dts/Bindings/hwmon/hih6130.txt b/dts/Bindings/hwmon/hih6130.txt deleted file mode 100644 index 2c43837af4..0000000000 --- a/dts/Bindings/hwmon/hih6130.txt +++ /dev/null @@ -1,12 +0,0 @@ -Honeywell Humidicon HIH-6130 humidity/temperature sensor --------------------------------------------------------- - -Requires node properties: -- compatible : "honeywell,hi6130" -- reg : the I2C address of the device. This is 0x27. - -Example: - hih6130@27 { - compatible = "honeywell,hih6130"; - reg = <0x27>; - }; diff --git a/dts/Bindings/hwmon/ibm,cffps1.txt b/dts/Bindings/hwmon/ibm,cffps1.txt deleted file mode 100644 index d9a2719f92..0000000000 --- a/dts/Bindings/hwmon/ibm,cffps1.txt +++ /dev/null @@ -1,26 +0,0 @@ -Device-tree bindings for IBM Common Form Factor Power Supply Versions 1 and 2 ------------------------------------------------------------------------------ - -Required properties: - - compatible : Must be one of the following: - "ibm,cffps1" - "ibm,cffps2" - or "ibm,cffps" if the system - must support any version of the - power supply - - reg = < I2C bus address >; : Address of the power supply on the - I2C bus. - -Example: - - i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - < more properties > - - power-supply@68 { - compatible = "ibm,cffps1"; - reg = <0x68>; - }; - }; diff --git a/dts/Bindings/hwmon/iio-hwmon.yaml b/dts/Bindings/hwmon/iio-hwmon.yaml new file mode 100644 index 0000000000..f5a6cc3efd --- /dev/null +++ b/dts/Bindings/hwmon/iio-hwmon.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ADC-attached Hardware Sensor Device Tree Bindings + +maintainers: + - Jonathan Cameron + +description: > + Bindings for hardware monitoring devices connected to ADC controllers + supporting the Industrial I/O bindings. + +properties: + compatible: + const: iio-hwmon + + io-channels: + minItems: 1 + maxItems: 8 # Should be enough + description: > + List of phandles to ADC channels to read the monitoring values + +required: + - compatible + - io-channels + +additionalProperties: false + +examples: + - | + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 1>, <&adc 2>; + }; diff --git a/dts/Bindings/hwmon/jc42.txt b/dts/Bindings/hwmon/jc42.txt deleted file mode 100644 index f569db58f6..0000000000 --- a/dts/Bindings/hwmon/jc42.txt +++ /dev/null @@ -1,46 +0,0 @@ -Properties for Jedec JC-42.4 compatible temperature sensors - -Required properties: -- compatible: May include a device-specific string consisting of the - manufacturer and the name of the chip. A list of supported - chip names follows. - Must include "jedec,jc-42.4-temp" for any Jedec JC-42.4 - compatible temperature sensor. - - Supported chip names: - adi,adt7408 - atmel,at30ts00 - atmel,at30tse004 - onnn,cat6095 - onnn,cat34ts02 - maxim,max6604 - microchip,mcp9804 - microchip,mcp9805 - microchip,mcp9808 - microchip,mcp98243 - microchip,mcp98244 - microchip,mcp9843 - nxp,se97 - nxp,se98 - st,stts2002 - st,stts2004 - st,stts3000 - st,stts424 - st,stts424e - idt,tse2002 - idt,tse2004 - idt,ts3000 - idt,ts3001 - -- reg: I2C address - -Optional properties: -- smbus-timeout-disable: When set, the smbus timeout function will be disabled. - This is not supported on all chips. - -Example: - -temp-sensor@1a { - compatible = "jedec,jc-42.4-temp"; - reg = <0x1a>; -}; diff --git a/dts/Bindings/hwmon/jedec,jc42.yaml b/dts/Bindings/hwmon/jedec,jc42.yaml new file mode 100644 index 0000000000..0e49b39011 --- /dev/null +++ b/dts/Bindings/hwmon/jedec,jc42.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/jedec,jc42.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Jedec JC-42.4 compatible temperature sensors + +maintainers: + - Jean Delvare + - Guenter Roeck + +select: + properties: + compatible: + const: jedec,jc-42.4-temp + + required: + - compatible + +properties: + compatible: + oneOf: + - const: jedec,jc-42.4-temp + - items: + - enum: + - adi,adt7408 + - atmel,at30ts00 + - atmel,at30tse004 + - idt,tse2002 + - idt,tse2004 + - idt,ts3000 + - idt,ts3001 + - maxim,max6604 + - microchip,mcp9804 + - microchip,mcp9805 + - microchip,mcp9808 + - microchip,mcp98243 + - microchip,mcp98244 + - microchip,mcp9843 + - nxp,se97 + - nxp,se97b + - nxp,se98 + - onnn,cat6095 + - onnn,cat34ts02 + - st,stts2002 + - st,stts2004 + - st,stts3000 + - st,stts424 + - st,stts424e + - const: jedec,jc-42.4-temp + + reg: + maxItems: 1 + + smbus-timeout-disable: + description: | + When set, the smbus timeout function will be disabled. This is not + supported on all chips. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + temp-sensor@1a { + compatible = "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + }; diff --git a/dts/Bindings/hwmon/lltc,ltc4151.yaml b/dts/Bindings/hwmon/lltc,ltc4151.yaml new file mode 100644 index 0000000000..4b5851c326 --- /dev/null +++ b/dts/Bindings/hwmon/lltc,ltc4151.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/lltc,ltc4151.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LTC4151 High Voltage I2C Current and Voltage Monitor + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: lltc,ltc4151 + + reg: + maxItems: 1 + + shunt-resistor-micro-ohms: + description: + Shunt resistor value in micro-Ohms + default: 1000 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@6e { + compatible = "lltc,ltc4151"; + reg = <0x6e>; + shunt-resistor-micro-ohms = <1500>; + }; + }; diff --git a/dts/Bindings/hwmon/lm70.txt b/dts/Bindings/hwmon/lm70.txt deleted file mode 100644 index ea417a0d32..0000000000 --- a/dts/Bindings/hwmon/lm70.txt +++ /dev/null @@ -1,22 +0,0 @@ -* LM70/TMP121/LM71/LM74 thermometer. - -Required properties: -- compatible: one of - "ti,lm70" - "ti,tmp121" - "ti,tmp122" - "ti,lm71" - "ti,lm74" - -See Documentation/devicetree/bindings/spi/spi-bus.txt for more required and -optional properties. - -Example: - -spi_master { - temperature-sensor@0 { - compatible = "ti,lm70"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; diff --git a/dts/Bindings/hwmon/lm90.txt b/dts/Bindings/hwmon/lm90.txt deleted file mode 100644 index 398dcb9657..0000000000 --- a/dts/Bindings/hwmon/lm90.txt +++ /dev/null @@ -1,51 +0,0 @@ -* LM90 series thermometer. - -Required node properties: -- compatible: manufacturer and chip name, one of - "adi,adm1032" - "adi,adt7461" - "adi,adt7461a" - "gmt,g781" - "national,lm90" - "national,lm86" - "national,lm89" - "national,lm99" - "dallas,max6646" - "dallas,max6647" - "dallas,max6649" - "dallas,max6657" - "dallas,max6658" - "dallas,max6659" - "dallas,max6680" - "dallas,max6681" - "dallas,max6695" - "dallas,max6696" - "onnn,nct1008" - "winbond,w83l771" - "nxp,sa56004" - "ti,tmp451" - -- reg: I2C bus address of the device - -- vcc-supply: vcc regulator for the supply voltage. - -Optional properties: -- interrupts: Contains a single interrupt specifier which describes the - LM90 "-ALERT" pin output. - See interrupt-controller/interrupts.txt for the format. - -- #thermal-sensor-cells: should be set to 1. See thermal/thermal-sensor.yaml - for details. See for the - definition of the local, remote and 2nd remote sensor index - constants. - -Example LM90 node: - -temp-sensor { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = ; - #thermal-sensor-cells = <1>; -} diff --git a/dts/Bindings/hwmon/ltc4151.txt b/dts/Bindings/hwmon/ltc4151.txt deleted file mode 100644 index d008a5ef52..0000000000 --- a/dts/Bindings/hwmon/ltc4151.txt +++ /dev/null @@ -1,18 +0,0 @@ -LTC4151 High Voltage I2C Current and Voltage Monitor - -Required properties: -- compatible: Must be "lltc,ltc4151" -- reg: I2C address - -Optional properties: -- shunt-resistor-micro-ohms - Shunt resistor value in micro-Ohms - Defaults to <1000> if unset. - -Example: - -ltc4151@6e { - compatible = "lltc,ltc4151"; - reg = <0x6e>; - shunt-resistor-micro-ohms = <1500>; -}; diff --git a/dts/Bindings/hwmon/mcp3021.txt b/dts/Bindings/hwmon/mcp3021.txt deleted file mode 100644 index 294318ba69..0000000000 --- a/dts/Bindings/hwmon/mcp3021.txt +++ /dev/null @@ -1,21 +0,0 @@ -mcp3021 properties - -Required properties: -- compatible: Must be one of the following: - - "microchip,mcp3021" for mcp3021 - - "microchip,mcp3221" for mcp3221 -- reg: I2C address - -Optional properties: - -- reference-voltage-microvolt - Reference voltage in microvolt (uV) - -Example: - -mcp3021@4d { - compatible = "microchip,mcp3021"; - reg = <0x4d>; - - reference-voltage-microvolt = <4500000>; /* 4.5 V */ -}; diff --git a/dts/Bindings/hwmon/microchip,mcp3021.yaml b/dts/Bindings/hwmon/microchip,mcp3021.yaml new file mode 100644 index 0000000000..c42051f8a1 --- /dev/null +++ b/dts/Bindings/hwmon/microchip,mcp3021.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,mcp3021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MCP3021 A/D converter + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - microchip,mcp3021 + - microchip,mcp3221 + + reg: + maxItems: 1 + + reference-voltage-microvolt: + description: + VDD supply power and reference voltage + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@4d { + compatible = "microchip,mcp3021"; + reg = <0x4d>; + + reference-voltage-microvolt = <4500000>; /* 4.5 V */ + }; + }; diff --git a/dts/Bindings/hwmon/national,lm90.yaml b/dts/Bindings/hwmon/national,lm90.yaml new file mode 100644 index 0000000000..6e1d54ff5d --- /dev/null +++ b/dts/Bindings/hwmon/national,lm90.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/national,lm90.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LM90 series thermometer + +maintainers: + - Jean Delvare + - Guenter Roeck + +properties: + compatible: + enum: + - adi,adm1032 + - adi,adt7461 + - adi,adt7461a + - dallas,max6646 + - dallas,max6647 + - dallas,max6649 + - dallas,max6657 + - dallas,max6658 + - dallas,max6659 + - dallas,max6680 + - dallas,max6681 + - dallas,max6695 + - dallas,max6696 + - gmt,g781 + - national,lm86 + - national,lm89 + - national,lm90 + - national,lm99 + - nxp,sa56004 + - onnn,nct1008 + - ti,tmp451 + - winbond,w83l771 + + + interrupts: + items: + - description: | + Single interrupt specifier which describes the LM90 "-ALERT" pin + output. + + reg: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + vcc-supply: + description: phandle to the regulator that provides the +VCC supply + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&palmas_ldo6_reg>; + interrupt-parent = <&gpio>; + interrupts = ; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/dts/Bindings/hwmon/ntc-thermistor.yaml b/dts/Bindings/hwmon/ntc-thermistor.yaml new file mode 100644 index 0000000000..9e77cee07d --- /dev/null +++ b/dts/Bindings/hwmon/ntc-thermistor.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/hwmon/ntc-thermistor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NTC thermistor temperature sensors + +maintainers: + - Naveen Krishna Chatradhi + - Linus Walleij + +description: | + Thermistors with negative temperature coefficient (NTC) are resistors that + vary in resistance in an often non-linear way in relation to temperature. + The negative temperature coefficient means that the resistance decreases + as the temperature rises. Since the relationship between resistance and + temperature is non-linear, software drivers most often need to use a look + up table and interpolation to get from resistance to temperature. + + When used in practice, a thermistor is often connected between ground, a + pull-up resistor or/and a pull-down resistor and a fixed voltage like this: + + + e.g. 5V = pull-up voltage (puv) + | + +-+ + | | + | | Pull-up resistor + | | (puo) + +-+ + |-------------------------o + +-+ | ^ + | |/ | + | / | + |/| Thermistor | Measured voltage (mv) + / | | "connected ground" + /| | | + +-+ | + |-------------------------o + +-+ ^ + | | | + | | Pull-down resistor | Measured voltage (mv) + | | (pdo) | "connected positive" + +-+ | + | | + | v + + GND GND + + The arrangements of where we measure the voltage over the thermistor are + called "connected ground" and "connected positive" and shall be understood as + the cases when either pull-up or pull-down resistance is zero. + + If the pull-up resistance is 0 one end of the thermistor is connected to the + positive voltage and we get the thermistor on top of a pull-down resistor + and we take the measure between the thermistor and the pull-down resistor. + + Conversely if the pull-down resistance is zero, one end of the thermistor is + connected to ground and we get the thermistor under the pull-up resistor + and we take the measure between the pull-up resistor and the thermistor. + + We can use both pull-up and pull-down resistors at the same time, and then + the figure illustrates where the voltage will be measured for the "connected + ground" and "connected positive" cases. + +properties: + $nodename: + pattern: "^thermistor(.*)?$" + + compatible: + oneOf: + - const: epcos,b57330v2103 + - const: epcos,b57891s0103 + - const: murata,ncp15wb473 + - const: murata,ncp18wb473 + - const: murata,ncp21wb473 + - const: murata,ncp03wb473 + - const: murata,ncp15wl333 + - const: murata,ncp03wf104 + - const: murata,ncp15xh103 + # Deprecated "ntp," compatible strings + - const: ntc,ncp15wb473 + deprecated: true + - const: ntc,ncp18wb473 + deprecated: true + - const: ntc,ncp21wb473 + deprecated: true + - const: ntc,ncp03wb473 + deprecated: true + - const: ntc,ncp15wl333 + deprecated: true + + "#thermal-sensor-cells": + description: Thermal sensor cells if used for thermal sensoring. + const: 0 + + pullup-uv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Pull-up voltage in micro volts. Must always be specified. + + pullup-ohm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Pull-up resistance in ohms. Must always be specified, even + if zero. + + pulldown-ohm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Pull-down resistance in ohms. Must always be specified, even + if zero. + + connected-positive: + $ref: /schemas/types.yaml#/definitions/flag + description: Indicates how the thermistor is connected in series with + a pull-up and/or a pull-down resistor. See the description above for + an illustration. If this flag is NOT specified, the thermistor is assumed + to be connected-ground, which usually means a pull-down resistance of + zero but complex arrangements are possible. + + # See /schemas/iio/adc/adc.yaml + io-channels: + maxItems: 1 + description: IIO ADC channel to read the voltage over the resistor. Must + always be specified. + +required: + - compatible + - pullup-uv + - pullup-ohm + - pulldown-ohm + - io-channels + +additionalProperties: false + +examples: + - | + thermistor0 { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x06>; + pullup-uv = <1800000>; + pullup-ohm = <220000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; diff --git a/dts/Bindings/hwmon/ntc_thermistor.txt b/dts/Bindings/hwmon/ntc_thermistor.txt deleted file mode 100644 index 4c5c371297..0000000000 --- a/dts/Bindings/hwmon/ntc_thermistor.txt +++ /dev/null @@ -1,44 +0,0 @@ -NTC Thermistor hwmon sensors -------------------------------- - -Requires node properties: -- "compatible" value : one of - "epcos,b57330v2103" - "epcos,b57891s0103" - "murata,ncp15wb473" - "murata,ncp18wb473" - "murata,ncp21wb473" - "murata,ncp03wb473" - "murata,ncp15wl333" - "murata,ncp03wf104" - "murata,ncp15xh103" - -/* Usage of vendor name "ntc" is deprecated */ - "ntc,ncp15wb473" - "ntc,ncp18wb473" - "ntc,ncp21wb473" - "ntc,ncp03wb473" - "ntc,ncp15wl333" - -- "pullup-uv" Pull up voltage in micro volts -- "pullup-ohm" Pull up resistor value in ohms -- "pulldown-ohm" Pull down resistor value in ohms -- "connected-positive" Always ON, If not specified. - Status change is possible. -- "io-channels" Channel node of ADC to be used for - conversion. - -Optional node properties: -- "#thermal-sensor-cells" Used to expose itself to thermal fw. - -Read more about iio bindings at - https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/ - -Example: - ncp15wb473@0 { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <47000>; - pulldown-ohm = <0>; - io-channels = <&adc 3>; - }; diff --git a/dts/Bindings/hwmon/nuvoton,nct7802.yaml b/dts/Bindings/hwmon/nuvoton,nct7802.yaml new file mode 100644 index 0000000000..2f0620eccc --- /dev/null +++ b/dts/Bindings/hwmon/nuvoton,nct7802.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/nuvoton,nct7802.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NCT7802Y Hardware Monitoring IC + +maintainers: + - Guenter Roeck + +description: | + The NCT7802Y is a hardware monitor IC which supports one on-die and up to + 5 remote temperature sensors with SMBus interface. + + Datasheets: + https://www.nuvoton.com/export/resource-files/Nuvoton_NCT7802Y_Datasheet_V12.pdf + +additionalProperties: false + +properties: + compatible: + enum: + - nuvoton,nct7802 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-3]$": + type: object + + additionalProperties: false + + properties: + reg: + items: + - enum: + - 0 # Local Temperature Sensor ("LTD") + - 1 # Remote Temperature Sensor or Voltage Sensor 1 ("RTD1") + - 2 # Remote Temperature Sensor or Voltage Sensor 2 ("RTD2") + - 3 # Remote Temperature Sensor or Voltage Sensor 3 ("RTD3") + + sensor-type: + items: + - enum: + - temperature + - voltage + + temperature-mode: + items: + - enum: + - thermistor + - thermal-diode + + required: + - reg + + allOf: + # For channels RTD1, RTD2 and RTD3, require sensor-type to be set. + # Otherwise (for all other channels), do not allow temperature-mode to be + # set. + - if: + properties: + reg: + items: + - enum: + - 1 + - 2 + - 3 + then: + required: + - sensor-type + else: + not: + required: + - sensor-type + + # For channels RTD1 and RTD2 and if sensor-type is "temperature", require + # temperature-mode to be set. Otherwise (for all other channels or + # sensor-type settings), do not allow temperature-mode to be set + - if: + properties: + reg: + items: + - enum: + - 1 + - 2 + sensor-type: + items: + - enum: + - temperature + then: + required: + - temperature-mode + else: + not: + required: + - temperature-mode + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nct7802@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "voltage"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermal-diode"; + }; + + channel@3 { /* RTD3 */ + reg = <3>; + sensor-type = "temperature"; + }; + }; + }; diff --git a/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml b/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml new file mode 100644 index 0000000000..da8292bc32 --- /dev/null +++ b/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/pmbus/ti,lm25066.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: National Semiconductor/Texas Instruments LM250x6/LM506x power-management ICs + +maintainers: + - Zev Weiss + +description: | + The LM25066 family of power-management ICs (a.k.a. hot-swap + controllers or eFuses in various contexts) are PMBus devices that + offer temperature, current, voltage, and power monitoring. + + Datasheet: https://www.ti.com/lit/ds/symlink/lm25066.pdf + +properties: + compatible: + enum: + - ti,lm25056 + - ti,lm25066 + - ti,lm5064 + - ti,lm5066 + - ti,lm5066i + + reg: + maxItems: 1 + + shunt-resistor-micro-ohms: + description: + Shunt (sense) resistor value in micro-Ohms + default: 1000 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@40 { + compatible = "ti,lm25066"; + reg = <0x40>; + shunt-resistor-micro-ohms = <675>; + }; + }; diff --git a/dts/Bindings/hwmon/sensirion,sht15.yaml b/dts/Bindings/hwmon/sensirion,sht15.yaml new file mode 100644 index 0000000000..4669217d01 --- /dev/null +++ b/dts/Bindings/hwmon/sensirion,sht15.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/sensirion,sht15.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sensirion SHT15 humidity and temperature sensor + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: sensirion,sht15 + + clk-gpios: + maxItems: 1 + + data-gpios: + maxItems: 1 + + vcc-supply: + description: regulator that drives the VCC pin + +required: + - compatible + - clk-gpios + - data-gpios + - vcc-supply + +additionalProperties: false + +examples: + - | + sensor { + compatible = "sensirion,sht15"; + clk-gpios = <&gpio4 12 0>; + data-gpios = <&gpio4 13 0>; + vcc-supply = <®_sht15>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sensor>; + }; diff --git a/dts/Bindings/hwmon/sht15.txt b/dts/Bindings/hwmon/sht15.txt deleted file mode 100644 index 6a80277cc4..0000000000 --- a/dts/Bindings/hwmon/sht15.txt +++ /dev/null @@ -1,19 +0,0 @@ -Sensirion SHT15 Humidity and Temperature Sensor - -Required properties: - - - "compatible": must be "sensirion,sht15". - - "data-gpios": GPIO connected to the data line. - - "clk-gpios": GPIO connected to the clock line. - - "vcc-supply": regulator that drives the VCC pin. - -Example: - - sensor { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sensor>; - compatible = "sensirion,sht15"; - clk-gpios = <&gpio4 12 0>; - data-gpios = <&gpio4 13 0>; - vcc-supply = <®_sht15>; - }; diff --git a/dts/Bindings/hwmon/ti,tmp102.yaml b/dts/Bindings/hwmon/ti,tmp102.yaml new file mode 100644 index 0000000000..d3eff4fac1 --- /dev/null +++ b/dts/Bindings/hwmon/ti,tmp102.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/ti,tmp102.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TMP102 temperature sensor + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - ti,tmp102 + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/dts/Bindings/hwmon/ti,tmp108.yaml b/dts/Bindings/hwmon/ti,tmp108.yaml new file mode 100644 index 0000000000..eda55bbc17 --- /dev/null +++ b/dts/Bindings/hwmon/ti,tmp108.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/ti,tmp108.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TMP108 temperature sensor + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - ti,tmp108 + + interrupts: + items: + - description: alert interrupt + + reg: + maxItems: 1 + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tmp_alrt>; + #thermal-sensor-cells = <0>; + }; + }; diff --git a/dts/Bindings/hwmon/ti,tmp421.yaml b/dts/Bindings/hwmon/ti,tmp421.yaml new file mode 100644 index 0000000000..36f649938f --- /dev/null +++ b/dts/Bindings/hwmon/ti,tmp421.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/ti,tmp421.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TMP42x/TMP44x temperature sensor + +maintainers: + - Guenter Roeck + +description: | + ±1°C Remote and Local temperature sensor + https://www.ti.com/lit/ds/symlink/tmp422.pdf + +properties: + compatible: + enum: + - ti,tmp421 + - ti,tmp422 + - ti,tmp423 + - ti,tmp441 + - ti,tmp442 + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "^channel@([0-3])$": + type: object + description: | + Represents channels of the device and their specific configuration. + + properties: + reg: + description: | + The channel number. 0 is local channel, 1-3 are remote channels + items: + minimum: 0 + maximum: 3 + + label: + description: | + A descriptive name for this channel, like "ambient" or "psu". + + ti,n-factor: + description: | + The value (two's complement) to be programmed in the channel specific N correction register. + For remote channels only. + $ref: /schemas/types.yaml#/definitions/uint32 + items: + minimum: 0 + maximum: 255 + + required: + - reg + + additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@4c { + compatible = "ti,tmp422"; + reg = <0x4c>; + }; + }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@4c { + compatible = "ti,tmp422"; + reg = <0x4c>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + ti,n-factor = <0x1>; + label = "local"; + }; + + channel@1 { + reg = <0x1>; + ti,n-factor = <0x0>; + label = "somelabel"; + }; + + channel@2 { + reg = <0x2>; + status = "disabled"; + }; + }; + }; diff --git a/dts/Bindings/hwmon/tmp108.txt b/dts/Bindings/hwmon/tmp108.txt deleted file mode 100644 index 54d4beed4e..0000000000 --- a/dts/Bindings/hwmon/tmp108.txt +++ /dev/null @@ -1,18 +0,0 @@ -TMP108 temperature sensor -------------------------- - -This device supports I2C only. - -Requires node properties: -- compatible : "ti,tmp108" -- reg : the I2C address of the device. This is 0x48, 0x49, 0x4a, or 0x4b. - -Optional properties: -- interrupts: Reference to the TMP108 alert interrupt. -- #thermal-sensor-cells: should be set to 0. - -Example: - tmp108@48 { - compatible = "ti,tmp108"; - reg = <0x48>; - }; diff --git a/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml b/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml index 6097e8ac46..1b03810d4b 100644 --- a/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml +++ b/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml @@ -55,7 +55,7 @@ examples: #size-cells = <0>; axp221: pmic@68 { - compatible = "x-powers,axp221"; + /* compatible = "x-powers,axp221"; */ reg = <0x68>; }; }; diff --git a/dts/Bindings/i2c/apple,i2c.yaml b/dts/Bindings/i2c/apple,i2c.yaml new file mode 100644 index 0000000000..22fc848325 --- /dev/null +++ b/dts/Bindings/i2c/apple,i2c.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/i2c/apple,i2c.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Apple/PASemi I2C controller + +maintainers: + - Sven Peter + +description: | + Apple SoCs such as the M1 come with a I2C controller based on the one found + in machines with P. A. Semi's PWRficient processors. + The bus is used to communicate with e.g. USB PD chips or the speaker + amp. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - apple,t8103-i2c + - apple,i2c + + reg: + maxItems: 1 + + clocks: + items: + - description: I2C bus reference clock + + interrupts: + maxItems: 1 + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. If not specified, 100 kHz will be + used. This frequency is generated by dividing the reference clock. + Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c@35010000 { + compatible = "apple,t8103-i2c"; + reg = <0x35010000 0x4000>; + interrupt-parent = <&aic>; + interrupts = <0 627 4>; + clocks = <&ref_clk>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/i2c/i2c-imx.yaml b/dts/Bindings/i2c/i2c-imx.yaml index 3592d49235..c167958ae2 100644 --- a/dts/Bindings/i2c/i2c-imx.yaml +++ b/dts/Bindings/i2c/i2c-imx.yaml @@ -57,7 +57,9 @@ properties: const: ipg clock-frequency: - enum: [ 100000, 400000 ] + minimum: 1 + default: 100000 + maximum: 400000 dmas: items: diff --git a/dts/Bindings/i2c/i2c-xlp9xx.txt b/dts/Bindings/i2c/i2c-xlp9xx.txt deleted file mode 100644 index f818ef507a..0000000000 --- a/dts/Bindings/i2c/i2c-xlp9xx.txt +++ /dev/null @@ -1,22 +0,0 @@ -Device tree configuration for the I2C controller on the XLP9xx/5xx SoC - -Required properties: -- compatible : should be "netlogic,xlp980-i2c" -- reg : bus address start and address range size of device -- interrupts : interrupt number - -Optional properties: -- clock-frequency : frequency of bus clock in Hz - Defaults to 100 KHz when the property is not specified - -Example: - -i2c0: i2c@113100 { - compatible = "netlogic,xlp980-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x113100 0x100>; - clock-frequency = <400000>; - interrupts = <30>; - interrupt-parent = <&pic>; -}; diff --git a/dts/Bindings/i2c/ingenic,i2c.yaml b/dts/Bindings/i2c/ingenic,i2c.yaml index e1e65eb4f7..febde6cc5f 100644 --- a/dts/Bindings/i2c/ingenic,i2c.yaml +++ b/dts/Bindings/i2c/ingenic,i2c.yaml @@ -60,7 +60,7 @@ unevaluatedProperties: false examples: - | - #include + #include #include #include i2c@10054000 { diff --git a/dts/Bindings/i2c/st,stm32-i2c.yaml b/dts/Bindings/i2c/st,stm32-i2c.yaml index d747f4990a..c07289a643 100644 --- a/dts/Bindings/i2c/st,stm32-i2c.yaml +++ b/dts/Bindings/i2c/st,stm32-i2c.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: I2C controller embedded in STMicroelectronics STM32 I2C platform maintainers: - - Pierre-Yves MORDRET + - Pierre-Yves MORDRET allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/dts/Bindings/iio/accel/adi,adxl313.yaml b/dts/Bindings/iio/accel/adi,adxl313.yaml new file mode 100644 index 0000000000..d6afc1b8c2 --- /dev/null +++ b/dts/Bindings/iio/accel/adi,adxl313.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/adi,adxl313.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADXL313 3-Axis Digital Accelerometer + +maintainers: + - Lucas Stankus + +description: | + Analog Devices ADXL313 3-Axis Digital Accelerometer that supports + both I2C & SPI interfaces. + https://www.analog.com/en/products/adxl313.html + +properties: + compatible: + enum: + - adi,adxl313 + + reg: + maxItems: 1 + + spi-3wire: true + + spi-max-frequency: true + + vs-supply: + description: Regulator that supplies power to the accelerometer + + vdd-supply: + description: Regulator that supplies the digital interface supply voltage + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a I2C device node */ + accelerometer@53 { + compatible = "adi,adxl313"; + reg = <0x53>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; + }; + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a SPI device node */ + accelerometer@0 { + compatible = "adi,adxl313"; + reg = <0>; + spi-max-frequency = <5000000>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; + }; diff --git a/dts/Bindings/iio/accel/adi,adxl355.yaml b/dts/Bindings/iio/accel/adi,adxl355.yaml new file mode 100644 index 0000000000..ba54d6998f --- /dev/null +++ b/dts/Bindings/iio/accel/adi,adxl355.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/accel/adi,adxl355.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADXL355 3-Axis, Low noise MEMS Accelerometer + +maintainers: + - Puranjay Mohan + +description: | + Analog Devices ADXL355 3-Axis, Low noise MEMS Accelerometer that supports + both I2C & SPI interfaces + https://www.analog.com/en/products/adxl355.html + +properties: + compatible: + enum: + - adi,adxl355 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 3 + description: | + Type for DRDY should be IRQ_TYPE_EDGE_RISING. + Three configurable interrupt lines exist. + + interrupt-names: + description: Specify which interrupt line is in use. + items: + enum: + - INT1 + - INT2 + - DRDY + minItems: 1 + maxItems: 3 + + vdd-supply: + description: Regulator that provides power to the sensor + + vddio-supply: + description: Regulator that provides power to the bus + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + /* Example for a I2C device node */ + accelerometer@1d { + compatible = "adi,adxl355"; + reg = <0x1d>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; + }; + }; + - | + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@0 { + compatible = "adi,adxl355"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; + }; + }; diff --git a/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml b/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml index 52fa0f7c2d..714e48e613 100644 --- a/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml +++ b/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml @@ -21,6 +21,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + vdd-supply: true vddio-supply: true diff --git a/dts/Bindings/iio/adc/adi,ad7949.yaml b/dts/Bindings/iio/adc/adi,ad7949.yaml index 9b56bd4d55..0b10ed5f74 100644 --- a/dts/Bindings/iio/adc/adi,ad7949.yaml +++ b/dts/Bindings/iio/adc/adi,ad7949.yaml @@ -26,19 +26,43 @@ properties: reg: maxItems: 1 + vrefin-supply: + description: + Buffered ADC reference voltage supply. + vref-supply: description: - ADC reference voltage supply + Unbuffered ADC reference voltage supply. + + adi,internal-ref-microvolt: + description: | + Internal reference voltage selection in microvolts. + + If no internal reference is specified, the channel will default to the + external reference defined by vrefin-supply (or vref-supply). + vrefin-supply will take precedence over vref-supply if both are defined. + + If no supplies are defined, the reference selection will default to + 4096mV internal reference. + + enum: [2500000, 4096000] + default: 4096000 + spi-max-frequency: true - "#io-channel-cells": + '#io-channel-cells': const: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + required: - compatible - reg - - vref-supply additionalProperties: false @@ -49,9 +73,30 @@ examples: #size-cells = <0>; adc@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad7949"; reg = <0>; vref-supply = <&vdd_supply>; }; + + adc@1 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,ad7949"; + reg = <1>; + vrefin-supply = <&vdd_supply>; + }; + + adc@2 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "adi,ad7949"; + reg = <2>; + adi,internal-ref-microvolt = <4096000>; + }; }; ... diff --git a/dts/Bindings/iio/adc/adi,ad799x.yaml b/dts/Bindings/iio/adc/adi,ad799x.yaml new file mode 100644 index 0000000000..29641ce717 --- /dev/null +++ b/dts/Bindings/iio/adc/adi,ad799x.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad799x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD799x analog to digital converters + +maintainers: + - Michael Hennerich + +description: | + Support for Analog Devices AD7991, AD7992, AD7993, AD7994, AD7995, AD7997, AD7998, + AD7999 and similar analog to digital converters. + Specifications on the converters can be found at: + AD7991, AD7995, AD7999: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7991_7995_7999.pdf + AD7992: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7992.pdf + AD7993, AD7994: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7993_7994.pdf + AD7997, AD7998: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7997_7998.pdf + +properties: + compatible: + enum: + - adi,ad7991 + - adi,ad7992 + - adi,ad7993 + - adi,ad7994 + - adi,ad7995 + - adi,ad7997 + - adi,ad7998 + - adi,ad7999 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vcc-supply: + description: + ADC power supply + + vref-supply: + description: + ADC reference voltage supply, optional for AD7991, AD7995 and AD7999 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc1: adc@28 { + reg = <0x28>; + compatible = "adi,ad7991"; + interrupts = <13 2>; + interrupt-parent = <&gpio6>; + + vcc-supply = <&vcc_3v3>; + vref-supply = <&adc_vref>; + }; + }; +... diff --git a/dts/Bindings/iio/adc/aspeed,ast2600-adc.yaml b/dts/Bindings/iio/adc/aspeed,ast2600-adc.yaml new file mode 100644 index 0000000000..b283c8ca2b --- /dev/null +++ b/dts/Bindings/iio/adc/aspeed,ast2600-adc.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADC that forms part of an ASPEED server management processor. + +maintainers: + - Billy Tsai + +description: | + • 10-bits resolution for 16 voltage channels. + • The device split into two individual engine and each contains 8 voltage + channels. + • Channel scanning can be non-continuous. + • Programmable ADC clock frequency. + • Programmable upper and lower threshold for each channels. + • Interrupt when larger or less than threshold for each channels. + • Support hysteresis for each channels. + • Built-in a compensating method. + • Built-in a register to trim internal reference voltage. + • Internal or External reference voltage. + • Support 2 Internal reference voltage 1.2v or 2.5v. + • Integrate dividing circuit for battery sensing. + +properties: + compatible: + enum: + - aspeed,ast2600-adc0 + - aspeed,ast2600-adc1 + description: + Their trimming data, which is used to calibrate internal reference volage, + locates in different address of OTP. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Input clock used to derive the sample clock. Expected to be the + SoC's APB clock. + + resets: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + vref-supply: + description: + The external regulator supply ADC reference voltage. + + aspeed,int-vref-microvolt: + enum: [1200000, 2500000] + description: + ADC internal reference voltage in microvolts. + + aspeed,battery-sensing: + type: boolean + description: + Inform the driver that last channel will be used to sensor battery. + + aspeed,trim-data-valid: + type: boolean + description: | + The ADC reference voltage can be calibrated to obtain the trimming + data which will be stored in otp. This property informs the driver that + the data store in the otp is valid. + +required: + - compatible + - reg + - clocks + - resets + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + adc0: adc@1e6e9000 { + compatible = "aspeed,ast2600-adc0"; + reg = <0x1e6e9000 0x100>; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + aspeed,int-vref-microvolt = <2500000>; + }; + adc1: adc@1e6e9100 { + compatible = "aspeed,ast2600-adc1"; + reg = <0x1e6e9100 0x100>; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_ADC>; + #io-channel-cells = <1>; + aspeed,int-vref-microvolt = <2500000>; + }; +... diff --git a/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml index 79c13b408e..efed361215 100644 --- a/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -15,6 +15,7 @@ properties: enum: - atmel,sama5d2-adc - microchip,sam9x60-adc + - microchip,sama7g5-adc reg: maxItems: 1 diff --git a/dts/Bindings/iio/adc/ingenic,adc.yaml b/dts/Bindings/iio/adc/ingenic,adc.yaml index 3eb7aa8822..698beb896f 100644 --- a/dts/Bindings/iio/adc/ingenic,adc.yaml +++ b/dts/Bindings/iio/adc/ingenic,adc.yaml @@ -74,7 +74,7 @@ additionalProperties: false examples: - | - #include + #include #include adc@10070000 { diff --git a/dts/Bindings/iio/adc/nxp,imx8qxp-adc.yaml b/dts/Bindings/iio/adc/nxp,imx8qxp-adc.yaml new file mode 100644 index 0000000000..9c59a20a60 --- /dev/null +++ b/dts/Bindings/iio/adc/nxp,imx8qxp-adc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP IMX8QXP ADC bindings + +maintainers: + - Cai Huoqing + +description: + Supports the ADC found on the IMX8QXP SoC. + +properties: + compatible: + const: nxp,imx8qxp-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: per + - const: ipg + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-rates + - power-domains + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX_SC_R_ADC_0>, + <&clk IMX_SC_R_ADC_0>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + #io-channel-cells = <1>; + }; + }; +... diff --git a/dts/Bindings/iio/adc/sigma-delta-modulator.yaml b/dts/Bindings/iio/adc/sigma-delta-modulator.yaml index a390343d0c..2287697f1f 100644 --- a/dts/Bindings/iio/adc/sigma-delta-modulator.yaml +++ b/dts/Bindings/iio/adc/sigma-delta-modulator.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Device-Tree bindings for sigma delta modulator maintainers: - - Arnaud Pouliquen + - Arnaud Pouliquen properties: compatible: diff --git a/dts/Bindings/iio/adc/st,stm32-adc.yaml b/dts/Bindings/iio/adc/st,stm32-adc.yaml index a58334c3bb..4d6074518b 100644 --- a/dts/Bindings/iio/adc/st,stm32-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-adc.yaml @@ -19,7 +19,7 @@ description: | Each STM32 ADC block can have up to 3 ADC instances. maintainers: - - Fabrice Gasnier + - Fabrice Gasnier properties: compatible: @@ -222,6 +222,12 @@ patternProperties: '#io-channel-cells': const: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + interrupts: description: | IRQ Line for the ADC instance. Valid values are: @@ -256,6 +262,7 @@ patternProperties: - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and stm32mp1. $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true st,adc-diff-channels: description: | @@ -265,7 +272,9 @@ patternProperties: , ,... vinp and vinn are numbered from 0 to 19. Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is - required. Both properties can be used together. Some channels can be + required if no adc generic channel is defined. These legacy channel + properties are exclusive with adc generic channel bindings. + Both properties can be used together. Some channels can be used as single-ended and some other ones as differential (mixed). But channels can't be configured both as single-ended and differential. $ref: /schemas/types.yaml#/definitions/uint32-matrix @@ -279,6 +288,7 @@ patternProperties: "vinn" indicates negative input number minimum: 0 maximum: 19 + deprecated: true st,min-sample-time-nsecs: description: @@ -289,6 +299,50 @@ patternProperties: list, to set sample time resp. for all channels, or independently for each channel. $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true + + nvmem-cells: + items: + - description: Phandle to the calibration vrefint data provided by otp + + nvmem-cell-names: + items: + - const: vrefint + + patternProperties: + "^channel@([0-9]|1[0-9])$": + type: object + $ref: "adc.yaml" + description: Represents the external channels which are connected to the ADC. + + properties: + reg: + items: + minimum: 0 + maximum: 19 + + label: + description: | + Unique name to identify which channel this is. + Reserved label names "vddcore", "vrefint" and "vbat" + are used to identify internal channels with matching names. + + diff-channels: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minimum: 0 + maximum: 19 + + st,min-sample-time-ns: + description: | + Minimum sampling time in nanoseconds. Depending on hardware (board) + e.g. high/low analog input source impedance, fine tune of ADC + sampling time may be recommended. + + required: + - reg + + additionalProperties: false allOf: - if: @@ -369,12 +423,6 @@ patternProperties: additionalProperties: false - anyOf: - - required: - - st,adc-channels - - required: - - st,adc-diff-channels - required: - compatible - reg @@ -451,4 +499,50 @@ examples: // other adc child node follow... }; + - | + // Example 3: with stm32mp157c to setup ADC2 with: + // - internal channels 13, 14, 15. + #include + #include + adc122: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = , + ; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + booster-supply = <&booster>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vref>; + st,syscfg = <&syscfg>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupts = <1>; + #address-cells = <1>; + #size-cells = <0>; + channel@13 { + reg = <13>; + label = "vrefint"; + st,min-sample-time-ns = <9000>; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; + }; + }; + ... diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 733351dee2..7c260f2096 100644 --- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DFSDM ADC device driver maintainers: - - Fabrice Gasnier - - Olivier Moysan + - Fabrice Gasnier + - Olivier Moysan description: | STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to diff --git a/dts/Bindings/iio/adc/ti,am3359-adc.yaml b/dts/Bindings/iio/adc/ti,am3359-adc.yaml new file mode 100644 index 0000000000..d6f21d5ccc --- /dev/null +++ b/dts/Bindings/iio/adc/ti,am3359-adc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM3359 ADC + +maintainers: + - Miquel Raynal + +properties: + compatible: + enum: + - ti,am3359-adc + - ti,am4372-adc + + '#io-channel-cells': + const: 1 + + ti,adc-channels: + description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and + so on until AIN7 = 7. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + ti,chan-step-opendelay: + description: List of open delays for each channel of ADC in the order of + ti,adc-channels. The value corresponds to the number of ADC clock cycles + to wait after applying the step configuration registers and before sending + the start of ADC conversion. Maximum value is 0x3FFFF. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + ti,chan-step-sampledelay: + description: List of sample delays for each channel of ADC in the order of + ti,adc-channels. The value corresponds to the number of ADC clock cycles + to sample (to hold start of conversion high). Maximum value is 0xFF. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + ti,chan-step-avg: + description: Number of averages to be performed for each channel of ADC. If + average is 16 (this is also the maximum) then input is sampled 16 times + and averaged to get more accurate value. This increases the time taken by + ADC to generate a sample. Maximum value is 16. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + +required: + - compatible + - '#io-channel-cells' + - ti,adc-channels + +additionalProperties: false + +examples: + - | + adc { + compatible = "ti,am3359-adc"; + #io-channel-cells = <1>; + ti,adc-channels = <4 5 6 7>; + ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; + ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; + ti,chan-step-avg = <16 2 4 8>; + }; diff --git a/dts/Bindings/iio/chemical/senseair,sunrise.yaml b/dts/Bindings/iio/chemical/senseair,sunrise.yaml new file mode 100644 index 0000000000..337fe09e4b --- /dev/null +++ b/dts/Bindings/iio/chemical/senseair,sunrise.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/chemical/senseair,sunrise.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Senseair Sunrise 006-0-0007 CO2 Sensor + +maintainers: + - Jacopo Mondi + +description: | + Senseair Sunrise 006-0-0007 is a NDIR CO2 sensor. It supports I2C or UART buses + for communications and control. + + Datasheets: + https://rmtplusstoragesenseair.blob.core.windows.net/docs/Dev/publicerat/PSP11704.pdf + https://rmtplusstoragesenseair.blob.core.windows.net/docs/Dev/publicerat/PSH11649.pdf + https://rmtplusstoragesenseair.blob.core.windows.net/docs/Dev/publicerat/TDE5531.pdf + https://rmtplusstoragesenseair.blob.core.windows.net/docs/Market/publicerat/TDE7318.pdf + +properties: + compatible: + const: senseair,sunrise-006-0-0007 + + reg: + maxItems: 1 + + ndry-gpios: + maxItems: 1 + description: + Phandle to the GPIO line connected to the nDRY pin. Typically active low. + + en-gpios: + maxItems: 1 + description: + Phandle to the GPIO line connected to the EN pin. Typically active high. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + co2-sensor@68 { + compatible = "senseair,sunrise-006-0-0007"; + reg = <0x68>; + }; + }; diff --git a/dts/Bindings/iio/chemical/sensirion,scd4x.yaml b/dts/Bindings/iio/chemical/sensirion,scd4x.yaml new file mode 100644 index 0000000000..798f48d052 --- /dev/null +++ b/dts/Bindings/iio/chemical/sensirion,scd4x.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/chemical/sensirion,scd4x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sensirion SCD4X carbon dioxide sensor + +maintainers: + - Roan van Dijk + +description: | + Air quality sensor capable of measuring co2 concentration, temperature + and relative humidity. + +properties: + compatible: + enum: + - sensirion,scd40 + - sensirion,scd41 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; + }; diff --git a/dts/Bindings/iio/dac/adi,ad5766.yaml b/dts/Bindings/iio/dac/adi,ad5766.yaml index d5c54813ce..a8f7720d1e 100644 --- a/dts/Bindings/iio/dac/adi,ad5766.yaml +++ b/dts/Bindings/iio/dac/adi,ad5766.yaml @@ -54,7 +54,7 @@ examples: ad5766@0 { compatible = "adi,ad5766"; - output-range-microvolts = <(-5000) 5000>; + output-range-microvolts = <(-5000000) 5000000>; reg = <0>; spi-cpol; spi-max-frequency = <1000000>; diff --git a/dts/Bindings/iio/dac/st,stm32-dac.yaml b/dts/Bindings/iio/dac/st,stm32-dac.yaml index 393f700594..6adeda4087 100644 --- a/dts/Bindings/iio/dac/st,stm32-dac.yaml +++ b/dts/Bindings/iio/dac/st,stm32-dac.yaml @@ -15,7 +15,7 @@ description: | current. maintainers: - - Fabrice Gasnier + - Fabrice Gasnier properties: compatible: diff --git a/dts/Bindings/iio/frequency/adi,adrf6780.yaml b/dts/Bindings/iio/frequency/adi,adrf6780.yaml new file mode 100644 index 0000000000..3a8ea93f4e --- /dev/null +++ b/dts/Bindings/iio/frequency/adi,adrf6780.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADRF6780 Microwave Upconverter + +maintainers: + - Antoniu Miclaus + +description: | + Wideband, microwave upconverter optimized for point to point microwave + radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. + + https://www.analog.com/en/products/adrf6780.html + +properties: + compatible: + enum: + - adi,adrf6780 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + + clocks: + description: + Definition of the external clock. + minItems: 1 + + clock-names: + items: + - const: lo_in + + clock-output-names: + maxItems: 1 + + adi,vga-buff-en: + description: + RF Variable Gain Amplifier Buffer Enable. Gain is controlled by + the voltage on the VATT pin. + type: boolean + + adi,lo-buff-en: + description: + Local Oscillator Amplifier Enable. Disable to put the part in + a power down state. + type: boolean + + adi,if-mode-en: + description: + Intermediate Frequency Mode Enable. Either IF Mode or I/Q Mode + can be enabled at a time. + type: boolean + + adi,iq-mode-en: + description: + I/Q Mode Enable. Either IF Mode or I/Q Mode can be enabled at a + time. + type: boolean + + adi,lo-x2-en: + description: + Double the Local Oscillator output frequency from the Local + Oscillator Input Frequency. Either LOx1 or LOx2 can be enabled + at a time. + type: boolean + + adi,lo-ppf-en: + description: + Local Oscillator input frequency equal to the Local Oscillator + output frequency (LO x1). Either LOx1 or LOx2 can be enabled + at a time. + type: boolean + + adi,lo-en: + description: + Enable additional cirtuitry in the LO chain. Disable to put the + part in a power down state. + type: boolean + + adi,uc-bias-en: + description: + Enable all bias circuitry thourghout the entire part. + Disable to put the part in a power down state. + type: boolean + + adi,lo-sideband: + description: + Switch to the Lower LO Sideband. By default the Upper LO + sideband is enabled. + type: boolean + + adi,vdet-out-en: + description: + VDET Output Select Enable. Expose the RF detector output to the + VDET external pin. + type: boolean + + '#clock-cells': + const: 0 + +dependencies: + adi,lo-x2-en: [ "adi,lo-en" ] + adi,lo-ppf-en: [ "adi,lo-en" ] + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + adrf6780@0 { + compatible = "adi,adrf6780"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adrf6780_lo>; + clock-names = "lo_in"; + }; + }; +... diff --git a/dts/Bindings/iio/light/liteon,ltr501.yaml b/dts/Bindings/iio/light/liteon,ltr501.yaml new file mode 100644 index 0000000000..db0407bc92 --- /dev/null +++ b/dts/Bindings/iio/light/liteon,ltr501.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/liteon,ltr501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LiteON LTR501 I2C Proximity and Light sensor + +maintainers: + - Nikita Travkin + +properties: + compatible: + enum: + - liteon,ltr501 + - liteon,ltr559 + - liteon,ltr301 + + reg: + maxItems: 1 + + vdd-supply: true + vddio-supply: true + + interrupts: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@23 { + compatible = "liteon,ltr559"; + reg = <0x23>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/dts/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml b/dts/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml index a0a1ffe017..9790f75fc6 100644 --- a/dts/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml +++ b/dts/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml @@ -17,11 +17,13 @@ properties: - asahi-kasei,ak8963 - asahi-kasei,ak09911 - asahi-kasei,ak09912 + - asahi-kasei,ak09916 - enum: - ak8975 - ak8963 - ak09911 - ak09912 + - ak09916 deprecated: true reg: @@ -43,6 +45,11 @@ properties: an optional regulator that needs to be on to provide VDD power to the sensor. + vid-supply: + description: | + an optional regulator that needs to be on to provide VID power to + the sensor. + mount-matrix: description: an optional 3x3 mounting rotation matrix. diff --git a/dts/Bindings/iio/multiplexer/io-channel-mux.yaml b/dts/Bindings/iio/multiplexer/io-channel-mux.yaml index 870b043406..611ad4444c 100644 --- a/dts/Bindings/iio/multiplexer/io-channel-mux.yaml +++ b/dts/Bindings/iio/multiplexer/io-channel-mux.yaml @@ -35,9 +35,18 @@ properties: mux-control-names: true channels: - $ref: /schemas/types.yaml#/definitions/string-array + $ref: /schemas/types.yaml#/definitions/non-unique-string-array description: - List of strings, labeling the mux controller states. + List of strings, labeling the mux controller states. An empty + string for a state means that the channel is not available. + + settle-time-us: + default: 0 + description: + Time required for analog signals to settle after muxing. + + "#io-channel-cells": + const: 1 required: - compatible diff --git a/dts/Bindings/iio/temperature/maxim,max31865.yaml b/dts/Bindings/iio/temperature/maxim,max31865.yaml new file mode 100644 index 0000000000..aafb33b165 --- /dev/null +++ b/dts/Bindings/iio/temperature/maxim,max31865.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/temperature/maxim,max31865.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX31865 Resistance Temperature Detector. + +maintainers: + - Navin Sankar Velliangiri + +description: | + https://datasheets.maximintegrated.com/en/ds/MAX31865.pdf + +properties: + compatible: + const: maxim,max31865 + + reg: + maxItems: 1 + + maxim,3-wire: + description: + Identifies the number of wires used by the RTD. Setting this property + enables 3-wire RTD connection. Else 2-wire or 4-wire RTD connection. + type: boolean + + spi-max-frequency: true + spi-cpha: true + +required: + - compatible + - reg + - spi-cpha + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + temp_sensor@0 { + compatible = "maxim,max31865"; + reg = <0>; + spi-max-frequency = <400000>; + spi-cpha; + maxim,3-wire; + }; + }; +... diff --git a/dts/Bindings/input/cap11xx.txt b/dts/Bindings/input/cap11xx.txt deleted file mode 100644 index 8c67a0b505..0000000000 --- a/dts/Bindings/input/cap11xx.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device tree bindings for Microchip CAP11xx based capacitive touch sensors - -The node for this device must be a child of a I2C controller node, as the -device communication via I2C only. - -Required properties: - - compatible: Must contain one of: - "microchip,cap1106" - "microchip,cap1126" - "microchip,cap1188" - - reg: The I2C slave address of the device. - - interrupts: Property describing the interrupt line the - device's ALERT#/CM_IRQ# pin is connected to. - The device only has one interrupt source. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - - microchip,sensor-gain: Defines the gain of the sensor circuitry. This - effectively controls the sensitivity, as a - smaller delta capacitance is required to - generate the same delta count values. - Valid values are 1, 2, 4, and 8. - By default, a gain of 1 is set. - - microchip,irq-active-high: By default the interrupt pin is active low - open drain. This property allows using the active - high push-pull output. - - linux,keycodes: Specifies an array of numeric keycode values to - be used for the channels. If this property is - omitted, KEY_A, KEY_B, etc are used as - defaults. The array must have exactly six - entries. - -Example: - -i2c_controller { - cap1106@28 { - compatible = "microchip,cap1106"; - interrupt-parent = <&gpio1>; - interrupts = <0 0>; - reg = <0x28>; - autorepeat; - microchip,sensor-gain = <2>; - - linux,keycodes = <103>, /* KEY_UP */ - <106>, /* KEY_RIGHT */ - <108>, /* KEY_DOWN */ - <105>, /* KEY_LEFT */ - <109>, /* KEY_PAGEDOWN */ - <104>; /* KEY_PAGEUP */ - - #address-cells = <1>; - #size-cells = <0>; - - usr@0 { - label = "cap11xx:green:usr0"; - reg = <0>; - }; - - usr@1 { - label = "cap11xx:green:usr1"; - reg = <1>; - }; - - alive@2 { - label = "cap11xx:green:alive"; - reg = <2>; - linux,default_trigger = "heartbeat"; - }; - }; -} diff --git a/dts/Bindings/input/cypress-sf.yaml b/dts/Bindings/input/cypress-sf.yaml new file mode 100644 index 0000000000..c0b0514662 --- /dev/null +++ b/dts/Bindings/input/cypress-sf.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cypress-sf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress StreetFighter touchkey controller + +maintainers: + - Yassine Oudjana + +allOf: + - $ref: input.yaml# + +properties: + compatible: + const: cypress,sf3155 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + avdd-supply: + description: Regulator for AVDD analog voltage + + vdd-supply: + description: Regulator for VDD digital voltage + + linux,keycodes: + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - interrupts + - avdd-supply + - vdd-supply + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchkey@28 { + compatible = "cypress,sf3155"; + reg = <0x28>; + interrupt-parent = <&msmgpio>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vreg_l6a_1p8>; + vdd-supply = <&vdd_3v2_tp>; + linux,keycodes = ; + }; + }; diff --git a/dts/Bindings/input/elan,ekth3000.yaml b/dts/Bindings/input/elan,ekth3000.yaml new file mode 100644 index 0000000000..2a9bb6ace0 --- /dev/null +++ b/dts/Bindings/input/elan,ekth3000.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/elan,ekth3000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Elantech I2C Touchpad + +maintainers: + - Dmitry Torokhov + +allOf: + - $ref: touchscreen/touchscreen.yaml# + +properties: + compatible: + const: elan,ekth3000 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: + type: boolean + description: touchpad can be used as a wakeup source + + vcc-supply: + description: a phandle for the regulator supplying 3.3V power + + elan,trackpoint: + type: boolean + description: touchpad can support a trackpoint + + elan,clickpad: + type: boolean + description: touchpad is a clickpad (the entire surface is a button) + + elan,middle-button: + type: boolean + description: touchpad has a physical middle button + + elan,x_traces: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of antennas on the x axis + + elan,y_traces: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of antennas on the y axis + + touchscreen-size-x: true + + touchscreen-size-y: true + + touchscreen-x-mm: true + + touchscreen-y-mm: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + }; diff --git a/dts/Bindings/input/elan_i2c.txt b/dts/Bindings/input/elan_i2c.txt deleted file mode 100644 index 9963247706..0000000000 --- a/dts/Bindings/input/elan_i2c.txt +++ /dev/null @@ -1,44 +0,0 @@ -Elantech I2C Touchpad - -Required properties: -- compatible: must be "elan,ekth3000". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchpad can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- vcc-supply: a phandle for the regulator supplying 3.3V power. -- elan,trackpoint: touchpad can support a trackpoint (boolean) -- elan,clickpad: touchpad is a clickpad (the entire surface is a button) -- elan,middle-button: touchpad has a physical middle button -- elan,x_traces: number of antennas on the x axis -- elan,y_traces: number of antennas on the y axis -- some generic touchscreen properties [2]: - * touchscreen-size-x - * touchscreen-size-y - * touchscreen-x-mm - * touchscreen-y-mm - - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt - -Example: - &i2c1 { - /* ... */ - - touchpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - /* ... */ - }; diff --git a/dts/Bindings/input/microchip,cap11xx.yaml b/dts/Bindings/input/microchip,cap11xx.yaml new file mode 100644 index 0000000000..d5d6bced31 --- /dev/null +++ b/dts/Bindings/input/microchip,cap11xx.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/input/microchip,cap11xx.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree bindings for Microchip CAP11xx based capacitive touch sensors + +description: | + The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive + touch controllers and LED drivers. The device communication via I2C only. + +maintainers: + - Rob Herring + +properties: + compatible: + enum: + - microchip,cap1106 + - microchip,cap1126 + - microchip,cap1188 + - microchip,cap1206 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + description: | + Property describing the interrupt line the + device's ALERT#/CM_IRQ# pin is connected to. + The device only has one interrupt source. + + autorepeat: + description: | + Enables the Linux input system's autorepeat feature on the input device. + + linux,keycodes: + minItems: 6 + maxItems: 6 + description: | + Specifies an array of numeric keycode values to + be used for the channels. If this property is + omitted, KEY_A, KEY_B, etc are used as defaults. + The array must have exactly six entries. + + microchip,sensor-gain: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: [1, 2, 4, 8] + description: | + Defines the gain of the sensor circuitry. This + effectively controls the sensitivity, as a + smaller delta capacitance is required to + generate the same delta count values. + + microchip,irq-active-high: + type: boolean + description: | + By default the interrupt pin is active low + open drain. This property allows using the active + high push-pull output. + +patternProperties: + "^led@[0-7]$": + type: object + description: CAP11xx LEDs + $ref: /schemas/leds/common.yaml# + + properties: + reg: + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + label: true + + linux,default-trigger: true + + default-state: true + + required: + - reg + + additionalProperties: false + +allOf: + - $ref: input.yaml + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1106 + then: + patternProperties: + "^led@[0-7]$": false + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cap1188@28 { + compatible = "microchip,cap1188"; + interrupt-parent = <&gpio1>; + interrupts = <0 0>; + reg = <0x28>; + autorepeat; + microchip,sensor-gain = <2>; + + linux,keycodes = <103>, /* KEY_UP */ + <106>, /* KEY_RIGHT */ + <108>, /* KEY_DOWN */ + <105>, /* KEY_LEFT */ + <109>, /* KEY_PAGEDOWN */ + <104>; /* KEY_PAGEUP */ + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + label = "cap11xx:green:usr0"; + reg = <0>; + }; + + led@1 { + label = "cap11xx:green:usr1"; + reg = <1>; + }; + + led@2 { + label = "cap11xx:green:alive"; + reg = <2>; + linux,default-trigger = "heartbeat"; + }; + }; + }; diff --git a/dts/Bindings/input/touchscreen/silead,gsl1680.yaml b/dts/Bindings/input/touchscreen/silead,gsl1680.yaml new file mode 100644 index 0000000000..eec6f7f6f0 --- /dev/null +++ b/dts/Bindings/input/touchscreen/silead,gsl1680.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/silead,gsl1680.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silead GSL1680 Touchscreen Controller Device Tree Bindings + +maintainers: + - Dmitry Torokhov + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - silead,gsl1680 + - silead,gsl1688 + - silead,gsl3670 + - silead,gsl3675 + - silead,gsl3692 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-gpios: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: > + File basename for board specific firmware + + silead,max-fingers: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + description: > + Maximum number of fingers the touchscreen can detect + + silead,home-button: + type: boolean + description: > + Does the device have a capacitive home-button build into the + touchscreen? + + avdd-supply: + description: > + Regulator phandle for controller AVDD + + vddio-supply: + description: > + Regulator phandle for controller VDDIO + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - power-gpios + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + silead,max-fingers = <5>; + }; + }; + +... diff --git a/dts/Bindings/input/touchscreen/silead_gsl1680.txt b/dts/Bindings/input/touchscreen/silead_gsl1680.txt deleted file mode 100644 index d67e558e5a..0000000000 --- a/dts/Bindings/input/touchscreen/silead_gsl1680.txt +++ /dev/null @@ -1,44 +0,0 @@ -* GSL 1680 touchscreen controller - -Required properties: -- compatible : Must be one of the following, depending on the model: - "silead,gsl1680" - "silead,gsl1688" - "silead,gsl3670" - "silead,gsl3675" - "silead,gsl3692" -- reg : I2C slave address of the chip (0x40) -- interrupts : interrupt specification for the gsl1680 interrupt -- power-gpios : Specification for the pin connected to the gsl1680's - shutdown input. This needs to be driven high to take the - gsl1680 out of its low power state -- touchscreen-size-x : See touchscreen.txt -- touchscreen-size-y : See touchscreen.txt - -Optional properties: -- firmware-name : File basename (string) for board specific firmware -- touchscreen-inverted-x : See touchscreen.txt -- touchscreen-inverted-y : See touchscreen.txt -- touchscreen-swapped-x-y : See touchscreen.txt -- silead,max-fingers : maximum number of fingers the touchscreen can detect -- silead,home-button : Boolean, set to true on devices which have a - capacitive home-button build into the touchscreen -- vddio-supply : regulator phandle for controller VDDIO -- avdd-supply : regulator phandle for controller AVDD - -Example: - -i2c@00000000 { - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - silead,max-fingers = <5>; - }; -}; diff --git a/dts/Bindings/input/touchscreen/ti,am3359-tsc.yaml b/dts/Bindings/input/touchscreen/ti,am3359-tsc.yaml new file mode 100644 index 0000000000..e44cc65abc --- /dev/null +++ b/dts/Bindings/input/touchscreen/ti,am3359-tsc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM3359 Touchscreen controller + +maintainers: + - Miquel Raynal + +properties: + compatible: + const: ti,am3359-tsc + + ti,wires: + description: Wires refer to application modes i.e. 4/5/8 wire touchscreen + support on the platform. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [4, 5, 8] + + ti,x-plate-resistance: + description: X plate resistance + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,coordinate-readouts: + description: The sequencer supports a total of 16 programmable steps. Each + step is used to read a single coordinate. A single readout is enough but + multiple reads can increase the quality. A value of 5 means, 5 reads for + X, 5 for Y and 2 for Z (always). This utilises 12 of the 16 software steps + available. The remaining 4 can be used by the ADC. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 6 + + ti,wire-config: + description: Different boards could have a different order for connecting + wires on touchscreen. We need to provide an 8-bit number where the + first four bits represent the analog lines and the next 4 bits represent + positive/negative terminal on that input line. Notations to represent the + input lines and terminals respectively are as follows, AIN0 = 0, AIN1 = 1 + and so on until AIN7 = 7. XP = 0, XN = 1, YP = 2, YN = 3. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 8 + + ti,charge-delay: + description: Length of touch screen charge delay step in terms of ADC clock + cycles. Charge delay value should be large in order to avoid false pen-up + events. This value effects the overall sampling speed, hence need to be + kept as low as possible, while avoiding false pen-up event. Start from a + lower value, say 0x400, and increase value until false pen-up events are + avoided. The pen-up detection happens immediately after the charge step, + so this does in fact function as a hardware knob for adjusting the amount + of "settling time". + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - ti,wires + - ti,x-plate-resistance + - ti,coordinate-readouts + - ti,wire-config + +additionalProperties: false + +examples: + - | + tsc { + compatible = "ti,am3359-tsc"; + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + ti,charge-delay = <0x400>; + }; diff --git a/dts/Bindings/input/touchscreen/ti-tsc-adc.txt b/dts/Bindings/input/touchscreen/ti-tsc-adc.txt deleted file mode 100644 index aad5e34965..0000000000 --- a/dts/Bindings/input/touchscreen/ti-tsc-adc.txt +++ /dev/null @@ -1,91 +0,0 @@ -* TI - TSC ADC (Touschscreen and analog digital converter) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Required properties: -- mfd - compatible: Should be - "ti,am3359-tscadc" for AM335x/AM437x SoCs - "ti,am654-tscadc", "ti,am3359-tscadc" for AM654 SoCs -- child "tsc" - compatible: Should be "ti,am3359-tsc". - ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen - support on the platform. - ti,x-plate-resistance: X plate resistance - ti,coordinate-readouts: The sequencer supports a total of 16 - programmable steps each step is used to - read a single coordinate. A single - readout is enough but multiple reads can - increase the quality. - A value of 5 means, 5 reads for X, 5 for - Y and 2 for Z (always). This utilises 12 - of the 16 software steps available. The - remaining 4 can be used by the ADC. - ti,wire-config: Different boards could have a different order for - connecting wires on touchscreen. We need to provide an - 8 bit number where in the 1st four bits represent the - analog lines and the next 4 bits represent positive/ - negative terminal on that input line. Notations to - represent the input lines and terminals resoectively - is as follows: - AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. - XP = 0, XN = 1, YP = 2, YN = 3. -- child "adc" - compatible: Should be - "ti,am3359-adc" for AM335x/AM437x SoCs - "ti,am654-adc", "ti,am3359-adc" for AM654 SoCs - ti,adc-channels: List of analog inputs available for ADC. - AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7. - -Optional properties: -- child "tsc" - ti,charge-delay: Length of touch screen charge delay step in terms of - ADC clock cycles. Charge delay value should be large - in order to avoid false pen-up events. This value - effects the overall sampling speed, hence need to be - kept as low as possible, while avoiding false pen-up - event. Start from a lower value, say 0x400, and - increase value until false pen-up events are avoided. - The pen-up detection happens immediately after the - charge step, so this does in fact function as a - hardware knob for adjusting the amount of "settling - time". - -- child "adc" - ti,chan-step-opendelay: List of open delays for each channel of - ADC in the order of ti,adc-channels. The - value corresponds to the number of ADC - clock cycles to wait after applying the - step configuration registers and before - sending the start of ADC conversion. - Maximum value is 0x3FFFF. - ti,chan-step-sampledelay: List of sample delays for each channel - of ADC in the order of ti,adc-channels. - The value corresponds to the number of - ADC clock cycles to sample (to hold - start of conversion high). - Maximum value is 0xFF. - ti,chan-step-avg: Number of averages to be performed for each - channel of ADC. If average is 16 then input - is sampled 16 times and averaged to get more - accurate value. This increases the time taken - by ADC to generate a sample. Valid range is 0 - average to 16 averages. Maximum value is 16. - -Example: - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordiante-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; - ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; - ti,chan-step-avg = <16 2 4 8>; - }; - } diff --git a/dts/Bindings/interrupt-controller/microchip,eic.yaml b/dts/Bindings/interrupt-controller/microchip,eic.yaml new file mode 100644 index 0000000000..50003880ee --- /dev/null +++ b/dts/Bindings/interrupt-controller/microchip,eic.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip External Interrupt Controller + +maintainers: + - Claudiu Beznea + +description: + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides + support for handling up to 2 external interrupt lines. + +properties: + compatible: + enum: + - microchip,sama7g5-eic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the input IRQ number (between 0 and 1), the second cell + is the trigger type as defined in interrupt.txt present in this directory. + + interrupts: + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. They + should be specified sequentially from output 0 to output 1. + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0x100>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + }; + +... diff --git a/dts/Bindings/interrupt-controller/msi-controller.yaml b/dts/Bindings/interrupt-controller/msi-controller.yaml new file mode 100644 index 0000000000..449d6067ec --- /dev/null +++ b/dts/Bindings/interrupt-controller/msi-controller.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSI controller + +maintainers: + - Marc Zyngier + +description: | + An MSI controller signals interrupts to a CPU when a write is made + to an MMIO address by some master. An MSI controller may feature a + number of doorbells. + +properties: + "#msi-cells": + description: | + The number of cells in an msi-specifier, required if not zero. + + Typically this will encode information related to sideband data, + and will not encode doorbells or payloads as these can be + configured dynamically. + + The meaning of the msi-specifier is defined by the device tree + binding of the specific MSI controller. + enum: [0, 1] + + msi-controller: + description: + Identifies the node as an MSI controller. + $ref: /schemas/types.yaml#/definitions/flag + + msi-ranges: + description: + A list of tuples, where "phandle" is the + parent interrupt controller, "intspec" is the starting/base + interrupt specifier and "span" is the size of the + range. Multiple ranges can be provided. + $ref: /schemas/types.yaml#/definitions/phandle-array + +dependencies: + "#msi-cells": [ msi-controller ] + +additionalProperties: true diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.yaml b/dts/Bindings/interrupt-controller/renesas,irqc.yaml index abb22db3bb..79d0358e2f 100644 --- a/dts/Bindings/interrupt-controller/renesas,irqc.yaml +++ b/dts/Bindings/interrupt-controller/renesas,irqc.yaml @@ -27,6 +27,7 @@ properties: - renesas,intc-ex-r8a774a1 # RZ/G2M - renesas,intc-ex-r8a774b1 # RZ/G2N - renesas,intc-ex-r8a774c0 # RZ/G2E + - renesas,intc-ex-r8a774e1 # RZ/G2H - renesas,intc-ex-r8a7795 # R-Car H3 - renesas,intc-ex-r8a7796 # R-Car M3-W - renesas,intc-ex-r8a77961 # R-Car M3-W+ diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml index 6d3e68eb2e..d19c881b4a 100644 --- a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml +++ b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 External Interrupt Controller Device Tree Bindings maintainers: - - Alexandre Torgue - - Ludovic Barre + - Alexandre Torgue + - Ludovic Barre properties: compatible: diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml index 03f2b2d4db..f66a3effba 100644 --- a/dts/Bindings/iommu/arm,smmu.yaml +++ b/dts/Bindings/iommu/arm,smmu.yaml @@ -33,10 +33,12 @@ properties: - description: Qcom SoCs implementing "arm,mmu-500" items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 + - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 diff --git a/dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml b/dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml index 02c69a95c3..ce0c715205 100644 --- a/dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml +++ b/dts/Bindings/iommu/renesas,ipmmu-vmsa.yaml @@ -43,6 +43,7 @@ properties: - renesas,ipmmu-r8a77980 # R-Car V3H - renesas,ipmmu-r8a77990 # R-Car E3 - renesas,ipmmu-r8a77995 # R-Car D3 + - renesas,ipmmu-r8a779a0 # R-Car V3U reg: maxItems: 1 diff --git a/dts/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/dts/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt index 028268fd99..c9902fd4b3 100644 --- a/dts/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ b/dts/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt @@ -9,6 +9,7 @@ Required properties: - compatible : should be one of "aspeed,ast2400-ibt-bmc" "aspeed,ast2500-ibt-bmc" + "aspeed,ast2600-ibt-bmc" - reg: physical address and size of the registers Optional properties: diff --git a/dts/Bindings/ipmi/ipmi-ipmb.yaml b/dts/Bindings/ipmi/ipmi-ipmb.yaml new file mode 100644 index 0000000000..93d8f8e88c --- /dev/null +++ b/dts/Bindings/ipmi/ipmi-ipmb.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ipmi/ipmi-ipmb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IPMI IPMB device bindings + +description: IPMI IPMB device bindings + +maintainers: + - Corey Minyard + +properties: + compatible: + enum: + - ipmi-ipmb + + device_type: + items: + - const: "ipmi" + + reg: + maxItems: 1 + + bmcaddr: + $ref: /schemas/types.yaml#/definitions/uint8 + description: The address of the BMC on the IPMB bus. Defaults to 0x20. + + retry-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between retries of sends, in milliseconds. Defaults to 250. + + max-retries: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of retries before a failure is declared. Defaults to 1. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ipmi-ipmb@40 { + compatible = "ipmi-ipmb"; + device_type = "ipmi"; + reg = <0x40>; + bmcaddr = /bits/ 8 <0x20>; + retry-time = <250>; + max-retries = <1>; + }; + }; diff --git a/dts/Bindings/leds/register-bit-led.txt b/dts/Bindings/leds/register-bit-led.txt deleted file mode 100644 index c7af6f70a9..0000000000 --- a/dts/Bindings/leds/register-bit-led.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device Tree Bindings for Register Bit LEDs - -Register bit leds are used with syscon multifunctional devices -where single bits in a certain register can turn on/off a -single LED. The register bit LEDs appear as children to the -syscon device, with the proper compatible string. For the -syscon bindings see: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Each LED is represented as a sub-node of the syscon device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: - -Required properties: -- compatible : must be "register-bit-led" -- offset : register offset to the register controlling this LED -- mask : bit mask for the bit controlling this LED in the register - typically 0x01, 0x02, 0x04 ... - -Optional properties: -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon"; - reg = <0x10000000 0x1000>; - - led@8.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; -}; diff --git a/dts/Bindings/leds/register-bit-led.yaml b/dts/Bindings/leds/register-bit-led.yaml new file mode 100644 index 0000000000..79b8fc0f9d --- /dev/null +++ b/dts/Bindings/leds/register-bit-led.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/register-bit-led.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Bindings for Register Bit LEDs + +maintainers: + - Linus Walleij + +description: |+ + Register bit leds are used with syscon multifunctional devices where single + bits in a certain register can turn on/off a single LED. The register bit LEDs + appear as children to the syscon device, with the proper compatible string. + For the syscon bindings see: + Documentation/devicetree/bindings/mfd/syscon.yaml + +allOf: + - $ref: /schemas/leds/common.yaml# + +properties: + $nodename: + description: + The unit-address is in the form of @, + pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$' + + compatible: + const: register-bit-led + + reg: + description: + The register address and size + maxItems: 1 + + mask: + description: + bit mask for the bit controlling this LED in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, + 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000, + 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000, + 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ] + + offset: + description: + register offset to the register controlling this LED + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + +required: + - compatible + - mask + - reg + +unevaluatedProperties: false + +examples: + - | + + syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon"; + reg = <0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x1000>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + default-state = "off"; + }; + }; +... diff --git a/dts/Bindings/mailbox/apple,mailbox.yaml b/dts/Bindings/mailbox/apple,mailbox.yaml new file mode 100644 index 0000000000..2c1704b34e --- /dev/null +++ b/dts/Bindings/mailbox/apple,mailbox.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Mailbox Controller + +maintainers: + - Hector Martin + - Sven Peter + +description: + The Apple mailbox consists of two FIFOs used to exchange 64+32 bit + messages between the main CPU and a co-processor. Multiple instances + of this mailbox can be found on Apple SoCs. + One of the two FIFOs is used to send data to a co-processor while the other + FIFO is used for the other direction. + Various clients implement different IPC protocols based on these simple + messages and shared memory buffers. + +properties: + compatible: + oneOf: + - description: + ASC mailboxes are the most common variant found on the M1 used + for example for the display controller, the system management + controller and the NVMe coprocessor. + items: + - const: apple,t8103-asc-mailbox + + - description: + M3 mailboxes are an older variant with a slightly different MMIO + interface still found on the M1. It is used for the Thunderbolt + co-processors. + items: + - const: apple,t8103-m3-mailbox + + reg: + maxItems: 1 + + interrupts: + items: + - description: send fifo is empty interrupt + - description: send fifo is not empty interrupt + - description: receive fifo is empty interrupt + - description: receive fifo is not empty interrupt + + interrupt-names: + items: + - const: send-empty + - const: send-not-empty + - const: recv-empty + - const: recv-not-empty + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + mailbox@77408000 { + compatible = "apple,t8103-asc-mailbox"; + reg = <0x77408000 0x4000>; + interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; diff --git a/dts/Bindings/mailbox/fsl,mu.yaml b/dts/Bindings/mailbox/fsl,mu.yaml index 675ad9de15..a337bcd80c 100644 --- a/dts/Bindings/mailbox/fsl,mu.yaml +++ b/dts/Bindings/mailbox/fsl,mu.yaml @@ -28,6 +28,7 @@ properties: - const: fsl,imx7ulp-mu - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu + - const: fsl,imx8ulp-mu-s4 - items: - enum: - fsl,imx7s-mu diff --git a/dts/Bindings/mailbox/mtk-gce.txt b/dts/Bindings/mailbox/mtk-gce.txt index 89a59b9c81..98fe37e8b1 100644 --- a/dts/Bindings/mailbox/mtk-gce.txt +++ b/dts/Bindings/mailbox/mtk-gce.txt @@ -40,8 +40,8 @@ Optional properties for a client mutex node: defined in 'dt-bindings/gce/-gce.h'. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', -'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h', -'dt-binding/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. +'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8192-gce.h', +'dt-bindings/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml index 6395281b0c..01e9d9155c 100644 --- a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -11,7 +11,7 @@ description: platforms. maintainers: - - Sivaprakash Murugesan + - Jassi Brar properties: compatible: @@ -24,6 +24,7 @@ properties: - qcom,msm8994-apcs-kpss-global - qcom,msm8996-apcs-hmss-global - qcom,msm8998-apcs-hmss-global + - qcom,qcm2290-apcs-hmss-global - qcom,qcs404-apcs-apps-global - qcom,sc7180-apss-shared - qcom,sc8180x-apss-shared diff --git a/dts/Bindings/mailbox/st,stm32-ipcc.yaml b/dts/Bindings/mailbox/st,stm32-ipcc.yaml index b15da9ba90..8eb4bf52ea 100644 --- a/dts/Bindings/mailbox/st,stm32-ipcc.yaml +++ b/dts/Bindings/mailbox/st,stm32-ipcc.yaml @@ -13,8 +13,8 @@ description: channels (N) can be read from a dedicated register. maintainers: - - Fabien Dessenne - - Arnaud Pouliquen + - Fabien Dessenne + - Arnaud Pouliquen properties: compatible: diff --git a/dts/Bindings/media/i2c/adv7604.yaml b/dts/Bindings/media/i2c/adv7604.yaml index de15cebe29..c19d8391e2 100644 --- a/dts/Bindings/media/i2c/adv7604.yaml +++ b/dts/Bindings/media/i2c/adv7604.yaml @@ -4,23 +4,24 @@ $id: http://devicetree.org/schemas/media/i2c/adv7604.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices ADV7604/11/12 video decoder with HDMI receiver +title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver maintainers: - Hans Verkuil description: - The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated - HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog - input, and the ADV7611 has one HDMI input and no analog input. The 7612 is - similar to the 7611 but has 2 HDMI inputs. + The ADV7604 and ADV7610/11/12 are multiformat video decoders with + an integrated HDMI receiver. The ADV7604 has four multiplexed HDMI inputs + and one analog input, and the ADV7610/11 have one HDMI input and no analog + input. The ADV7612 is similar to the ADV7610/11 but has 2 HDMI inputs. - These device tree bindings support the ADV7611/12 only at the moment. + These device tree bindings support the ADV7610/11/12 only at the moment. properties: compatible: items: - enum: + - adi,adv7610 - adi,adv7611 - adi,adv7612 diff --git a/dts/Bindings/media/i2c/aptina,mt9p031.yaml b/dts/Bindings/media/i2c/aptina,mt9p031.yaml new file mode 100644 index 0000000000..c2ba78116d --- /dev/null +++ b/dts/Bindings/media/i2c/aptina,mt9p031.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/aptina,mt9p031.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor + +maintainers: + - Laurent Pinchart + +description: | + The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor + with an active array size of 2592H x 1944V. It is programmable through a + simple two-wire serial interface. + +properties: + compatible: + enum: + - aptina,mt9p031 + - aptina,mt9p031m + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + vdd-supply: + description: Digital supply voltage, 1.8 V + + vdd_io-supply: + description: I/O supply voltage, 1.8 or 2.8 V + + vaa-supply: + description: Analog supply voltage, 2.8 V + + reset-gpios: + maxItems: 1 + description: Chip reset GPIO + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + input-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 6000000 + maximum: 96000000 + description: Input clock frequency + + pixel-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 96000000 + description: Target pixel clock frequency + + pclk-sample: + default: 0 + + required: + - input-clock-frequency + - pixel-clock-frequency + +required: + - compatible + - reg + - clocks + - vdd-supply + - vdd_io-supply + - vaa-supply + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt9p031@5d { + compatible = "aptina,mt9p031"; + reg = <0x5d>; + reset-gpios = <&gpio_sensor 0 0>; + + clocks = <&sensor_clk>; + + vdd-supply = <®_vdd>; + vdd_io-supply = <®_vdd_io>; + vaa-supply = <®_vaa>; + + port { + mt9p031_1: endpoint { + input-clock-frequency = <6000000>; + pixel-clock-frequency = <96000000>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/media/i2c/hynix,hi846.yaml b/dts/Bindings/media/i2c/hynix,hi846.yaml new file mode 100644 index 0000000000..85a8877c2f --- /dev/null +++ b/dts/Bindings/media/i2c/hynix,hi846.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/hynix,hi846.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SK Hynix Hi-846 1/4" 8M Pixel MIPI CSI-2 sensor + +maintainers: + - Martin Kepplinger + +description: |- + The Hi-846 is a raw image sensor with an MIPI CSI-2 image data + interface and CCI (I2C compatible) control bus. The output format + is raw Bayer. + +properties: + compatible: + const: hynix,hi846 + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the mclk clock. + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + reset-gpios: + description: Reference to the GPIO connected to the RESETB pin. Active low. + maxItems: 1 + + shutdown-gpios: + description: Reference to the GPIO connected to the XSHUTDOWN pin. Active low. + maxItems: 1 + + vddio-supply: + description: Definition of the regulator used for the VDDIO power supply. + + vdda-supply: + description: Definition of the regulator used for the VDDA power supply. + + vddd-supply: + description: Definition of the regulator used for the VDDD power supply. + + port: + $ref: /schemas/graph.yaml#/properties/port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + oneOf: + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 1 + - const: 2 + + required: + - data-lanes + +required: + - compatible + - reg + - clocks + - assigned-clocks + - assigned-clock-rates + - vddio-supply + - vdda-supply + - vddd-supply + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hi846: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk 0>; + assigned-clocks = <&clk 0>; + assigned-clock-rates = <25000000>; + vdda-supply = <®_camera_vdda>; + vddd-supply = <®_camera_vddd>; + vddio-supply = <®_camera_vddio>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + + port { + camera_out: endpoint { + remote-endpoint = <&csi1_ep1>; + link-frequencies = /bits/ 64 + <80000000 200000000>; + data-lanes = <1 2>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/media/i2c/mt9p031.txt b/dts/Bindings/media/i2c/mt9p031.txt deleted file mode 100644 index cb60443ff7..0000000000 --- a/dts/Bindings/media/i2c/mt9p031.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor - -The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a simple -two-wire serial interface. - -Required Properties: -- compatible: value should be either one among the following - (a) "aptina,mt9p031" for mt9p031 sensor - (b) "aptina,mt9p031m" for mt9p031m sensor - -- input-clock-frequency: Input clock frequency. - -- pixel-clock-frequency: Pixel clock frequency. - -Optional Properties: -- reset-gpios: Chip reset GPIO - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - mt9p031@5d { - compatible = "aptina,mt9p031"; - reg = <0x5d>; - reset-gpios = <&gpio3 30 0>; - - port { - mt9p031_1: endpoint { - input-clock-frequency = <6000000>; - pixel-clock-frequency = <96000000>; - }; - }; - }; - ... - }; diff --git a/dts/Bindings/media/i2c/ov5640.txt b/dts/Bindings/media/i2c/ov5640.txt deleted file mode 100644 index c97c2f2da1..0000000000 --- a/dts/Bindings/media/i2c/ov5640.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Omnivision OV5640 MIPI CSI-2 / parallel sensor - -Required Properties: -- compatible: should be "ovti,ov5640" -- clocks: reference to the xclk input clock. -- clock-names: should be "xclk". -- DOVDD-supply: Digital I/O voltage supply, 1.8 volts -- AVDD-supply: Analog voltage supply, 2.8 volts -- DVDD-supply: Digital core voltage supply, 1.5 volts - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the reset pin, if any. - This is an active low signal to the OV5640. -- powerdown-gpios: reference to the GPIO connected to the powerdown pin, - if any. This is an active high signal to the OV5640. -- rotation: as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt, - valid values are 0 (sensor mounted upright) and 180 (sensor - mounted upside down). - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -OV5640 can be connected to a MIPI CSI-2 bus or a parallel bus endpoint. - -Endpoint node required properties for CSI-2 connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- clock-lanes: should be set to <0> (clock lane on hardware lane 0) -- data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported) - -Endpoint node required properties for parallel connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- bus-width: shall be set to <8> for 8 bits parallel bus - or <10> for 10 bits parallel bus -- data-shift: shall be set to <2> for 8 bits parallel bus - (lines 9:2 are used) or <0> for 10 bits parallel bus -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. - -Examples: - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v */ - DVDD-supply = <&vgen2_reg>; /* 1.5v */ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - rotation = <180>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_from_ov5640>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - - port { - /* Parallel bus endpoint */ - ov5640_to_parallel: endpoint { - remote-endpoint = <¶llel_from_ov5640>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; -}; diff --git a/dts/Bindings/media/i2c/ovti,ov5640.yaml b/dts/Bindings/media/i2c/ovti,ov5640.yaml new file mode 100644 index 0000000000..540fd69ac3 --- /dev/null +++ b/dts/Bindings/media/i2c/ovti,ov5640.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV5640 Image Sensor Device Tree Bindings + +maintainers: + - Steve Longerbeam + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov5640 + + reg: + maxItems: 1 + + clocks: + description: XCLK Input Clock + + clock-names: + const: xclk + + AVDD-supply: + description: Analog voltage supply, 2.8 volts + + DVDD-supply: + description: Digital core voltage supply, 1.5 volts + + DOVDD-supply: + description: Digital I/O voltage supply, 1.8 volts + + powerdown-gpios: + maxItems: 1 + description: > + Reference to the GPIO connected to the powerdown pin, if any. + + reset-gpios: + maxItems: 1 + description: > + Reference to the GPIO connected to the reset pin, if any. + + rotation: + enum: + - 0 + - 180 + + port: + description: Digital Output Port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + const: 0 + + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + bus-width: + enum: [8, 10] + + data-shift: + enum: [0, 2] + +required: + - compatible + - reg + - clocks + - clock-names + - AVDD-supply + - DVDD-supply + - DOVDD-supply + - port + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v */ + powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + rotation = <180>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_from_ov5640>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v */ + + port { + /* Parallel bus endpoint */ + ov5640_to_parallel: endpoint { + remote-endpoint = <¶llel_from_ov5640>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/media/mediatek-vcodec.txt b/dts/Bindings/media/mediatek-vcodec.txt index ad1321e5a2..665a950870 100644 --- a/dts/Bindings/media/mediatek-vcodec.txt +++ b/dts/Bindings/media/mediatek-vcodec.txt @@ -10,6 +10,8 @@ Required properties: "mediatek,mt8183-vcodec-enc" for MT8183 encoder. "mediatek,mt8173-vcodec-dec" for MT8173 decoder. "mediatek,mt8192-vcodec-enc" for MT8192 encoder. + "mediatek,mt8183-vcodec-dec" for MT8183 decoder. + "mediatek,mt8195-vcodec-enc" for MT8195 encoder. - reg : Physical base address of the video codec registers and length of memory mapped region. - interrupts : interrupt number to the cpu. diff --git a/dts/Bindings/media/qcom,sc7280-venus.yaml b/dts/Bindings/media/qcom,sc7280-venus.yaml new file mode 100644 index 0000000000..e2874683b4 --- /dev/null +++ b/dts/Bindings/media/qcom,sc7280-venus.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Venus video encode and decode accelerators + +maintainers: + - Stanimir Varbanov + +description: | + The Venus Iris2 IP is a video encode and decode accelerator present + on Qualcomm platforms + +properties: + compatible: + const: qcom,sc7280-venus + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + minItems: 2 + maxItems: 3 + + power-domain-names: + minItems: 2 + items: + - const: venus + - const: vcodec0 + - const: cx + + clocks: + maxItems: 5 + + clock-names: + items: + - const: core + - const: bus + - const: iface + - const: vcodec_core + - const: vcodec_bus + + iommus: + maxItems: 2 + + memory-region: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + video-decoder: + type: object + + properties: + compatible: + const: venus-decoder + + required: + - compatible + + additionalProperties: false + + video-encoder: + type: object + + properties: + compatible: + const: venus-encoder + + required: + - compatible + + additionalProperties: false + + video-firmware: + type: object + + description: | + Firmware subnode is needed when the platform does not + have TrustZone. + + properties: + iommus: + maxItems: 1 + + required: + - iommus + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + - clocks + - clock-names + - iommus + - memory-region + - video-decoder + - video-encoder + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + venus: video-codec@aa00000 { + compatible = "qcom,sc7280-venus"; + reg = <0x0aa00000 0xd0600>; + interrupts = ; + + clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_MVS0_CORE_CLK>, + <&videocc VIDEO_CC_MVS0_AXI_CLK>; + clock-names = "core", "bus", "iface", + "vcodec_core", "vcodec_bus"; + + power-domains = <&videocc MVSC_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC7280_CX>; + power-domain-names = "venus", "vcodec0", "cx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cpu-cfg", "video-mem"; + + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x2184 0x20>; + + memory-region = <&video_mem>; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + + video-firmware { + iommus = <&apps_smmu 0x21a2 0x0>; + }; + }; diff --git a/dts/Bindings/media/qcom,sdm660-venus.yaml b/dts/Bindings/media/qcom,sdm660-venus.yaml new file mode 100644 index 0000000000..33da7d3cfd --- /dev/null +++ b/dts/Bindings/media/qcom,sdm660-venus.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Venus video encode and decode accelerators + +maintainers: + - Stanimir Varbanov + - AngeloGioacchino Del Regno + +description: | + The Venus IP is a video encode and decode accelerator present + on Qualcomm platforms + +properties: + compatible: + const: qcom,sdm660-venus + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: bus_throttle + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + interrupts: + maxItems: 1 + + iommus: + maxItems: 20 + + memory-region: + maxItems: 1 + + power-domains: + maxItems: 1 + + video-decoder: + type: object + + properties: + compatible: + const: venus-decoder + + clocks: + maxItems: 1 + + clock-names: + items: + - const: vcodec0_core + + power-domains: + maxItems: 1 + + required: + - compatible + - clocks + - clock-names + - power-domains + + additionalProperties: false + + video-encoder: + type: object + + properties: + compatible: + const: venus-encoder + + clocks: + maxItems: 1 + + clock-names: + items: + - const: vcodec0_core + + power-domains: + maxItems: 1 + + required: + - compatible + - clocks + - clock-names + - power-domains + + additionalProperties: false + + video-firmware: + type: object + + description: | + Firmware subnode is needed when the platform does not + have TrustZone. + + properties: + iommus: + maxItems: 1 + + required: + - iommus + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - iommus + - memory-region + - power-domains + - video-decoder + - video-encoder + +additionalProperties: false + +examples: + - | + #include + #include + + video-codec@cc00000 { + compatible = "qcom,sdm660-venus"; + reg = <0x0cc00000 0xff000>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc THROTTLE_VIDEO_AXI_CLK>; + clock-names = "core", "iface", "bus", "bus_throttle"; + interconnects = <&gnoc 0 &mnoc 13>, + <&mnoc 4 &bimc 5>; + interconnect-names = "cpu-cfg", "video-mem"; + interrupts = ; + iommus = <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + memory-region = <&venus_region>; + power-domains = <&mmcc VENUS_GDSC>; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "vcodec0_core"; + power-domains = <&mmcc VENUS_CORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "vcodec0_core"; + power-domains = <&mmcc VENUS_CORE0_GDSC>; + }; + }; diff --git a/dts/Bindings/media/renesas,csi2.yaml b/dts/Bindings/media/renesas,csi2.yaml index 23703b767f..e6a0367210 100644 --- a/dts/Bindings/media/renesas,csi2.yaml +++ b/dts/Bindings/media/renesas,csi2.yaml @@ -30,6 +30,7 @@ properties: - renesas,r8a77970-csi2 # R-Car V3M - renesas,r8a77980-csi2 # R-Car V3H - renesas,r8a77990-csi2 # R-Car E3 + - renesas,r8a779a0-csi2 # R-Car V3U reg: maxItems: 1 diff --git a/dts/Bindings/media/renesas,imr.txt b/dts/Bindings/media/renesas,imr.txt deleted file mode 100644 index b0614153ed..0000000000 --- a/dts/Bindings/media/renesas,imr.txt +++ /dev/null @@ -1,31 +0,0 @@ -Renesas R-Car Image Renderer (Distortion Correction Engine) ------------------------------------------------------------ - -The image renderer, or the distortion correction engine, is a drawing processor -with a simple instruction system capable of referencing video capture data or -data in an external memory as 2D texture data and performing texture mapping -and drawing with respect to any shape that is split into triangular objects. - -Required properties: - -- compatible: "renesas,-imr-lx4", "renesas,imr-lx4" as a fallback for - the image renderer light extended 4 (IMR-LX4) found in the R-Car gen3 SoCs, - where the examples with are: - - "renesas,r8a7795-imr-lx4" for R-Car H3, - - "renesas,r8a7796-imr-lx4" for R-Car M3-W. -- reg: offset and length of the register block; -- interrupts: single interrupt specifier; -- clocks: single clock phandle/specifier pair; -- power-domains: power domain phandle/specifier pair; -- resets: reset phandle/specifier pair. - -Example: - - imr-lx4@fe860000 { - compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 823>; - }; diff --git a/dts/Bindings/media/renesas,imr.yaml b/dts/Bindings/media/renesas,imr.yaml new file mode 100644 index 0000000000..512f57417f --- /dev/null +++ b/dts/Bindings/media/renesas,imr.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,imr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Image Renderer (Distortion Correction Engine) + +maintainers: + - Sergei Shtylyov + +description: | + The image renderer, or the distortion correction engine, is a drawing + processor with a simple instruction system capable of referencing video + capture data or data in an external memory as 2D texture data and performing + texture mapping and drawing with respect to any shape that is split into + triangular objects. + + The image renderer light extended 4 (IMR-LX4) is found in R-Car Gen3 SoCs. + +properties: + compatible: + items: + - enum: + - renesas,r8a7795-imr-lx4 # R-Car H3 + - renesas,r8a7796-imr-lx4 # R-Car M3-W + - const: renesas,imr-lx4 # R-Car Gen3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + imr-lx4@fe860000 { + compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4"; + reg = <0xfe860000 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 823>; + }; diff --git a/dts/Bindings/media/rockchip-isp1.yaml b/dts/Bindings/media/rockchip-isp1.yaml index a6b1eff879..d1489b1773 100644 --- a/dts/Bindings/media/rockchip-isp1.yaml +++ b/dts/Bindings/media/rockchip-isp1.yaml @@ -15,13 +15,22 @@ description: | properties: compatible: - const: rockchip,rk3399-cif-isp + enum: + - rockchip,px30-cif-isp + - rockchip,rk3399-cif-isp reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 3 + + interrupt-names: + items: + - const: isp + - const: mi + - const: mipi clocks: minItems: 3 @@ -41,7 +50,7 @@ properties: - const: aclk - const: hclk # only for isp1 - - const: pclk_isp + - const: pclk iommus: maxItems: 1 @@ -90,19 +99,29 @@ required: - power-domains - ports -if: - properties: - compatible: - contains: - const: rockchip,rk3399-cif-isp -then: - properties: - clocks: - minItems: 3 - maxItems: 4 - clock-names: - minItems: 3 - maxItems: 4 +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3399-cif-isp + then: + properties: + clocks: + minItems: 3 + maxItems: 4 + clock-names: + minItems: 3 + maxItems: 4 + + - if: + properties: + compatible: + contains: + const: rockchip,px30-cif-isp + then: + required: + - interrupt-names additionalProperties: false @@ -183,3 +202,66 @@ examples: }; }; }; + + - | + + #include + #include + + parent1: parent { + #address-cells = <2>; + #size-cells = <2>; + + isp: isp@ff4a0000 { + compatible = "rockchip,px30-cif-isp"; + reg = <0x0 0xff4a0000 0x0 0x8000>; + interrupts = , + , + ; + interrupt-names = "isp", "mi", "mipi"; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_WRAPPER>, + <&cru PCLK_ISP1_WRAPPER>; + clock-names = "isp", "aclk", "hclk", "pclk"; + iommus = <&isp_mmu>; + phys = <&csi_dphy>; + phy-names = "dphy"; + power-domains = <&power PX30_PD_VI>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@0 { + reg = <0>; + remote-endpoint = <&ucam1_out>; + data-lanes = <1 2>; + }; + }; + }; + }; + + i2c2: i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5695: camera@36 { + compatible = "ovti,ov5647"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + + port { + ucam1_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/media/st,stm32-cec.yaml b/dts/Bindings/media/st,stm32-cec.yaml index d75019c093..77144cc6f7 100644 --- a/dts/Bindings/media/st,stm32-cec.yaml +++ b/dts/Bindings/media/st,stm32-cec.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CEC bindings maintainers: - - Benjamin Gaignard - - Yannick Fertre + - Yannick Fertre properties: compatible: diff --git a/dts/Bindings/media/st,stm32-dcmi.yaml b/dts/Bindings/media/st,stm32-dcmi.yaml index 41e1d0cd80..9c1262a276 100644 --- a/dts/Bindings/media/st,stm32-dcmi.yaml +++ b/dts/Bindings/media/st,stm32-dcmi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding maintainers: - - Hugues Fruchet + - Hugues Fruchet properties: compatible: diff --git a/dts/Bindings/media/ti,cal.yaml b/dts/Bindings/media/ti,cal.yaml index 65177cd695..66c5d392fa 100644 --- a/dts/Bindings/media/ti,cal.yaml +++ b/dts/Bindings/media/ti,cal.yaml @@ -154,7 +154,9 @@ examples: camera-sensor@3c { compatible = "ovti,ov5640"; reg = <0x3c>; - + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml new file mode 100644 index 0000000000..25ed0266f6 --- /dev/null +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + oneOf: + - items: + - enum: + - elpida,ECB240ABACN + - elpida,B8132B2PB-6D-F + - enum: + - jedec,lpddr2-s4 + - items: + - enum: + - jedec,lpddr2-s2 + - items: + - enum: + - jedec,lpddr2-nvm + + revision-id1: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Revision 1 value of SDRAM chip. Obtained from device datasheet. + + revision-id2: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Revision 2 value of SDRAM chip. Obtained from device datasheet. + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. Obtained from device datasheet. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. Obtained from device datasheet. + enum: + - 32 + - 16 + - 8 + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Active bank a to active bank b in terms of number of clock cycles. + Obtained from device datasheet. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + Obtained from device datasheet. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. Obtained from device datasheet. + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. Obtained from device datasheet. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + Obtained from device datasheet. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + RAS-to-CAS delay in terms of number of clock cycles. Obtained from + device datasheet. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + WRITE recovery time in terms of number of clock cycles. Obtained from + device datasheet. + + tRASmin-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Row active time in terms of number of clock cycles. Obtained from device + datasheet. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. Obtained from device + datasheet. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 16 + description: | + Four-bank activate window in terms of number of clock cycles. Obtained + from device datasheet. + +patternProperties: + "^lpddr2-timings": + type: object + description: | + The lpddr2 node may have one or more child nodes of type "lpddr2-timings". + "lpddr2-timings" provides AC timing parameters of the device for + a given speed-bin. The user may provide the timings for as many + speed-bins as is required. Please see Documentation/devicetree/ + bindings/memory-controllers/ddr/lpddr2-timings.txt for more information + on "lpddr2-timings". + +required: + - compatible + - density + - io-width + +additionalProperties: false + +examples: + - | + elpida_ECB240ABACN: lpddr2 { + compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + revision-id1 = <1>; + revision-id2 = <0>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + }; + }; diff --git a/dts/Bindings/memory-controllers/ddr/lpddr2-timings.txt b/dts/Bindings/memory-controllers/ddr/lpddr2-timings.txt new file mode 100644 index 0000000000..9ceb19e0c7 --- /dev/null +++ b/dts/Bindings/memory-controllers/ddr/lpddr2-timings.txt @@ -0,0 +1,52 @@ +* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin + +Required properties: +- compatible : Should be "jedec,lpddr2-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- max-freq : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). Parameters with +a different unit have a suffix indicating the unit such as 'tRAS-max-ns' +- tRCD +- tWR +- tRAS-min +- tRRD +- tWTR +- tXP +- tRTP +- tDQSCK-max +- tFAW +- tZQCS +- tZQinit +- tRPab +- tZQCL +- tCKESR +- tRAS-max-ns +- tDQSCK-max-derated + +Example: + +timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; +}; diff --git a/dts/Bindings/memory-controllers/ddr/lpddr3-timings.txt b/dts/Bindings/memory-controllers/ddr/lpddr3-timings.txt new file mode 100644 index 0000000000..84705e50a3 --- /dev/null +++ b/dts/Bindings/memory-controllers/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/dts/Bindings/memory-controllers/ddr/lpddr3.txt b/dts/Bindings/memory-controllers/ddr/lpddr3.txt new file mode 100644 index 0000000000..031af5fb03 --- /dev/null +++ b/dts/Bindings/memory-controllers/ddr/lpddr3.txt @@ -0,0 +1,107 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be ",", and generic value "jedec,lpddr3". + Example "," values: + "samsung,K3QF2F20DB" + +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +- manufacturer-id : Manufacturer ID value read from Mode Register 5 +- revision-id : Revision IDs read from Mode Registers 6 and 7 + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt + for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + manufacturer-id = <1>; + revision-id = <123 234>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + /* workaround: 'reg' shows max-freq */ + reg = <800000000>; + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +} diff --git a/dts/Bindings/memory-controllers/fsl/ddr.txt b/dts/Bindings/memory-controllers/fsl/ddr.txt deleted file mode 100644 index dde6d83708..0000000000 --- a/dts/Bindings/memory-controllers/fsl/ddr.txt +++ /dev/null @@ -1,29 +0,0 @@ -Freescale DDR memory controller - -Properties: - -- compatible : Should include "fsl,chip-memory-controller" where - chip is the processor (bsc9132, mpc8572 etc.), or - "fsl,qoriq-memory-controller". -- reg : Address and size of DDR controller registers -- interrupts : Error interrupt of DDR controller -- little-endian : Specifies little-endian access to registers - If omitted, big-endian will be used. - -Example 1: - - memory-controller@2000 { - compatible = "fsl,bsc9132-memory-controller"; - reg = <0x2000 0x1000>; - interrupts = <16 2 1 8>; - }; - - -Example 2: - - ddr1: memory-controller@8000 { - compatible = "fsl,qoriq-memory-controller-v4.7", - "fsl,qoriq-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml b/dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml new file mode 100644 index 0000000000..af5147f9da --- /dev/null +++ b/dts/Bindings/memory-controllers/fsl/fsl,ddr.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale DDR memory controller + +maintainers: + - Borislav Petkov + - York Sun + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - fsl,qoriq-memory-controller-v4.4 + - fsl,qoriq-memory-controller-v4.5 + - fsl,qoriq-memory-controller-v4.7 + - fsl,qoriq-memory-controller-v5.0 + - const: fsl,qoriq-memory-controller + - enum: + - fsl,bsc9132-memory-controller + - fsl,8540-memory-controller + - fsl,8541-memory-controller + - fsl,8544-memory-controller + - fsl,8548-memory-controller + - fsl,8555-memory-controller + - fsl,8568-memory-controller + - fsl,mpc8536-memory-controller + - fsl,mpc8540-memory-controller + - fsl,mpc8541-memory-controller + - fsl,mpc8544-memory-controller + - fsl,mpc8548-memory-controller + - fsl,mpc8555-memory-controller + - fsl,mpc8560-memory-controller + - fsl,mpc8568-memory-controller + - fsl,mpc8569-memory-controller + - fsl,mpc8572-memory-controller + - fsl,mpc8349-memory-controller + - fsl,p1020-memory-controller + - fsl,p1021-memory-controller + - fsl,p2020-memory-controller + - fsl,qoriq-memory-controller + + interrupts: + maxItems: 1 + + little-endian: + description: + Specifies little-endian access to registers. If omitted, big-endian will + be used. + type: boolean + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + memory-controller@2000 { + compatible = "fsl,bsc9132-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <16 2 1 8>; + }; + + - | + memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; diff --git a/dts/Bindings/memory-controllers/ingenic,nemc.yaml b/dts/Bindings/memory-controllers/ingenic,nemc.yaml index fe0ce191a8..24f9e19820 100644 --- a/dts/Bindings/memory-controllers/ingenic,nemc.yaml +++ b/dts/Bindings/memory-controllers/ingenic,nemc.yaml @@ -84,7 +84,7 @@ additionalProperties: false examples: - | - #include + #include #include nemc: memory-controller@13410000 { compatible = "ingenic,jz4780-nemc"; diff --git a/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml b/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml new file mode 100644 index 0000000000..85e02854f0 --- /dev/null +++ b/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 SDRAM controller + +maintainers: + - Sergio Paracuellos + +properties: + compatible: + const: mediatek,mt7621-memc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@5000 { + compatible = "mediatek,mt7621-memc"; + reg = <0x5000 0x1000>; + }; diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.yaml b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml index e87e438280..3a82b0b27f 100644 --- a/dts/Bindings/memory-controllers/mediatek,smi-common.yaml +++ b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -36,6 +36,9 @@ properties: - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common - mediatek,mt8192-smi-common + - mediatek,mt8195-smi-common-vdo + - mediatek,mt8195-smi-common-vpp + - mediatek,mt8195-smi-sub-common - description: for mt7623 items: @@ -65,6 +68,10 @@ properties: minItems: 2 maxItems: 4 + mediatek,smi: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the smi-common node above. Only for sub-common. + required: - compatible - reg @@ -91,6 +98,29 @@ allOf: - const: smi - const: async + - if: # only for sub common + properties: + compatible: + contains: + enum: + - mediatek,mt8195-smi-sub-common + then: + required: + - mediatek,smi + properties: + clock: + items: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: apb + - const: smi + - const: gals0 + else: + properties: + mediatek,smi: false + - if: # for gen2 HW that have gals properties: compatible: @@ -98,6 +128,8 @@ allOf: - mediatek,mt6779-smi-common - mediatek,mt8183-smi-common - mediatek,mt8192-smi-common + - mediatek,mt8195-smi-common-vdo + - mediatek,mt8195-smi-common-vpp then: properties: diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml index 2353f6cf3c..eaeff1ada7 100644 --- a/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb - mediatek,mt8192-smi-larb + - mediatek,mt8195-smi-larb - description: for mt7623 items: @@ -74,6 +75,7 @@ allOf: compatible: enum: - mediatek,mt8183-smi-larb + - mediatek,mt8195-smi-larb then: properties: @@ -108,6 +110,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8167-smi-larb - mediatek,mt8192-smi-larb + - mediatek,mt8195-smi-larb then: required: diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml index cac6842dc8..2fa44951cf 100644 --- a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -164,12 +164,20 @@ patternProperties: "#size-cells": const: 0 + lpddr2: + $ref: "ddr/jedec,lpddr2.yaml#" + type: object + patternProperties: "^emc-table@[0-9]+$": $ref: "#/$defs/emc-table" - required: - - nvidia,ram-code + oneOf: + - required: + - nvidia,ram-code + + - required: + - lpddr2 additionalProperties: false @@ -227,4 +235,15 @@ examples: 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; + + emc-tables@1 { + reg = <1>; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id1 = <1>; + density = <2048>; + io-width = <16>; + }; + }; }; diff --git a/dts/Bindings/memory-controllers/omap-gpmc.txt b/dts/Bindings/memory-controllers/omap-gpmc.txt deleted file mode 100644 index c1359f4d48..0000000000 --- a/dts/Bindings/memory-controllers/omap-gpmc.txt +++ /dev/null @@ -1,157 +0,0 @@ -Device tree bindings for OMAP general purpose memory controllers (GPMC) - -The actual devices are instantiated from the child nodes of a GPMC node. - -Required properties: - - - compatible: Should be set to one of the following: - - ti,omap2420-gpmc (omap2420) - ti,omap2430-gpmc (omap2430) - ti,omap3430-gpmc (omap3430 & omap3630) - ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) - ti,am3352-gpmc (am335x devices) - - - reg: A resource specifier for the register space - (see the example below) - - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is - completed. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - gpmc,num-cs: The maximum number of chip-select lines that controller - can support. - - gpmc,num-waitpins: The maximum number of wait pins that controller can - support. - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - 0 - - Currently, calculated values derived from the contents - of the per-CS register GPMC_CONFIG7 (as set up by the - bootloader) are used for the physical address decoding. - As this will change in the future, filling correct - values here is a requirement. - - interrupt-controller: The GPMC driver implements and interrupt controller for - the NAND events "fifoevent" and "termcount" plus the - rising/falling edges on the GPMC_WAIT pins. - The interrupt number mapping is as follows - 0 - NAND_fifoevent - 1 - NAND_termcount - 2 - GPMC_WAIT0 pin edge - 3 - GPMC_WAIT1 pin edge, and so on. - - interrupt-cells: Must be set to 2 - - gpio-controller: The GPMC driver implements a GPIO controller for the - GPMC WAIT pins that can be used as general purpose inputs. - 0 maps to GPMC_WAIT0 pin. - - gpio-cells: Must be set to 2 - -Required properties when using NAND prefetch dma: - - dmas GPMC NAND prefetch dma channel - - dma-names Must be set to "rxtx" - -Timing properties for child nodes. All are optional and default to 0. - - - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: - - gpmc,cs-on-ns: Assertion time - - gpmc,cs-rd-off-ns: Read deassertion time - - gpmc,cs-wr-off-ns: Write deassertion time - - ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: - - gpmc,adv-on-ns: Assertion time - - gpmc,adv-rd-off-ns: Read deassertion time - - gpmc,adv-wr-off-ns: Write deassertion time - - gpmc,adv-aad-mux-on-ns: Assertion time for AAD - - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD - - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD - - WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,we-on-ns Assertion time - - gpmc,we-off-ns: Deassertion time - - OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,oe-on-ns: Assertion time - - gpmc,oe-off-ns: Deassertion time - - gpmc,oe-aad-mux-on-ns: Assertion time for AAD - - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD - - Access time and cycle time timings (in nanoseconds) corresponding to - GPMC_CONFIG5: - - gpmc,page-burst-access-ns: Multiple access word delay - - gpmc,access-ns: Start-cycle to first data valid delay - - gpmc,rd-cycle-ns: Total read cycle time - - gpmc,wr-cycle-ns: Total write cycle time - - gpmc,bus-turnaround-ns: Turn-around time between successive accesses - - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses - - gpmc,clk-activation-ns: GPMC clock activation time - - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid - data - -Boolean timing parameters. If property is present parameter enabled and -disabled if omitted: - - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock - - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock - - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive - accesses to a different CS - - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive - accesses to the same CS - - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock - - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock - - gpmc,time-para-granularity: Multiply all access times by 2 - -The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access-ns: In synchronous write mode, for single or - burst accesses, defines the number of - GPMC_FCLK cycles from start access time - to the GPMC_CLK rising edge used by the - memory device for the first data capture. - - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies - the time when the first data is driven on - the address-data bus. - -GPMC chip-select settings properties for child nodes. All are optional. - -- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. -- gpmc,burst-wrap Enables wrap bursting -- gpmc,burst-read Enables read page/burst mode -- gpmc,burst-write Enables write page/burst mode -- gpmc,device-width Total width of device(s) connected to a GPMC - chip-select in bytes. The GPMC supports 8-bit - and 16-bit devices and so this property must be - 1 or 2. -- gpmc,mux-add-data Address and data multiplexing configuration. - Valid values are 1 for address-address-data - multiplexing mode and 2 for address-data - multiplexing mode. -- gpmc,sync-read Enables synchronous read. Defaults to asynchronous - is this is not set. -- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous - is this is not set. -- gpmc,wait-pin Wait-pin used by client. Must be less than - "gpmc,num-waitpins". -- gpmc,wait-on-read Enables wait monitoring on reads. -- gpmc,wait-on-write Enables wait monitoring on writes. - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - - /* child nodes go here */ - }; diff --git a/dts/Bindings/memory-controllers/renesas,rpc-if.yaml b/dts/Bindings/memory-controllers/renesas,rpc-if.yaml index d25072c414..9da80e8f24 100644 --- a/dts/Bindings/memory-controllers/renesas,rpc-if.yaml +++ b/dts/Bindings/memory-controllers/renesas,rpc-if.yaml @@ -33,6 +33,7 @@ properties: - renesas,r8a77970-rpc-if # R-Car V3M - renesas,r8a77980-rpc-if # R-Car V3H - renesas,r8a77995-rpc-if # R-Car D3 + - renesas,r8a779a0-rpc-if # R-Car V3U - const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device reg: diff --git a/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 6f4fd5814b..fe8639dcff 100644 --- a/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -51,7 +51,8 @@ properties: $ref: '/schemas/types.yaml#/definitions/phandle' description: | phandle of the connected DRAM memory device. For more information please - refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt + refer to documentation file: + Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt operating-points-v2: true diff --git a/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index cba7420584..6b516d3895 100644 --- a/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -19,7 +19,7 @@ description: | Select. The FMC2 performs only one access at a time to an external device. maintainers: - - Christophe Kerello + - Christophe Kerello properties: compatible: diff --git a/dts/Bindings/memory-controllers/ti,gpmc-child.yaml b/dts/Bindings/memory-controllers/ti,gpmc-child.yaml new file mode 100644 index 0000000000..6e3995bb16 --- /dev/null +++ b/dts/Bindings/memory-controllers/ti,gpmc-child.yaml @@ -0,0 +1,245 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: device tree bindings for children of the Texas Instruments GPMC + +maintainers: + - Tony Lindgren + - Roger Quadros + +description: + This binding is meant for the child nodes of the GPMC node. The node + represents any device connected to the GPMC bus. It may be a Flash chip, + RAM chip or Ethernet controller, etc. These properties are meant for + configuring the GPMC settings/timings and will accompany the bindings + supported by the respective device. + +properties: + reg: true + +# GPMC Timing properties for child nodes. All are optional and default to 0. + gpmc,sync-clk-ps: + description: Minimum clock period for synchronous mode + default: 0 + +# Chip-select signal timings corresponding to GPMC_CONFIG2: + gpmc,cs-on-ns: + description: Assertion time + default: 0 + + gpmc,cs-rd-off-ns: + description: Read deassertion time + default: 0 + + gpmc,cs-wr-off-ns: + description: Write deassertion time + default: 0 + +# ADV signal timings corresponding to GPMC_CONFIG3: + gpmc,adv-on-ns: + description: Assertion time + default: 0 + + gpmc,adv-rd-off-ns: + description: Read deassertion time + default: 0 + + gpmc,adv-wr-off-ns: + description: Write deassertion time + default: 0 + + gpmc,adv-aad-mux-on-ns: + description: Assertion time for AAD + default: 0 + + gpmc,adv-aad-mux-rd-off-ns: + description: Read deassertion time for AAD + default: 0 + + gpmc,adv-aad-mux-wr-off-ns: + description: Write deassertion time for AAD + default: 0 + +# WE signals timings corresponding to GPMC_CONFIG4: + gpmc,we-on-ns: + description: Assertion time + default: 0 + + gpmc,we-off-ns: + description: Deassertion time + default: 0 + +# OE signals timings corresponding to GPMC_CONFIG4: + gpmc,oe-on-ns: + description: Assertion time + default: 0 + + gpmc,oe-off-ns: + description: Deassertion time + default: 0 + + gpmc,oe-aad-mux-on-ns: + description: Assertion time for AAD + default: 0 + + gpmc,oe-aad-mux-off-ns: + description: Deassertion time for AAD + default: 0 + +# Access time and cycle time timings (in nanoseconds) corresponding to +# GPMC_CONFIG5: + gpmc,page-burst-access-ns: + description: Multiple access word delay + default: 0 + + gpmc,access-ns: + description: Start-cycle to first data valid delay + default: 0 + + gpmc,rd-cycle-ns: + description: Total read cycle time + default: 0 + + gpmc,wr-cycle-ns: + description: Total write cycle time + default: 0 + + gpmc,bus-turnaround-ns: + description: Turn-around time between successive accesses + default: 0 + + gpmc,cycle2cycle-delay-ns: + description: Delay between chip-select pulses + default: 0 + + gpmc,clk-activation-ns: + description: GPMC clock activation time + default: 0 + + gpmc,wait-monitoring-ns: + description: Start of wait monitoring with regard to valid data + default: 0 + +# Boolean timing parameters. If property is present, parameter is enabled +# otherwise disabled. + gpmc,adv-extra-delay: + description: ADV signal is delayed by half GPMC clock + type: boolean + + gpmc,cs-extra-delay: + description: CS signal is delayed by half GPMC clock + type: boolean + + gpmc,cycle2cycle-diffcsen: + description: | + Add "cycle2cycle-delay" between successive accesses + to a different CS + type: boolean + + gpmc,cycle2cycle-samecsen: + description: | + Add "cycle2cycle-delay" between successive accesses + to the same CS + type: boolean + + gpmc,oe-extra-delay: + description: OE signal is delayed by half GPMC clock + type: boolean + + gpmc,we-extra-delay: + description: WE signal is delayed by half GPMC clock + type: boolean + + gpmc,time-para-granularity: + description: Multiply all access times by 2 + type: boolean + +# The following two properties are applicable only to OMAP3+ and AM335x: + gpmc,wr-access-ns: + description: | + In synchronous write mode, for single or + burst accesses, defines the number of + GPMC_FCLK cycles from start access time + to the GPMC_CLK rising edge used by the + memory device for the first data capture. + default: 0 + + gpmc,wr-data-mux-bus-ns: + description: | + In address-data multiplex mode, specifies + the time when the first data is driven on + the address-data bus. + default: 0 + +# GPMC chip-select settings properties for child nodes. All are optional. + gpmc,burst-length: + description: Page/burst length. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 4, 8, 16] + default: 0 + + gpmc,burst-wrap: + description: Enables wrap bursting + type: boolean + + gpmc,burst-read: + description: Enables read page/burst mode + type: boolean + + gpmc,burst-write: + description: Enables write page/burst mode + type: boolean + + gpmc,device-width: + description: | + Total width of device(s) connected to a GPMC + chip-select in bytes. The GPMC supports 8-bit + and 16-bit devices and so this property must be + 1 or 2. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + default: 1 + + gpmc,mux-add-data: + description: | + Address and data multiplexing configuration. + Valid values are + 0 for Non multiplexed mode + 1 for address-address-data multiplexing mode and + 2 for address-data multiplexing mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + gpmc,sync-read: + description: | + Enables synchronous read. Defaults to asynchronous + is this is not set. + type: boolean + + gpmc,sync-write: + description: | + Enables synchronous writes. Defaults to asynchronous + is this is not set. + type: boolean + + gpmc,wait-pin: + description: | + Wait-pin used by client. Must be less than "gpmc,num-waitpins". + $ref: /schemas/types.yaml#/definitions/uint32 + + gpmc,wait-on-read: + description: Enables wait monitoring on reads. + type: boolean + + gpmc,wait-on-write: + description: Enables wait monitoring on writes. + type: boolean + +required: + - reg + +# the GPMC child will have its own native properties +additionalProperties: true diff --git a/dts/Bindings/memory-controllers/ti,gpmc.yaml b/dts/Bindings/memory-controllers/ti,gpmc.yaml new file mode 100644 index 0000000000..25b42d68f9 --- /dev/null +++ b/dts/Bindings/memory-controllers/ti,gpmc.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC Memory Controller device-tree bindings + +maintainers: + - Tony Lindgren + - Roger Quadros + +description: + The GPMC is a unified memory controller dedicated for interfacing + with external memory devices like + - Asynchronous SRAM-like memories and ASICs + - Asynchronous, synchronous, and page mode burst NOR flash + - NAND flash + - Pseudo-SRAM devices + +properties: + compatible: + items: + - enum: + - ti,am3352-gpmc + - ti,omap2420-gpmc + - ti,omap2430-gpmc + - ti,omap3430-gpmc + - ti,omap4430-gpmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: | + Functional clock. Used for bus timing calculations and + GPMC configuration. + + clock-names: + items: + - const: fck + + dmas: + items: + - description: DMA channel for GPMC NAND prefetch + + dma-names: + items: + - const: rxtx + + "#address-cells": true + + "#size-cells": true + + gpmc,num-cs: + description: maximum number of supported chip-select lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + gpmc,num-waitpins: + description: maximum number of supported wait pins. + $ref: /schemas/types.yaml#/definitions/uint32 + + ranges: + minItems: 1 + description: | + Must be set up to reflect the memory layout with four + integer values for each chip-select line in use, + 0 + items: + - description: NAND bank 0 + - description: NOR/SRAM bank 0 + - description: NOR/SRAM bank 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: + description: | + The GPMC driver implements and interrupt controller for + the NAND events "fifoevent" and "termcount" plus the + rising/falling edges on the GPMC_WAIT pins. + The interrupt number mapping is as follows + 0 - NAND_fifoevent + 1 - NAND_termcount + 2 - GPMC_WAIT0 pin edge + 3 - GPMC_WAIT1 pin edge, and so on. + + '#gpio-cells': + const: 2 + + gpio-controller: + description: | + The GPMC driver implements a GPIO controller for the + GPMC WAIT pins that can be used as general purpose inputs. + 0 maps to GPMC_WAIT0 pin. + + ti,hwmods: + description: + Name of the HWMOD associated with GPMC. This is for legacy + omap2/3 platforms only. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + + ti,no-idle-on-init: + description: + Prevent idling the module at init. This is for legacy omap2/3 + platforms only. + type: boolean + deprecated: true + +patternProperties: + "@[0-7],[a-f0-9]+$": + type: object + description: | + The child device node represents the device connected to the GPMC + bus. The device can be a NAND chip, SRAM device, NOR device + or an ASIC. + + allOf: + - $ref: "ti,gpmc-child.yaml" + + unevaluatedProperties: false + +required: + - compatible + - reg + - gpmc,num-cs + - gpmc,num-waitpins + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + clocks = <&l3s_clkctrl>; + clock-names = "fck"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + }; + }; diff --git a/dts/Bindings/mfd/ac100.txt b/dts/Bindings/mfd/ac100.txt deleted file mode 100644 index dff219f074..0000000000 --- a/dts/Bindings/mfd/ac100.txt +++ /dev/null @@ -1,50 +0,0 @@ -X-Powers AC100 Codec/RTC IC Device Tree bindings - -AC100 is a audio codec and RTC subsystem combo IC. The 2 parts are -separated, including power supplies and interrupt lines, but share -a common register address space and host interface. - -Required properties: -- compatible: "x-powers,ac100" -- reg: The I2C slave address or RSB hardware address for the chip -- sub-nodes: - - codec - - compatible: "x-powers,ac100-codec" - - interrupts: SoC NMI / GPIO interrupt connected to the - IRQ_AUDIO pin - - #clock-cells: Shall be 0 - - clock-output-names: "4M_adda" - - - see clock/clock-bindings.txt for common clock bindings - - - rtc - - compatible: "x-powers,ac100-rtc" - - clocks: A phandle to the codec's "4M_adda" clock - - #clock-cells: Shall be 1 - - clock-output-names: "cko1_rtc", "cko2_rtc", "cko3_rtc" - - - see clock/clock-bindings.txt for common clock bindings - -Example: - -ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", "cko2_rtc", "cko3_rtc"; - }; -}; diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 936aa108ea..0000000000 --- a/dts/Bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,157 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality, which includes, but is not limited to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = ; - snoop-ports = <0x80>; - }; -}; - - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - "aspeed,ast2600-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -Optional properties: - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - "aspeed,ast2600-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: One of: - "aspeed,ast2600-lpc-reset"; - "aspeed,ast2500-lpc-reset"; - "aspeed,ast2400-lpc-reset"; - - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/mfd/aspeed-lpc.yaml b/dts/Bindings/mfd/aspeed-lpc.yaml new file mode 100644 index 0000000000..750996d9a1 --- /dev/null +++ b/dts/Bindings/mfd/aspeed-lpc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Tehchnology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Low Pin Count (LPC) Bus Controller + +maintainers: + - Andrew Jeffery + - Chia-Wei Wang + +description: + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The + primary use case of the Aspeed LPC controller is as a slave on the bus + (typically in a Baseboard Management Controller SoC), but under certain + conditions it can also take the role of bus master. + + The LPC controller is represented as a multi-function device to account for the + mix of functionality, which includes, but is not limited to + + * An IPMI Block Transfer[2] Controller + + * An LPC Host Interface Controller manages functions exposed to the host such + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART + management and bus snoop configuration. + + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom + hardware management protocols for handover between the host and baseboard + management controller. + + Additionally the state of the LPC controller influences the pinmux + configuration, therefore the host portion of the controller is exposed as a + syscon as a means to arbitrate access. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-v2 + - aspeed,ast2500-lpc-v2 + - aspeed,ast2600-lpc-v2 + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^lpc-ctrl@[0-9a-f]+$": + type: object + additionalProperties: false + + description: | + The LPC Host Interface Controller manages functions exposed to the host such as + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management + and bus snoop configuration. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-ctrl + - aspeed,ast2500-lpc-ctrl + - aspeed,ast2600-lpc-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + memory-region: + maxItems: 1 + description: handle to memory reservation for the LPC to AHB mapping region + + flash: + $ref: /schemas/types.yaml#/definitions/phandle + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping + + required: + - compatible + - clocks + + "^reset-controller@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The UARTs present in the ASPEED SoC can have their resets tied to the reset + state of the LPC bus. Some systems may chose to modify this configuration + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-reset + - aspeed,ast2500-lpc-reset + - aspeed,ast2600-lpc-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + required: + - compatible + - '#reset-cells' + + "^lpc-snoop@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The LPC snoop interface allows the BMC to listen on and record the data + bytes written by the Host to the targeted LPC I/O pots. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-snoop + - aspeed,ast2500-lpc-snoop + - aspeed,ast2600-lpc-snoop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + snoop-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: The LPC I/O ports to snoop + + required: + - compatible + - interrupts + - snoop-ports + + "^uart-routing@[0-9a-f]+$": + $ref: /schemas/soc/aspeed/uart-routing.yaml# + description: The UART routing control under LPC register space + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + #include + #include + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + lpc_snoop: lpc-snoop@90 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x90 0x8>; + interrupts = ; + snoop-ports = <0x80>; + }; + }; diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt deleted file mode 100644 index 2b53dcc0ea..0000000000 --- a/dts/Bindings/mfd/axp20x.txt +++ /dev/null @@ -1,273 +0,0 @@ -AXP family PMIC device tree bindings - -The axp20x family current members : -axp152 (X-Powers) -axp202 (X-Powers) -axp209 (X-Powers) -axp221 (X-Powers) -axp223 (X-Powers) -axp803 (X-Powers) -axp806 (X-Powers) -axp809 (X-Powers) -axp813 (X-Powers) - -The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything -other than the packaging. Pins are routed separately. As such they should -be treated as separate entities. The other half is an AC100 RTC/codec -combo chip. Please see ./ac100.txt for its bindings. - -Required properties: -- compatible: should be one of: - * "x-powers,axp152" - * "x-powers,axp202" - * "x-powers,axp209" - * "x-powers,axp221" - * "x-powers,axp223" - * "x-powers,axp803" - * "x-powers,axp806" - * "x-powers,axp805", "x-powers,axp806" - * "x-powers,axp305", "x-powers,axp805", "x-powers,axp806" - * "x-powers,axp809" - * "x-powers,axp813" -- reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupt-controller: The PMIC has its own internal IRQs -- #interrupt-cells: Should be set to 1 - -Supported common regulator properties, see ../regulator/regulator.txt for -more information: -- regulator-ramp-delay: sets the ramp up delay in uV/us - AXP20x/DCDC2: 1600, 800 - AXP20x/LDO3: 1600, 800 -- regulator-soft-start: enable the output at the lowest possible voltage and - only then set the desired voltage - AXP20x/LDO3: software-based implementation - -Optional properties: -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin -- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz - AXP152/20X: range: 750-1875, Default: 1.5 MHz - AXP22X/8XX: range: 1800-4050, Default: 3 MHz - -- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is - used as an output pin to control an external - regulator to drive the OTG VBus, rather then - as an input pin which signals whether the - board is driving OTG VBus or not. - (axp221 / axp223 / axp803/ axp813 only) - -- x-powers,self-working-mode and - x-powers,master-mode: Boolean (axp806 only). Set either of these when the - PMIC is wired for self-working mode or master mode. - If neither is set then slave mode is assumed. - This corresponds to how the MODESET pin is wired. - -- -supply: a phandle to the regulator supply node. May be omitted if - inputs are unregulated, such as using the IPSOUT output - from the PMIC. - -- regulators: A node that houses a sub-node for each regulator. Regulators - not used but preferred to be managed by the OS should be - listed as well. - See Documentation/devicetree/bindings/regulator/regulator.txt - for more information on standard regulator bindings. - -Optional properties for DCDC regulators: -- x-powers,dcdc-workmode: 1 for PWM mode, 0 for AUTO (PWM/PFM) mode - Default: Current hardware setting - The DCDC regulators work in a mixed PWM/PFM mode, - using PFM under light loads and switching to PWM - for heavier loads. Forcing PWM mode trades efficiency - under light loads for lower output noise. This - probably makes sense for HiFi audio related - applications that aren't battery constrained. - -AXP202/AXP209 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -LDO1 : LDO : acin-supply : always on -LDO2 : LDO : ldo24in-supply : shared supply -LDO3 : LDO : ldo3in-supply -LDO4 : LDO : ldo24in-supply : shared supply -LDO5 : LDO : ldo5in-supply - -AXP221/AXP223 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP803 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DC1SW : On/Off Switch : : DCDC1 secondary output -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP806 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDCA : DC-DC buck : vina-supply : poly-phase capable -DCDCB : DC-DC buck : vinb-supply : poly-phase capable -DCDCC : DC-DC buck : vinc-supply : poly-phase capable -DCDCD : DC-DC buck : vind-supply : poly-phase capable -DCDCE : DC-DC buck : vine-supply : poly-phase capable -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -BLDO1 : LDO : bldoin-supply : shared supply -BLDO2 : LDO : bldoin-supply : shared supply -BLDO3 : LDO : bldoin-supply : shared supply -BLDO4 : LDO : bldoin-supply : shared supply -CLDO1 : LDO : cldoin-supply : shared supply -CLDO2 : LDO : cldoin-supply : shared supply -CLDO3 : LDO : cldoin-supply : shared supply -SW : On/Off Switch : swin-supply - -Additionally, the AXP806 DC-DC regulators support poly-phase arrangements -for higher output current. The possible groupings are: A+B, A+B+C, D+E. - -AXP809 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply - -AXP813 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DCDC7 : DC-DC buck : vin7-supply -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -FLDO3 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - x-powers,dcdc-freq = <1500>; - - vdd_cpu: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; - }; - - vdd_int_dll: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; - }; - - vdd_rtc: ldo1 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-rtc"; - }; - - avcc: ldo2 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - }; - - ldo3 { - /* unused but preferred to be managed by OS */ - }; - }; -}; diff --git a/dts/Bindings/mfd/brcm,cru.yaml b/dts/Bindings/mfd/brcm,cru.yaml index 28ac60acf4..be4a2df71c 100644 --- a/dts/Bindings/mfd/brcm,cru.yaml +++ b/dts/Bindings/mfd/brcm,cru.yaml @@ -36,9 +36,15 @@ patternProperties: '^clock-controller@[a-f0-9]+$': $ref: ../clock/brcm,iproc-clocks.yaml + '^phy@[a-f0-9]+$': + $ref: ../phy/bcm-ns-usb2-phy.yaml + '^pin-controller@[a-f0-9]+$': $ref: ../pinctrl/brcm,ns-pinmux.yaml + '^syscon@[a-f0-9]+$': + $ref: syscon.yaml + '^thermal@[a-f0-9]+$': $ref: ../thermal/brcm,ns-thermal.yaml @@ -49,6 +55,7 @@ required: examples: - | + #include cru-bus@1800c100 { compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x1800c100 0x1d0>; @@ -73,6 +80,20 @@ examples: "iprocfast", "sata1", "sata2"; }; + phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; diff --git a/dts/Bindings/mfd/brcm,misc.yaml b/dts/Bindings/mfd/brcm,misc.yaml new file mode 100644 index 0000000000..cff7d772a7 --- /dev/null +++ b/dts/Bindings/mfd/brcm,misc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/brcm,misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom's MISC block + +maintainers: + - Rafał Miłecki + +description: | + Broadcom's MISC is a hardware block used on some SoCs (e.g. bcm63xx and + bcm4908). It's used to implement some simple functions like a watchdog, PCIe + reset, UniMAC control and more. + +properties: + compatible: + items: + - const: brcm,misc + - const: simple-mfd + + reg: + description: MISC block registers + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + '^reset-controller@[a-f0-9]+$': + $ref: ../reset/brcm,bcm4908-misc-pcie-reset.yaml + +additionalProperties: false + +required: + - reg + - '#address-cells' + - '#size-cells' + +examples: + - | + misc@ff802600 { + compatible = "brcm,misc", "simple-mfd"; + reg = <0xff802600 0xe4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe4>; + + reset-controller@44 { + compatible = "brcm,bcm4908-misc-pcie-reset"; + reg = <0x44 0x4>; + #reset-cells = <1>; + }; + }; diff --git a/dts/Bindings/mfd/max14577.txt b/dts/Bindings/mfd/max14577.txt index 92070b3467..be11943a05 100644 --- a/dts/Bindings/mfd/max14577.txt +++ b/dts/Bindings/mfd/max14577.txt @@ -71,7 +71,7 @@ max14577@25 { compatible = "maxim,max14577"; reg = <0x25>; interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; muic: max14577-muic { compatible = "maxim,max14577-muic"; @@ -106,7 +106,7 @@ max77836@25 { compatible = "maxim,max77836"; reg = <0x25>; interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; muic: max77836-muic { compatible = "maxim,max77836-muic"; diff --git a/dts/Bindings/mfd/max77686.txt b/dts/Bindings/mfd/max77686.txt index 42968b7144..4447d07489 100644 --- a/dts/Bindings/mfd/max77686.txt +++ b/dts/Bindings/mfd/max77686.txt @@ -21,6 +21,6 @@ Example: max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; }; diff --git a/dts/Bindings/mfd/max77693.txt b/dts/Bindings/mfd/max77693.txt index 0ced96e16c..1032df1449 100644 --- a/dts/Bindings/mfd/max77693.txt +++ b/dts/Bindings/mfd/max77693.txt @@ -139,7 +139,7 @@ Example: compatible = "maxim,max77693"; reg = <0x66>; interrupt-parent = <&gpx1>; - interrupts = <5 2>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; regulators { esafeout@1 { diff --git a/dts/Bindings/mfd/qcom,spmi-pmic.txt b/dts/Bindings/mfd/qcom,spmi-pmic.txt index 5ef79bf3d0..7a27c500ff 100644 --- a/dts/Bindings/mfd/qcom,spmi-pmic.txt +++ b/dts/Bindings/mfd/qcom,spmi-pmic.txt @@ -15,29 +15,38 @@ each. A function can consume one or more of these fixed-size register regions. Required properties: - compatible: Should contain one of: - "qcom,pm8941", - "qcom,pm8841", - "qcom,pma8084", + "qcom,pm660", + "qcom,pm660l", + "qcom,pm7325", + "qcom,pm8004", + "qcom,pm8005", "qcom,pm8019", - "qcom,pm8226", + "qcom,pm8028", "qcom,pm8110", - "qcom,pma8084", - "qcom,pmi8962", - "qcom,pmd9635", - "qcom,pm8994", - "qcom,pmi8994", - "qcom,pm8916", - "qcom,pm8004", + "qcom,pm8150", + "qcom,pm8150b", + "qcom,pm8150c", + "qcom,pm8150l", + "qcom,pm8226", + "qcom,pm8350c", + "qcom,pm8841", + "qcom,pm8901", "qcom,pm8909", + "qcom,pm8916", + "qcom,pm8941", "qcom,pm8950", - "qcom,pmi8950", + "qcom,pm8994", "qcom,pm8998", + "qcom,pma8084", + "qcom,pmd9635", + "qcom,pmi8950", + "qcom,pmi8962", + "qcom,pmi8994", "qcom,pmi8998", - "qcom,pm8005", - "qcom,pm8350c", + "qcom,pmk8002", "qcom,pmk8350", - "qcom,pm7325", "qcom,pmr735a", + "qcom,smb2351", or generalized "qcom,spmi-pmic". - reg: Specifies the SPMI USID slave address for this device. For more information see: diff --git a/dts/Bindings/mfd/qcom,tcsr.txt b/dts/Bindings/mfd/qcom,tcsr.txt index e90519d566..c5f4f0ddfc 100644 --- a/dts/Bindings/mfd/qcom,tcsr.txt +++ b/dts/Bindings/mfd/qcom,tcsr.txt @@ -6,6 +6,7 @@ registers via syscon. Required properties: - compatible: Should contain: + "qcom,tcsr-ipq6018", "syscon", "simple-mfd" for IPQ6018 "qcom,tcsr-ipq8064", "syscon" for IPQ8064 "qcom,tcsr-apq8064", "syscon" for APQ8064 "qcom,tcsr-msm8660", "syscon" for MSM8660 diff --git a/dts/Bindings/mfd/qcom-pm8xxx.yaml b/dts/Bindings/mfd/qcom-pm8xxx.yaml index 9065ec53e6..2568736701 100644 --- a/dts/Bindings/mfd/qcom-pm8xxx.yaml +++ b/dts/Bindings/mfd/qcom-pm8xxx.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - qcom,pm8018 - qcom,pm8058 - qcom,pm8821 - qcom,pm8921 diff --git a/dts/Bindings/mfd/samsung,s2mpa01.yaml b/dts/Bindings/mfd/samsung,s2mpa01.yaml new file mode 100644 index 0000000000..017befdf8a --- /dev/null +++ b/dts/Bindings/mfd/samsung,s2mpa01.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mpa01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPA01 Power Management IC + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S2MPA01 is a Power Management IC which includes voltage + and current regulators, RTC, clock outputs and other sub-blocks. + +properties: + compatible: + const: samsung,s2mpa01-pmic + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + $ref: ../regulator/samsung,s2mpa01.yaml + description: + List of child nodes that specify the regulators. + + wakeup-source: true + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mpa01-pmic"; + reg = <0x66>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_MMC2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + // ... + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <50000>; + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,s2mps11.yaml b/dts/Bindings/mfd/samsung,s2mps11.yaml new file mode 100644 index 0000000000..771b3f16da --- /dev/null +++ b/dts/Bindings/mfd/samsung,s2mps11.yaml @@ -0,0 +1,267 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mps11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS11/13/14/15 and S2MPU02 Power Management IC + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S2MPS11/13/14/15 and S2MPU02 is a family of Power Management IC + which include voltage and current regulators, RTC, clock outputs and other + sub-blocks. + +properties: + compatible: + enum: + - samsung,s2mps11-pmic + - samsung,s2mps13-pmic + - samsung,s2mps14-pmic + - samsung,s2mps15-pmic + - samsung,s2mpu02-pmic + + clocks: + $ref: ../clock/samsung,s2mps11.yaml + description: + Child node describing clock provider. + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + type: object + description: + List of child nodes that specify the regulators. + + samsung,s2mps11-acokb-ground: + description: | + Indicates that ACOKB pin of S2MPS11 PMIC is connected to the ground so + the PMIC must manually set PWRHOLD bit in CTRL1 register to turn off the + power. Usually the ACOKB is pulled up to VBATT so when PWRHOLD pin goes + low, the rising ACOKB will trigger power off. + type: boolean + + samsung,s2mps11-wrstbi-ground: + description: | + Indicates that WRSTBI pin of PMIC is pulled down. When the system is + suspended it will always go down thus triggerring unwanted buck warm + reset (setting buck voltages to default values). + type: boolean + + wakeup-source: true + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,s2mps11-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps11.yaml + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps13-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps13.yaml + samsung,s2mps11-acokb-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps14-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps14.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps15-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps15.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mpu02-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mpu02.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + samsung,s2mps11-acokb-ground; + wakeup-source; + + clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // .... + + BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // ... + }; + }; + }; + + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mps14-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", "s2mps14_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VLDO1_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + // ... + + BUCK1 { + regulator-name = "VBUCK1_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,s5m8767.yaml b/dts/Bindings/mfd/samsung,s5m8767.yaml new file mode 100644 index 0000000000..5531718abd --- /dev/null +++ b/dts/Bindings/mfd/samsung,s5m8767.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s5m8767.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5M8767 Power Management IC + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S5M8767 is a Power Management IC which includes voltage + and current regulators, RTC, clock outputs and other sub-blocks. + +properties: + compatible: + const: samsung,s5m8767-pmic + + clocks: + $ref: ../clock/samsung,s2mps11.yaml + description: + Child node describing clock provider. + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + $ref: ../regulator/samsung,s5m8767.yaml + description: + List of child nodes that specify the regulators. + + s5m8767,pmic-buck2-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck2 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck3-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck3 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck4-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck4 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck-ds-gpios: + minItems: 3 + maxItems: 3 + description: | + GPIO specifiers for three host gpio's used for selecting GPIO DVS lines. + It is one-to-one mapped to dvs gpio lines. + + s5m8767,pmic-buck2-uses-gpio-dvs: + type: boolean + description: buck2 can be controlled by gpio dvs. + + s5m8767,pmic-buck3-uses-gpio-dvs: + type: boolean + description: buck3 can be controlled by gpio dvs. + + s5m8767,pmic-buck4-uses-gpio-dvs: + type: boolean + description: buck4 can be controlled by gpio dvs. + + s5m8767,pmic-buck-default-dvs-idx: + $ref: /schemas/types.yaml#/definitions/uint32-array + minimum: 0 + maximum: 7 + default: 0 + description: | + Default voltage setting selected from the possible 8 options selectable + by the dvs gpios. The value of this property should be between 0 and 7. + If not specified or if out of range, the default value of this property + is set to 0. + + s5m8767,pmic-buck-dvs-gpios: + minItems: 3 + maxItems: 3 + description: | + GPIO specifiers for three host gpio's used for dvs. + + vinb1-supply: + description: Power supply for buck1 + vinb2-supply: + description: Power supply for buck2 + vinb3-supply: + description: Power supply for buck3 + vinb4-supply: + description: Power supply for buck4 + vinb5-supply: + description: Power supply for buck5 + vinb6-supply: + description: Power supply for buck6 + vinb7-supply: + description: Power supply for buck7 + vinb8-supply: + description: Power supply for buck8 + vinb9-supply: + description: Power supply for buck9 + + vinl1-supply: + description: Power supply for LDO3, LDO10, LDO26, LDO27 + vinl2-supply: + description: Power supply for LDO13, LDO16, LDO25, LDO28 + vinl3-supply: + description: Power supply for LDO11, LDO14 + vinl4-supply: + description: Power supply for LDO4, LDO9 + vinl5-supply: + description: Power supply for LDO12, LDO17, LDO19, LDO23 + vinl6-supply: + description: Power supply for LDO18, LDO20, LDO21, LDO24 + vinl7-supply: + description: Power supply for LDO5, LDO22 + vinl8-supply: + description: Power supply for LDO1, LDO6, LDO7, LDO8, LDO15 + vinl9-supply: + description: Power supply for LDO2 + + wakeup-source: true + +required: + - compatible + - reg + - regulators + - s5m8767,pmic-buck-ds-gpios + +dependencies: + s5m8767,pmic-buck2-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck3-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck4-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck2-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck2-dvs-voltage' ] + s5m8767,pmic-buck3-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck3-dvs-voltage' ] + s5m8767,pmic-buck4-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck4-dvs-voltage' ] + +additionalProperties: false + +allOf: + - if: + required: + - s5m8767,pmic-buck2-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck3-uses-gpio-dvs: false + s5m8767,pmic-buck4-uses-gpio-dvs: false + + - if: + required: + - s5m8767,pmic-buck3-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck2-uses-gpio-dvs: false + s5m8767,pmic-buck4-uses-gpio-dvs: false + + - if: + required: + - s5m8767,pmic-buck4-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck2-uses-gpio-dvs: false + s5m8767,pmic-buck3-uses-gpio-dvs: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + s5m8767,pmic-buck2-uses-gpio-dvs; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, + <&gpd1 1 GPIO_ACTIVE_LOW>, + <&gpd1 2 GPIO_ACTIVE_LOW>; + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, + <&gpx2 4 GPIO_ACTIVE_LOW>, + <&gpx2 5 GPIO_ACTIVE_LOW>; + + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", "en32khz_cp", "en32khz_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + + BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + }; + }; + }; + + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, + <&gpx2 4 GPIO_ACTIVE_LOW>, + <&gpx2 5 GPIO_ACTIVE_LOW>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", "en32khz_cp", "en32khz_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,sec-core.txt b/dts/Bindings/mfd/samsung,sec-core.txt deleted file mode 100644 index c68cdd3651..0000000000 --- a/dts/Bindings/mfd/samsung,sec-core.txt +++ /dev/null @@ -1,86 +0,0 @@ -Binding for Samsung S2M and S5M family multi-function device -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. - -The Samsung S2MPA01, S2MPS11/13/14/15, S2MPU02 and S5M8767 is a family -of multi-function devices which include voltage and current regulators, RTC, -charger controller, clock outputs and other sub-blocks. It is interfaced -to the host controller using an I2C interface. Each sub-block is usually -addressed by the host system using different I2C slave addresses. - - -This document describes bindings for main device node. Optional sub-blocks -must be a sub-nodes to it. Bindings for them can be found in: - - bindings/regulator/samsung,s2mpa01.txt - - bindings/regulator/samsung,s2mps11.txt - - bindings/regulator/samsung,s5m8767.txt - - bindings/clock/samsung,s2mps11.txt - - -Required properties: - - compatible: Should be one of the following - - "samsung,s2mpa01-pmic", - - "samsung,s2mps11-pmic", - - "samsung,s2mps13-pmic", - - "samsung,s2mps14-pmic", - - "samsung,s2mps15-pmic", - - "samsung,s2mpu02-pmic", - - "samsung,s5m8767-pmic". - - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. - -Optional properties: - - interrupts: Interrupt specifiers for interrupt sources. - - samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled - down. When the system is suspended it will always go down thus triggerring - unwanted buck warm reset (setting buck voltages to default values). - - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is - connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1 - register to turn off the power. Usually the ACOKB is pulled up to VBATT so - when PWRHOLD pin goes low, the rising ACOKB will trigger power off. - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/dts/Bindings/mfd/st,stm32-lptimer.yaml b/dts/Bindings/mfd/st,stm32-lptimer.yaml index 8bcea8dd7d..ec7f0190f4 100644 --- a/dts/Bindings/mfd/st,stm32-lptimer.yaml +++ b/dts/Bindings/mfd/st,stm32-lptimer.yaml @@ -17,7 +17,7 @@ description: | - simple counter from IN1 input signal. maintainers: - - Fabrice Gasnier + - Fabrice Gasnier properties: compatible: diff --git a/dts/Bindings/mfd/st,stm32-timers.yaml b/dts/Bindings/mfd/st,stm32-timers.yaml index dace35362a..10b330d429 100644 --- a/dts/Bindings/mfd/st,stm32-timers.yaml +++ b/dts/Bindings/mfd/st,stm32-timers.yaml @@ -17,8 +17,7 @@ description: | programmable prescaler. maintainers: - - Benjamin Gaignard - - Fabrice Gasnier + - Fabrice Gasnier properties: compatible: diff --git a/dts/Bindings/mfd/st,stmfx.yaml b/dts/Bindings/mfd/st,stmfx.yaml index 19e9afb385..b2a4e4aa7f 100644 --- a/dts/Bindings/mfd/st,stmfx.yaml +++ b/dts/Bindings/mfd/st,stmfx.yaml @@ -12,7 +12,7 @@ description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C through VDD) and resistive touchscreen controller. maintainers: - - Amelie Delaunay + - Amelie Delaunay properties: compatible: diff --git a/dts/Bindings/mfd/st,stpmic1.yaml b/dts/Bindings/mfd/st,stpmic1.yaml index 305123e74a..426658ad81 100644 --- a/dts/Bindings/mfd/st,stpmic1.yaml +++ b/dts/Bindings/mfd/st,stpmic1.yaml @@ -9,7 +9,7 @@ title: STMicroelectonics STPMIC1 Power Management IC bindings description: STMicroelectronics STPMIC1 Power Management IC maintainers: - - pascal Paillet + - pascal Paillet properties: compatible: diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml index abe3fd817e..5de16388a0 100644 --- a/dts/Bindings/mfd/syscon.yaml +++ b/dts/Bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - brcm,cru-clkset - hisilicon,dsa-subctrl - hisilicon,hi6220-sramctrl - hisilicon,pcie-sas-subctrl @@ -49,12 +50,14 @@ properties: - rockchip,rk3066-qos - rockchip,rk3228-qos - rockchip,rk3288-qos + - rockchip,rk3368-qos - rockchip,rk3399-qos - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg - samsung,exynos5433-sysreg + - samsung,exynosautov9-sysreg - const: syscon diff --git a/dts/Bindings/mfd/ti,am3359-tscadc.yaml b/dts/Bindings/mfd/ti,am3359-tscadc.yaml new file mode 100644 index 0000000000..34bf6a0143 --- /dev/null +++ b/dts/Bindings/mfd/ti,am3359-tscadc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,am3359-tscadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM3359 Touchscreen controller/ADC + +maintainers: + - Miquel Raynal + +properties: + compatible: + oneOf: + - const: ti,am3359-tscadc + - items: + - const: ti,am654-tscadc + - const: ti,am3359-tscadc + - const: ti,am4372-magadc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + dmas: + items: + - description: DMA controller phandle and request line for FIFO0 + - description: DMA controller phandle and request line for FIFO1 + + dma-names: + items: + - const: fifo0 + - const: fifo1 + + adc: + type: object + description: ADC child + + tsc: + type: object + description: Touchscreen controller child + + mag: + type: object + description: Magnetic reader + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + + tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + }; + + adc { + }; + }; diff --git a/dts/Bindings/mfd/x-powers,ac100.yaml b/dts/Bindings/mfd/x-powers,ac100.yaml new file mode 100644 index 0000000000..de330c9869 --- /dev/null +++ b/dts/Bindings/mfd/x-powers,ac100.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: X-Powers AC100 Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + +properties: + compatible: + const: x-powers,ac100 + + reg: + maxItems: 1 + + codec: + type: object + + properties: + "#clock-cells": + const: 0 + + compatible: + const: x-powers,ac100-codec + + interrupts: + maxItems: 1 + + clock-output-names: + maxItems: 1 + description: > + Name of the 4M_adda clock exposed by the codec + + required: + - "#clock-cells" + - compatible + - interrupts + - clock-output-names + + additionalProperties: false + + rtc: + type: object + + properties: + "#clock-cells": + const: 1 + + compatible: + const: x-powers,ac100-rtc + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: > + A phandle to the codec's "4M_adda" clock + + clock-output-names: + maxItems: 3 + description: > + Name of the cko1, cko2 and cko3 clocks exposed by the codec + + required: + - "#clock-cells" + - compatible + - interrupts + - clocks + - clock-output-names + + additionalProperties: false + +required: + - compatible + - reg + - codec + - rtc + +additionalProperties: false + +examples: + - | + #include + + rsb { + #address-cells = <1>; + #size-cells = <0>; + + codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", "cko2_rtc", "cko3_rtc"; + }; + }; + }; + +... diff --git a/dts/Bindings/mfd/x-powers,axp152.yaml b/dts/Bindings/mfd/x-powers,axp152.yaml new file mode 100644 index 0000000000..3a53bae611 --- /dev/null +++ b/dts/Bindings/mfd/x-powers,axp152.yaml @@ -0,0 +1,400 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: X-Powers AXP PMIC Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + +allOf: + - if: + properties: + compatible: + contains: + enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + + then: + properties: + regulators: + properties: + x-powers,dcdc-freq: + minimum: 750 + maximum: 1875 + default: 1500 + + else: + properties: + regulators: + properties: + x-powers,dcdc-freq: + minimum: 1800 + maximum: 4050 + default: 3000 + + - if: + properties: + compatible: + contains: + enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + + then: + not: + required: + - x-powers,drive-vbus-en + + - if: + not: + properties: + compatible: + contains: + const: x-powers,axp806 + + then: + allOf: + - not: + required: + - x-powers,self-working-mode + + - not: + required: + - x-powers,master-mode + + - if: + not: + properties: + compatible: + contains: + const: x-powers,axp305 + + then: + required: + - interrupts + +properties: + compatible: + oneOf: + - enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + - x-powers,axp221 + - x-powers,axp223 + - x-powers,axp803 + - x-powers,axp806 + - x-powers,axp809 + - x-powers,axp813 + - items: + - const: x-powers,axp805 + - const: x-powers,axp806 + - items: + - const: x-powers,axp305 + - const: x-powers,axp805 + - const: x-powers,axp806 + - items: + - const: x-powers,axp818 + - const: x-powers,axp813 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + x-powers,drive-vbus-en: + type: boolean + description: > + Set this when the N_VBUSEN pin is used as an output pin to control an + external regulator to drive the OTG VBus, rather then as an input pin + which signals whether the board is driving OTG VBus or not. + + x-powers,self-working-mode: + type: boolean + description: > + Set this when the PMIC is wired for self-working mode through the MODESET + pin. + + x-powers,master-mode: + type: boolean + description: > + Set this when the PMIC is wired for master mode through the MODESET pin. + + vin1-supply: + description: > + DCDC1 power supply node, if present. + + vin2-supply: + description: > + DCDC2 power supply node, if present. + + vin3-supply: + description: > + DCDC3 power supply node, if present. + + vin4-supply: + description: > + DCDC4 power supply node, if present. + + vin5-supply: + description: > + DCDC5 power supply node, if present. + + vin6-supply: + description: > + DCDC6 power supply node, if present. + + vin7-supply: + description: > + DCDC7 power supply node, if present. + + vina-supply: + description: > + DCDCA power supply node, if present. + + vinb-supply: + description: > + DCDCB power supply node, if present. + + vinc-supply: + description: > + DCDCC power supply node, if present. + + vind-supply: + description: > + DCDCD power supply node, if present. + + vine-supply: + description: > + DCDCE power supply node, if present. + + acin-supply: + description: > + LDO1 power supply node, if present. + + ldo24in-supply: + description: > + LDO2 and LDO4 power supply node, if present. + + ldo3in-supply: + description: > + LDO3 power supply node, if present. + + ldo5in-supply: + description: > + LDO5 power supply node, if present. + + aldoin-supply: + description: > + ALDO* power supply node, if present. + + bldoin-supply: + description: > + BLDO* power supply node, if present. + + cldoin-supply: + description: > + CLDO* power supply node, if present. + + dldoin-supply: + description: > + DLDO* power supply node, if present. + + eldoin-supply: + description: > + ELDO* power supply node, if present. + + fldoin-supply: + description: > + FLDO* power supply node, if present. + + ips-supply: + description: > + LDO_IO0, LDO_IO1 and RTC_LDO power supply node, if present. + + drivevbus-supply: + description: > + DRIVEVBUS power supply node, if present. + + swin-supply: + description: > + SW power supply node, if present. + + adc: + $ref: /schemas/iio/adc/x-powers,axp209-adc.yaml# + + gpio: + $ref: /schemas/gpio/x-powers,axp209-gpio.yaml# + + ac-power: + $ref: /schemas/power/supply/x-powers,axp20x-ac-power-supply.yaml# + + battery-power: + $ref: /schemas/power/supply/x-powers,axp20x-battery-power-supply.yaml# + + usb-power: + $ref: /schemas/power/supply/x-powers,axp20x-usb-power-supply.yaml# + + regulators: + type: object + + properties: + x-powers,dcdc-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Defines the work frequency of DC-DC in kHz. + + patternProperties: + "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|drivevbus|dc5ldo)$": + $ref: /schemas/regulator/regulator.yaml# + type: object + + properties: + regulator-ramp-delay: + description: > + Only 800 and 1600 are valid for the DCDC2 and LDO3 regulators on + the AXP209. + + regulator-soft-start: + description: > + Only valid for the LDO3 regulator. + + x-powers,dcdc-workmode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: > + Only valid for DCDC regulators. Setup 1 for PWM mode, 0 + for AUTO (PWM/PFM) mode. The DCDC regulators work in a + mixed PWM/PFM mode, using PFM under light loads and + switching to PWM for heavier loads. Forcing PWM mode + trades efficiency under light loads for lower output + noise. This probably makes sense for HiFi audio related + applications that aren't battery constrained. + + additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + - | + #include + + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp202-ac-power-supply"; + }; + + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0-adc-pin { + pins = "GPIO0"; + function = "adc"; + }; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp209-battery-power-supply"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <1500>; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; + }; + + reg_ldo1: ldo1 { + /* LDO1 is a fixed output regulator */ + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; + }; + + reg_ldo2: ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + reg_ldo3: ldo3 { + regulator-name = "ldo3"; + }; + + reg_ldo4: ldo4 { + regulator-name = "ldo4"; + }; + + reg_ldo5: ldo5 { + regulator-name = "ldo5"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp202-usb-power-supply"; + }; + }; + }; diff --git a/dts/Bindings/mfd/xylon,logicvc.yaml b/dts/Bindings/mfd/xylon,logicvc.yaml index 8a1a6625c7..9efd49c39b 100644 --- a/dts/Bindings/mfd/xylon,logicvc.yaml +++ b/dts/Bindings/mfd/xylon,logicvc.yaml @@ -46,6 +46,9 @@ patternProperties: "^gpio@[0-9a-f]+$": $ref: /schemas/gpio/xylon,logicvc-gpio.yaml# + "^display@[0-9a-f]+$": + $ref: /schemas/display/xylon,logicvc-display.yaml# + required: - compatible - reg diff --git a/dts/Bindings/mips/ingenic/ingenic,cpu.yaml b/dts/Bindings/mips/ingenic/ingenic,cpu.yaml index 6df1a9470d..b7e7fa7154 100644 --- a/dts/Bindings/mips/ingenic/ingenic,cpu.yaml +++ b/dts/Bindings/mips/ingenic/ingenic,cpu.yaml @@ -44,7 +44,7 @@ additionalProperties: false examples: - | - #include + #include cpus { #address-cells = <1>; diff --git a/dts/Bindings/mips/ralink.txt b/dts/Bindings/mips/ralink.txt deleted file mode 100644 index 8cc0ab4157..0000000000 --- a/dts/Bindings/mips/ralink.txt +++ /dev/null @@ -1,32 +0,0 @@ -Ralink MIPS SoC device tree bindings - -1. SoCs - -Each device tree must specify a compatible value for the Ralink SoC -it uses in the compatible property of the root node. The compatible -value must be one of the following values: - - ralink,rt2880-soc - ralink,rt3050-soc - ralink,rt3052-soc - ralink,rt3350-soc - ralink,rt3352-soc - ralink,rt3883-soc - ralink,rt5350-soc - ralink,mt7620a-soc - ralink,mt7620n-soc - ralink,mt7628a-soc - ralink,mt7688a-soc - -2. Boards - -GARDENA smart Gateway (MT7688) - -This board is based on the MediaTek MT7688 and equipped with 128 MiB -of DDR and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND -storage. - ------------------------------- -Required root node properties: -- compatible = "gardena,smart-gateway-mt7688", "ralink,mt7688a-soc", - "ralink,mt7628a-soc"; diff --git a/dts/Bindings/mips/ralink.yaml b/dts/Bindings/mips/ralink.yaml new file mode 100644 index 0000000000..0588cee25a --- /dev/null +++ b/dts/Bindings/mips/ralink.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ralink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink SoC based Platforms Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + Boards with a Ralink SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Boards with Ralink RT2880 SoC + items: + - enum: + - ralink,rt2880-eval-board + - const: ralink,rt2880-soc + + - description: Boards with Ralink RT3050 SoC + items: + - const: ralink,rt3050-soc + + - description: Boards with Ralink RT3052 SoC + items: + - enum: + - ralink,rt3052-eval-board + - const: ralink,rt3052-soc + + - description: Boards with Ralink RT3350 SoC + items: + - const: ralink,rt3350-soc + + - description: Boards with Ralink RT3352 SoC + items: + - const: ralink,rt3352-soc + + - description: Boards with Ralink RT3383 SoC + items: + - enum: + - ralink,rt3883-eval-board + - const: ralink,rt3383-soc + + - description: Boards with Ralink RT5350 SoC + items: + - const: ralink,rt5350-soc + + - description: Boards with Mediatek/Ralink MT7620A SoC + items: + - enum: + - ralink,mt7620a-eval-board + - const: ralink,mt7620a-soc + + - description: Boards with Mediatek/Ralink MT7620N SoC + items: + - const: ralink,mt7620n-soc + + - description: Boards with Mediatek/Ralink MT7628A SoC + items: + - enum: + - onion,omega2+ + - vocore,vocore2 + - const: ralink,mt7628a-soc + + - description: Boards with Mediatek/Ralink MT7688A SoC + items: + - enum: + - gardena,smart-gateway-mt7688 + - onion,omega2+ + - const: ralink,mt7628a-soc + + - description: Boards with Mediatek/Ralink MT7621 SoC + items: + - enum: + - gnubee,gb-pc1 + - gnubee,gb-pc2 + - const: mediatek,mt7621-soc + +additionalProperties: true + +... diff --git a/dts/Bindings/mmc/arasan,sdhci.yaml b/dts/Bindings/mmc/arasan,sdhci.yaml index 37a5fe7b26..de6f076e0e 100644 --- a/dts/Bindings/mmc/arasan,sdhci.yaml +++ b/dts/Bindings/mmc/arasan,sdhci.yaml @@ -88,6 +88,12 @@ properties: description: For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - items: + - const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY + - const: arasan,sdhci-5.1 + description: + For this device it is strongly suggested to include + clock-output-names and '#clock-cells'. reg: maxItems: 1 @@ -153,7 +159,6 @@ properties: The MIO bank number in which the command and data lines are configured. dependencies: - clock-output-names: [ '#clock-cells' ] '#clock-cells': [ clock-output-names ] required: @@ -301,3 +306,22 @@ examples: <&scmi_clk KEEM_BAY_PSS_SD0>; arasan,soc-ctl-syscon = <&sd0_phy_syscon>; }; + + - | + #define EMMC_XIN_CLK + #define EMMC_AXI_CLK + #define TBH_PSS_EMMC_RST_N + mmc@80420000 { + compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1"; + interrupts = ; + reg = <0x80420000 0x400>; + clocks = <&scmi_clk EMMC_XIN_CLK>, + <&scmi_clk EMMC_AXI_CLK>; + clock-names = "clk_xin", "clk_ahb"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + assigned-clocks = <&scmi_clk EMMC_XIN_CLK>; + clock-output-names = "emmc_cardclock"; + resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>; + #clock-cells = <0x0>; + }; diff --git a/dts/Bindings/mmc/cdns,sdhci.yaml b/dts/Bindings/mmc/cdns,sdhci.yaml index af7442f738..4207fed62d 100644 --- a/dts/Bindings/mmc/cdns,sdhci.yaml +++ b/dts/Bindings/mmc/cdns,sdhci.yaml @@ -17,6 +17,7 @@ properties: compatible: items: - enum: + - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml index a3412f2211..19621a2f8b 100644 --- a/dts/Bindings/mmc/fsl-imx-esdhc.yaml +++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml @@ -34,6 +34,7 @@ properties: - fsl,imx6ull-usdhc - fsl,imx7d-usdhc - fsl,imx7ulp-usdhc + - nxp,s32g2-usdhc - items: - enum: - fsl,imx8mm-usdhc diff --git a/dts/Bindings/mmc/ingenic,mmc.yaml b/dts/Bindings/mmc/ingenic,mmc.yaml index 546480f411..01d5c6da0e 100644 --- a/dts/Bindings/mmc/ingenic,mmc.yaml +++ b/dts/Bindings/mmc/ingenic,mmc.yaml @@ -61,7 +61,7 @@ unevaluatedProperties: false examples: - | - #include + #include #include mmc0: mmc@13450000 { compatible = "ingenic,jz4780-mmc"; diff --git a/dts/Bindings/mmc/mmc-card.txt b/dts/Bindings/mmc/mmc-card.txt deleted file mode 100644 index 8d2d717589..0000000000 --- a/dts/Bindings/mmc/mmc-card.txt +++ /dev/null @@ -1,30 +0,0 @@ -mmc-card / eMMC bindings ------------------------- - -This documents describes the devicetree bindings for a mmc-host controller -child node describing a mmc-card / an eMMC, see "Use of Function subnodes" -in mmc.txt - -Required properties: --compatible : Must be "mmc-card" --reg : Must be <0> - -Optional properties: --broken-hpi : Use this to indicate that the mmc-card has a broken hpi - implementation, and that hpi should not be used - -Example: - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/dts/Bindings/mmc/mmc-card.yaml b/dts/Bindings/mmc/mmc-card.yaml new file mode 100644 index 0000000000..b17d454442 --- /dev/null +++ b/dts/Bindings/mmc/mmc-card.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC Card / eMMC Generic Device Tree Bindings + +maintainers: + - Ulf Hansson + +description: | + This documents describes the devicetree bindings for a mmc-host controller + child node describing a mmc-card / an eMMC. + +properties: + compatible: + const: mmc-card + + reg: + const: 0 + + broken-hpi: + $ref: /schemas/types.yaml#/definitions/flag + description: + Use this to indicate that the mmc-card has a broken hpi + implementation, and that hpi should not be used. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + mmc { + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + broken-hpi; + }; + }; + +... diff --git a/dts/Bindings/mmc/mmc-controller.yaml b/dts/Bindings/mmc/mmc-controller.yaml index 25ac8e2009..513f3c8758 100644 --- a/dts/Bindings/mmc/mmc-controller.yaml +++ b/dts/Bindings/mmc/mmc-controller.yaml @@ -333,12 +333,6 @@ patternProperties: subnode describes. A value of 0 denotes the memory SD function, values from 1 to 7 denote the SDIO functions. - broken-hpi: - $ref: /schemas/types.yaml#/definitions/flag - description: - Use this to indicate that the mmc-card has a broken hpi - implementation, and that hpi should not be used. - required: - reg diff --git a/dts/Bindings/mmc/mtk-sd.yaml b/dts/Bindings/mmc/mtk-sd.yaml index e866e98554..82768a8072 100644 --- a/dts/Bindings/mmc/mtk-sd.yaml +++ b/dts/Bindings/mmc/mtk-sd.yaml @@ -119,6 +119,18 @@ properties: If present, HS400 command responses are sampled on rising edges. If not present, HS400 command responses are sampled on falling edges. + mediatek,hs400-ds-dly3: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Gear of the third delay line for DS for input data latch in data + pad macro, there are 32 stages from 0 to 31. + For different corner IC, the time is different about one step, it is + about 100ps. + The value is confirmed by doing scan and calibration to find a best + value with corner IC and it is valid only for HS400 mode. + minimum: 0 + maximum: 31 + mediatek,latch-ck: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/dts/Bindings/mmc/sdhci-msm.txt b/dts/Bindings/mmc/sdhci-msm.txt index 365c3fc122..50841e2843 100644 --- a/dts/Bindings/mmc/sdhci-msm.txt +++ b/dts/Bindings/mmc/sdhci-msm.txt @@ -13,6 +13,7 @@ Required properties: string is added to support this change - "qcom,sdhci-msm-v5". full compatible strings with SoC and version: "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" + "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" diff --git a/dts/Bindings/mmc/sdhci-omap.txt b/dts/Bindings/mmc/sdhci-omap.txt index aeb615ef67..f91e341e6b 100644 --- a/dts/Bindings/mmc/sdhci-omap.txt +++ b/dts/Bindings/mmc/sdhci-omap.txt @@ -5,7 +5,11 @@ Refer to mmc.txt for standard MMC bindings. For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning. Required properties: -- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers +- compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers + Should be "ti,omap3-sdhci" for omap3 controllers + Should be "ti,omap4-sdhci" for omap4 and ti81 controllers + Should be "ti,omap5-sdhci" for omap5 controllers + Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers Should be "ti,k2g-sdhci" for K2G Should be "ti,am335-sdhci" for am335x controllers Should be "ti,am437-sdhci" for am437x controllers @@ -24,6 +28,9 @@ Optional properties: DMA specifiers listed in dmas. The string naming is to be "tx" and "rx" for TX and RX DMA requests, respectively. +Deprecated properties: +- ti,non-removable: Compatible with the generic non-removable property + Example: mmc1: mmc@4809c000 { compatible = "ti,dra7-sdhci"; diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt deleted file mode 100644 index c459f169a9..0000000000 --- a/dts/Bindings/mtd/gpmc-nand.txt +++ /dev/null @@ -1,147 +0,0 @@ -Device tree bindings for GPMC connected NANDs - -GPMC connected NAND (found on OMAP boards) are represented as child nodes of -the GPMC controller with a name of "nand". - -All timing relevant properties as well as generic gpmc child properties are -explained in a separate documents - please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -For NAND specific properties such as ECC modes or bus width, please refer to -Documentation/devicetree/bindings/mtd/nand-controller.yaml - - -Required properties: - - - compatible: "ti,omap2-nand" - - reg: range id (CS number), base offset and length of the - NAND I/O space - - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount. - -Optional properties: - - - nand-bus-width: Set this numeric value to 16 if the hardware - is wired that way. If not specified, a bus - width of 8 is assumed. - - - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: - "sw" 1-bit Hamming ecc code via software - "hw" use "ham1" instead - "hw-romcode" use "ham1" instead - "ham1" 1-bit Hamming ecc code - "bch4" 4-bit BCH ecc code - "bch8" 8-bit BCH ecc code - "bch16" 16-bit BCH ECC code - Refer below "How to select correct ECC scheme for your device ?" - - - ti,nand-xfer-type: A string setting the data transfer type. One of: - - "prefetch-polled" Prefetch polled mode (default) - "polled" Polled mode, without prefetch - "prefetch-dma" Prefetch enabled DMA mode - "prefetch-irq" Prefetch enabled irq mode - - - elm_id: use "ti,elm-id" instead - - ti,elm-id: Specifies phandle of the ELM devicetree node. - ELM is an on-chip hardware engine on TI SoC which is used for - locating ECC errors for BCHx algorithms. SoC devices which have - ELM hardware engines should specify this device node in .dtsi - Using ELM for ECC error correction frees some CPU cycles. - - rb-gpios: GPIO specifier for the ready/busy# pin. - -For inline partition table parsing (optional): - - - #address-cells: should be set to 1 - - #size-cells: should be set to 1 - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x36c>; - interrupts = <100>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */ - elm_id = <&elm>; - interrupt-controller; - #interrupt-cells = <2>; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - /* partitions go here */ - }; - }; - -How to select correct ECC scheme for your device ? --------------------------------------------------- -Higher ECC scheme usually means better protection against bit-flips and -increased system lifetime. However, selection of ECC scheme is dependent -on various other factors also like; - -(1) support of built in hardware engines. - Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot - support ecc-schemes with hardware error-correction (BCHx_HW). However - such SoC can use ecc-schemes with software library for error-correction - (BCHx_HW_DETECTION_SW). The error correction capability with software - library remains equivalent to their hardware counter-part, but there is - slight CPU penalty when too many bit-flips are detected during reads. - -(2) Device parameters like OOBSIZE. - Other factor which governs the selection of ecc-scheme is oob-size. - Higher ECC schemes require more OOB/Spare area to store ECC syndrome, - so the device should have enough free bytes available its OOB/Spare - area to accommodate ECC for entire page. In general following expression - helps in determining if given device can accommodate ECC syndrome: - "2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE" - where - OOBSIZE number of bytes in OOB/spare area - PAGESIZE number of bytes in main-area of device page - ECC_BYTES number of ECC bytes generated to protect - 512 bytes of data, which is: - '3' for HAM1_xx ecc schemes - '7' for BCH4_xx ecc schemes - '14' for BCH8_xx ecc schemes - '26' for BCH16_xx ecc schemes - - Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and - trying to use BCH16 (ECC_BYTES=26) ecc-scheme. - Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B - which is greater than capacity of NAND device (OOBSIZE=64) - Hence, BCH16 cannot be supported on given device. But it can - probably use lower ecc-schemes like BCH8. - - Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and - trying to use BCH16 (ECC_BYTES=26) ecc-scheme. - Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B - which can be accommodated in the OOB/Spare area of this device - (OOBSIZE=128). So this device can use BCH16 ecc-scheme. diff --git a/dts/Bindings/mtd/gpmc-nor.txt b/dts/Bindings/mtd/gpmc-nor.txt deleted file mode 100644 index 2133be0d52..0000000000 --- a/dts/Bindings/mtd/gpmc-nor.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree bindings for NOR flash connect to TI GPMC - -NOR flash connected to the TI GPMC (found on OMAP boards) are represented as -child nodes of the GPMC controller with a name of "nor". - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Required properties: -- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and - 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml -- gpmc,cs-on-ns: Chip-select assertion time -- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads -- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes -- gpmc,oe-on-ns: Output-enable assertion time -- gpmc,oe-off-ns: Output-enable de-assertion time -- gpmc,we-on-ns Write-enable assertion time -- gpmc,we-off-ns: Write-enable de-assertion time -- gpmc,access-ns: Start cycle to first data capture (read access) -- gpmc,rd-cycle-ns: Total read cycle time -- gpmc,wr-cycle-ns: Total write cycle time -- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml -- reg: Chip-select, base address (relative to chip-select) - and size of NOR flash. Note that base address will be - typically 0 as this is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Optional properties for partition table parsing: -- #address-cells: should be set to 1 -- #size-cells: should be set to 1 - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc", "simple-bus"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0x10000000 0x08000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; -}; diff --git a/dts/Bindings/mtd/gpmc-onenand.txt b/dts/Bindings/mtd/gpmc-onenand.txt deleted file mode 100644 index e9f01a963a..0000000000 --- a/dts/Bindings/mtd/gpmc-onenand.txt +++ /dev/null @@ -1,48 +0,0 @@ -Device tree bindings for GPMC connected OneNANDs - -GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of -the GPMC controller with a name of "onenand". - -All timing relevant properties as well as generic gpmc child properties are -explained in a separate documents - please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Required properties: - - - compatible: "ti,omap2-onenand" - - reg: The CS line the peripheral is connected to - - gpmc,device-width: Width of the ONENAND device connected to the GPMC - in bytes. Must be 1 or 2. - -Optional properties: - - - int-gpios: GPIO specifier for the INT pin. - -For inline partition table parsing (optional): - - - #address-cells: should be set to 1 - - #size-cells: should be set to 1 - -Example for an OMAP3430 board: - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - onenand@0 { - compatible = "ti,omap2-onenand"; - reg = <0 0 0>; /* CS0, offset 0 */ - gpmc,device-width = <2>; - - #address-cells = <1>; - #size-cells = <1>; - - /* partitions go here */ - }; - }; diff --git a/dts/Bindings/mtd/ingenic,nand.yaml b/dts/Bindings/mtd/ingenic,nand.yaml index 89aa3ceda5..9de8ef6e59 100644 --- a/dts/Bindings/mtd/ingenic,nand.yaml +++ b/dts/Bindings/mtd/ingenic,nand.yaml @@ -55,7 +55,7 @@ unevaluatedProperties: false examples: - | - #include + #include memory-controller@13410000 { compatible = "ingenic,jz4780-nemc"; reg = <0x13410000 0x10000>; diff --git a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml index 29c5ef24ac..eab8ea3da1 100644 --- a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings maintainers: - - Christophe Kerello + - Christophe Kerello properties: compatible: diff --git a/dts/Bindings/mtd/ti,gpmc-nand.yaml b/dts/Bindings/mtd/ti,gpmc-nand.yaml new file mode 100644 index 0000000000..beb26b9bcf --- /dev/null +++ b/dts/Bindings/mtd/ti,gpmc-nand.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC NAND Flash controller. + +maintainers: + - Tony Lindgren + - Roger Quadros + +description: + GPMC NAND controller/Flash is represented as a child of the + GPMC controller node. + +properties: + compatible: + const: ti,omap2-nand + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for fifoevent + - description: Interrupt for termcount + + "#address-cells": true + + "#size-cells": true + + ti,nand-ecc-opt: + description: Desired ECC algorithm + $ref: /schemas/types.yaml#/definitions/string + enum: [sw, ham1, bch4, bch8, bch16] + + ti,nand-xfer-type: + description: Data transfer method between controller and chip. + $ref: /schemas/types.yaml#/definitions/string + enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq] + default: prefetch-polled + + ti,elm-id: + description: + phandle to the ELM (Error Location Module). + $ref: /schemas/types.yaml#/definitions/phandle + + nand-bus-width: + description: + Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +allOf: + - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml" + +required: + - compatible + - reg + - ti,nand-ecc-opt + +unevaluatedProperties: false + +examples: + - | + #include + #include + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + #address-cells = <1>; + #size-cells = <1>; + + /* NAND generic properties */ + nand-bus-width = <8>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + + /* GPMC properties*/ + gpmc,device-width = <1>; + + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + }; + }; diff --git a/dts/Bindings/mtd/ti,gpmc-onenand.yaml b/dts/Bindings/mtd/ti,gpmc-onenand.yaml new file mode 100644 index 0000000000..a953f7397c --- /dev/null +++ b/dts/Bindings/mtd/ti,gpmc-onenand.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,gpmc-onenand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OneNAND over Texas Instruments GPMC bus. + +maintainers: + - Tony Lindgren + - Roger Quadros + +description: + GPMC connected OneNAND (found on OMAP boards) are represented + as child nodes of the GPMC controller. + +properties: + compatible: + const: ti,omap2-onenand + + reg: + items: + - description: | + Chip Select number, register offset and size of + OneNAND register window. + + "#address-cells": true + + "#size-cells": true + + int-gpios: + description: GPIO specifier for the INT pin. + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +allOf: + - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml" + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + gpmc: memory-controller@6e000000 { + compatible = "ti,omap3430-gpmc"; + reg = <0x6e000000 0x02d0>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + clocks = <&l3s_clkctrl>; + clock-names = "fck"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ + <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ + + onenand@0,0 { + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00100000>; + }; + + partition@100000 { + label = "config"; + reg = <0x00100000 0x002c0000>; + }; + }; + }; diff --git a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml index 9eb4bb529a..407586bc36 100644 --- a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -15,7 +15,7 @@ properties: oneOf: - const: allwinner,sun8i-a83t-emac - const: allwinner,sun8i-h3-emac - - const: allwinner,sun8i-r40-emac + - const: allwinner,sun8i-r40-gmac - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac - items: @@ -93,7 +93,7 @@ allOf: compatible: contains: enum: - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac then: properties: diff --git a/dts/Bindings/net/asix,ax88796c.yaml b/dts/Bindings/net/asix,ax88796c.yaml new file mode 100644 index 0000000000..699ebf4524 --- /dev/null +++ b/dts/Bindings/net/asix,ax88796c.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/asix,ax88796c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASIX AX88796C SPI Ethernet Adapter + +maintainers: + - Łukasz Stelmach + +description: | + ASIX AX88796C is an Ethernet controller with a built in PHY. This + describes SPI mode of the chip. + + The node for this driver must be a child node of an SPI controller, + hence all mandatory properties described in + ../spi/spi-controller.yaml must be specified. + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + const: asix,ax88796c + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + interrupts: + maxItems: 1 + + reset-gpios: + description: + A GPIO line handling reset of the chip. As the line is active low, + it should be marked GPIO_ACTIVE_LOW. + maxItems: 1 + + local-mac-address: true + + mac-address: true + +required: + - compatible + - reg + - spi-max-frequency + - interrupts + - reset-gpios + +additionalProperties: false + +examples: + # Artik5 eval board + - | + #include + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "asix,ax88796c"; + reg = <0x0>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + interrupt-parent = <&gpx2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <40000000>; + reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/dts/Bindings/net/brcm,bcmgenet.txt b/dts/Bindings/net/brcm,bcmgenet.txt index 33a0d67e4c..0b5994fba3 100644 --- a/dts/Bindings/net/brcm,bcmgenet.txt +++ b/dts/Bindings/net/brcm,bcmgenet.txt @@ -2,7 +2,8 @@ Required properties: - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2", - "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5". + "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or + "brcm,bcm7712-genet-v5". - reg: address and length of the register set for the device - interrupts and/or interrupts-extended: must be two cells, the first cell is the general purpose interrupt line, while the second cell is the diff --git a/dts/Bindings/net/broadcom-bluetooth.yaml b/dts/Bindings/net/broadcom-bluetooth.yaml index fbdc2083be..5aac094fd2 100644 --- a/dts/Bindings/net/broadcom-bluetooth.yaml +++ b/dts/Bindings/net/broadcom-bluetooth.yaml @@ -50,16 +50,29 @@ properties: by interrupts and "host-wakeup" interrupt-names clocks: + minItems: 1 maxItems: 2 description: 1 or 2 clocks as defined in clock-names below, in that order clock-names: description: Names of the 1 to 2 supplied clocks - items: + oneOf: + - const: extclk + deprecated: true + description: Deprecated in favor of txco + - const: txco + description: > + external reference clock (not a standalone crystal) + - const: lpo - - const: extclk + description: > + external low power 32.768 kHz clock + + - items: + - const: txco + - const: lpo vbat-supply: description: phandle to regulator supply for VBAT diff --git a/dts/Bindings/net/dsa/dsa.yaml b/dts/Bindings/net/dsa/dsa.yaml index 16aa192c11..2ad7f79ad3 100644 --- a/dts/Bindings/net/dsa/dsa.yaml +++ b/dts/Bindings/net/dsa/dsa.yaml @@ -46,6 +46,9 @@ patternProperties: type: object description: Ethernet switch ports + allOf: + - $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#" + properties: reg: description: Port number @@ -73,11 +76,14 @@ patternProperties: dsa-tag-protocol: description: Instead of the default, the switch will use this tag protocol if - possible. Useful when a device supports multiple protcols and + possible. Useful when a device supports multiple protocols and the default is incompatible with the Ethernet device. enum: - dsa - edsa + - ocelot + - ocelot-8021q + - seville phy-handle: true @@ -91,6 +97,10 @@ patternProperties: managed: true + rx-internal-delay-ps: true + + tx-internal-delay-ps: true + required: - reg diff --git a/dts/Bindings/net/dsa/nxp,sja1105.yaml b/dts/Bindings/net/dsa/nxp,sja1105.yaml index f978f8719d..24cd733c11 100644 --- a/dts/Bindings/net/dsa/nxp,sja1105.yaml +++ b/dts/Bindings/net/dsa/nxp,sja1105.yaml @@ -74,10 +74,42 @@ properties: - compatible - reg +patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + allOf: + - if: + properties: + phy-mode: + contains: + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id + then: + properties: + rx-internal-delay-ps: + $ref: "#/$defs/internal-delay-ps" + tx-internal-delay-ps: + $ref: "#/$defs/internal-delay-ps" + required: - compatible - reg +$defs: + internal-delay-ps: + description: + Disable tunable delay lines using 0 ps, or enable them and select + the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps + (101.7 degree shift) in increments of 0.9 degrees (20 ps). + enum: + [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840, + 1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080, + 2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260] + unevaluatedProperties: false examples: @@ -97,29 +129,40 @@ examples: port@0 { phy-handle = <&rgmii_phy6>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <0>; }; port@1 { phy-handle = <&rgmii_phy3>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <1>; }; port@2 { phy-handle = <&rgmii_phy4>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <2>; }; port@3 { + phy-handle = <&rgmii_phy4>; phy-mode = "rgmii-id"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <3>; }; port@4 { ethernet = <&enet2>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; reg = <4>; fixed-link { diff --git a/dts/Bindings/net/dsa/qca8k.txt b/dts/Bindings/net/dsa/qca8k.txt deleted file mode 100644 index 8c73f67c43..0000000000 --- a/dts/Bindings/net/dsa/qca8k.txt +++ /dev/null @@ -1,215 +0,0 @@ -* Qualcomm Atheros QCA8xxx switch family - -Required properties: - -- compatible: should be one of: - "qca,qca8327" - "qca,qca8334" - "qca,qca8337" - -- #size-cells: must be 0 -- #address-cells: must be 1 - -Optional properties: - -- reset-gpios: GPIO to be used to reset the whole device - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external -mdio-bus each subnode describing a port needs to have a valid phandle -referencing the internal PHY it is connected to. This is because there's no -N:N mapping of port and PHY id. -To declare the internal mdio-bus configuration, declare a mdio node in the -switch node and declare the phandle for the port referencing the internal -PHY is connected to. In this config a internal mdio-bus is registered and -the mdio MASTER is used as communication. - -Don't use mixed external and internal mdio-bus configurations, as this is -not supported by the hardware. - -The CPU port of this switch is always port 0. - -A CPU port node has the following optional node: - -- fixed-link : Fixed-link subnode describing a link to a non-MDIO - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. - -For QCA8K the 'fixed-link' sub-node supports only the following properties: - -- 'speed' (integer, mandatory), to indicate the link speed. Accepted - values are 10, 100 and 1000 -- 'full-duplex' (boolean, optional), to indicate that full duplex is - used. When absent, half duplex is assumed. - -Examples: - -for the external mdio-bus configuration: - - &mdio0 { - phy_port1: phy@0 { - reg = <0>; - }; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - phy_port4: phy@3 { - reg = <3>; - }; - - phy_port5: phy@4 { - reg = <4>; - }; - - switch@10 { - compatible = "qca,qca8337"; - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - reg = <0x10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = 1000; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&phy_port1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-handle = <&phy_port3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; - phy-handle = <&phy_port4>; - }; - - port@5 { - reg = <5>; - label = "wan"; - phy-handle = <&phy_port5>; - }; - }; - }; - }; - -for the internal master mdio-bus configuration: - - &mdio0 { - switch@10 { - compatible = "qca,qca8337"; - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - reg = <0x10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "cpu"; - ethernet = <&gmac1>; - phy-mode = "rgmii"; - fixed-link { - speed = 1000; - full-duplex; - }; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&phy_port1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&phy_port3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; - phy-mode = "internal"; - phy-handle = <&phy_port4>; - }; - - port@5 { - reg = <5>; - label = "wan"; - phy-mode = "internal"; - phy-handle = <&phy_port5>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy_port1: phy@0 { - reg = <0>; - }; - - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - - phy_port4: phy@3 { - reg = <3>; - }; - - phy_port5: phy@4 { - reg = <4>; - }; - }; - }; - }; diff --git a/dts/Bindings/net/dsa/qca8k.yaml b/dts/Bindings/net/dsa/qca8k.yaml new file mode 100644 index 0000000000..48de0ace26 --- /dev/null +++ b/dts/Bindings/net/dsa/qca8k.yaml @@ -0,0 +1,362 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros QCA83xx switch family + +maintainers: + - John Crispin + +description: + If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode + describing a port needs to have a valid phandle referencing the internal PHY + it is connected to. This is because there is no N:N mapping of port and PHY + ID. To declare the internal mdio-bus configuration, declare an MDIO node in + the switch node and declare the phandle for the port, referencing the internal + PHY it is connected to. In this config, an internal mdio-bus is registered and + the MDIO master is used for communication. Mixed external and internal + mdio-bus configurations are not supported by the hardware. + +properties: + compatible: + oneOf: + - enum: + - qca,qca8327 + - qca,qca8328 + - qca,qca8334 + - qca,qca8337 + description: | + qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package + qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package + qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package + qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package + + reg: + maxItems: 1 + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + qca,ignore-power-on-sel: + $ref: /schemas/types.yaml#/definitions/flag + description: + Ignore power-on pin strapping to configure LED open-drain or EEPROM + presence. This is needed for devices with incorrect configuration or when + the OEM has decided not to use pin strapping and falls back to SW regs. + + qca,led-open-drain: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to + be set, otherwise the driver will fail at probe. This is required if the + OEM does not use pin strapping to set this mode and prefers to set it + using SW regs. The pin strappings related to LED open-drain mode are + B68 on the QCA832x and B49 on the QCA833x. + + mdio: + type: object + description: Qca8k switch have an internal mdio to access switch port. + If this is not present, the legacy mapping is used and the + internal mdio access is used. + With the legacy mapping the reg corresponding to the internal + mdio is the switch reg with an offset of -1. + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?phy@[0-4]$": + type: object + + allOf: + - $ref: "http://devicetree.org/schemas/net/mdio.yaml#" + + properties: + reg: + maxItems: 1 + + required: + - reg + +patternProperties: + "^(ethernet-)?ports$": + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?port@[0-6]$": + type: object + description: Ethernet switch ports + + properties: + reg: + description: Port number + + label: + description: + Describes the label associated with this port, which will become + the netdev name + $ref: /schemas/types.yaml#/definitions/string + + link: + description: + Should be a list of phandles to other switch's DSA port. This + port is used as the outgoing port towards the phandle ports. The + full routing information must be given, not just the one hop + routes to neighbouring switches + $ref: /schemas/types.yaml#/definitions/phandle-array + + ethernet: + description: + Should be a phandle to a valid Ethernet device node. This host + device is what the switch port is connected to + $ref: /schemas/types.yaml#/definitions/phandle + + phy-handle: true + + phy-mode: true + + fixed-link: true + + mac-address: true + + sfp: true + + qca,sgmii-rxclk-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set the receive clock phase to falling edge. Mostly commonly used on + the QCA8327 with CPU port 0 set to SGMII. + + qca,sgmii-txclk-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set the transmit clock phase to falling edge. + + qca,sgmii-enable-pll: + $ref: /schemas/types.yaml#/definitions/flag + description: + For SGMII CPU port, explicitly enable PLL, TX and RX chain along with + Signal Detection. On the QCA8327 this should not be enabled, otherwise + the SGMII port will not initialize. When used on the QCA8337, revision 3 + or greater, a warning will be displayed. When the CPU port is set to + SGMII on the QCA8337, it is advised to set this unless a communication + issue is observed. + + required: + - reg + + additionalProperties: false + +oneOf: + - required: + - ports + - required: + - ethernet-ports + +required: + - compatible + - reg + +additionalProperties: true + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + external_phy_port1: ethernet-phy@0 { + reg = <0>; + }; + + external_phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + external_phy_port3: ethernet-phy@2 { + reg = <2>; + }; + + external_phy_port4: ethernet-phy@3 { + reg = <3>; + }; + + external_phy_port5: ethernet-phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&external_phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&external_phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&external_phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&external_phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&external_phy_port5>; + }; + }; + }; + }; + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&internal_phy_port1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&internal_phy_port2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&internal_phy_port3>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&internal_phy_port4>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&internal_phy_port5>; + }; + + port@6 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "sgmii"; + + qca,sgmii-rxclk-falling-edge; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + internal_phy_port1: ethernet-phy@0 { + reg = <0>; + }; + + internal_phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + internal_phy_port3: ethernet-phy@2 { + reg = <2>; + }; + + internal_phy_port4: ethernet-phy@3 { + reg = <3>; + }; + + internal_phy_port5: ethernet-phy@4 { + reg = <4>; + }; + }; + }; + }; diff --git a/dts/Bindings/net/dsa/realtek-smi.txt b/dts/Bindings/net/dsa/realtek-smi.txt index b6ae8541bd..7959ec2379 100644 --- a/dts/Bindings/net/dsa/realtek-smi.txt +++ b/dts/Bindings/net/dsa/realtek-smi.txt @@ -9,6 +9,7 @@ SMI-based Realtek devices. Required properties: - compatible: must be exactly one of: + "realtek,rtl8365mb" (4+1 ports) "realtek,rtl8366" "realtek,rtl8366rb" (4+1 ports) "realtek,rtl8366s" (4+1 ports) @@ -62,6 +63,8 @@ and subnodes of DSA switches. Examples: +An example for the RTL8366RB: + switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ @@ -151,3 +154,87 @@ switch { }; }; }; + +An example for the RTL8365MB-VC: + +switch { + compatible = "realtek,rtl8365mb"; + mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + + switch_intc: interrupt-controller { + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + port@0 { + reg = <0>; + label = "swp0"; + phy-handle = <ðphy0>; + }; + port@1 { + reg = <1>; + label = "swp1"; + phy-handle = <ðphy1>; + }; + port@2 { + reg = <2>; + label = "swp2"; + phy-handle = <ðphy2>; + }; + port@3 { + reg = <3>; + label = "swp3"; + phy-handle = <ðphy3>; + }; + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: phy@0 { + reg = <0>; + interrupt-parent = <&switch_intc>; + interrupts = <0>; + }; + ethphy1: phy@1 { + reg = <1>; + interrupt-parent = <&switch_intc>; + interrupts = <1>; + }; + ethphy2: phy@2 { + reg = <2>; + interrupt-parent = <&switch_intc>; + interrupts = <2>; + }; + ethphy3: phy@3 { + reg = <3>; + interrupt-parent = <&switch_intc>; + interrupts = <3>; + }; + }; +}; diff --git a/dts/Bindings/net/gpmc-eth.txt b/dts/Bindings/net/gpmc-eth.txt deleted file mode 100644 index 32821066a8..0000000000 --- a/dts/Bindings/net/gpmc-eth.txt +++ /dev/null @@ -1,97 +0,0 @@ -Device tree bindings for Ethernet chip connected to TI GPMC - -Besides being used to interface with external memory devices, the -General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices -such as ethernet controllers to processors using the TI GPMC as a data bus. - -Ethernet controllers connected to TI GPMC are represented as child nodes of -the GPMC controller with an "ethernet" name. - -All timing relevant properties as well as generic GPMC child properties are -explained in a separate documents. Please refer to -Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -For the properties relevant to the ethernet controller connected to the GPMC -refer to the binding documentation of the device. For example, the documentation -for the SMSC 911x is Documentation/devicetree/bindings/net/smsc,lan9115.yaml - -Child nodes need to specify the GPMC bus address width using the "bank-width" -property but is possible that an ethernet controller also has a property to -specify the I/O registers address width. Even when the GPMC has a maximum 16-bit -address width, it supports devices with 32-bit word registers. -For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an -OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". - -Required properties: -- bank-width: Address width of the device in bytes. GPMC supports 8-bit - and 16-bit devices and so must be either 1 or 2 bytes. -- compatible: Compatible string property for the ethernet child device. -- gpmc,cs-on-ns: Chip-select assertion time -- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads -- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes -- gpmc,oe-on-ns: Output-enable assertion time -- gpmc,oe-off-ns: Output-enable de-assertion time -- gpmc,we-on-ns: Write-enable assertion time -- gpmc,we-off-ns: Write-enable de-assertion time -- gpmc,access-ns: Start cycle to first data capture (read access) -- gpmc,rd-cycle-ns: Total read cycle time -- gpmc,wr-cycle-ns: Total write cycle time -- reg: Chip-select, base address (relative to chip-select) - and size of the memory mapped for the device. - Note that base address will be typically 0 as this - is the start of the chip-select. - -Optional properties: -- gpmc,XXX Additional GPMC timings and settings parameters. See - Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt - -Example: - -gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x1000>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <5 0 0x2c000000 0x1000000>; - - ethernet@5,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <5 0 0xff>; - bank-width = <2>; - - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - interrupt-parent = <&gpio6>; - interrupts = <16>; - vmmc-supply = <&vddvario>; - vmmc_aux-supply = <&vdd33a>; - reg-io-width = <4>; - - smsc,save-mac-address; - }; -}; diff --git a/dts/Bindings/net/ingenic,mac.yaml b/dts/Bindings/net/ingenic,mac.yaml index d08a88125a..8e52b2e683 100644 --- a/dts/Bindings/net/ingenic,mac.yaml +++ b/dts/Bindings/net/ingenic,mac.yaml @@ -58,7 +58,7 @@ additionalProperties: false examples: - | - #include + #include mac: ethernet@134b0000 { compatible = "ingenic,x1000-mac"; diff --git a/dts/Bindings/net/lantiq,etop-xway.yaml b/dts/Bindings/net/lantiq,etop-xway.yaml new file mode 100644 index 0000000000..437502c5ca --- /dev/null +++ b/dts/Bindings/net/lantiq,etop-xway.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq Xway ETOP Ethernet driver + +maintainers: + - John Crispin + +properties: + $nodename: + pattern: "^ethernet@[0-9a-f]+$" + + compatible: + const: lantiq,etop-xway + + reg: + maxItems: 1 + + interrupts: + items: + - description: TX interrupt + - description: RX interrupt + + interrupt-names: + items: + - const: tx + - const: rx + + lantiq,tx-burst-length: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + TX programmable burst length. + enum: [2, 4, 8] + + lantiq,rx-burst-length: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RX programmable burst length. + enum: [2, 4, 8] + + phy-mode: true + +required: + - compatible + - reg + - interrupt-parent + - interrupts + - interrupt-names + - lantiq,tx-burst-length + - lantiq,rx-burst-length + - phy-mode + +additionalProperties: false + +examples: + - | + ethernet@e180000 { + compatible = "lantiq,etop-xway"; + reg = <0xe180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73>, <78>; + interrupt-names = "tx", "rx"; + lantiq,tx-burst-length = <8>; + lantiq,rx-burst-length = <8>; + phy-mode = "rmii"; + }; diff --git a/dts/Bindings/net/lantiq,xrx200-net.txt b/dts/Bindings/net/lantiq,xrx200-net.txt deleted file mode 100644 index 5ff5e68bbb..0000000000 --- a/dts/Bindings/net/lantiq,xrx200-net.txt +++ /dev/null @@ -1,21 +0,0 @@ -Lantiq xRX200 GSWIP PMAC Ethernet driver -================================== - -Required properties: - -- compatible : "lantiq,xrx200-net" for the PMAC of the embedded - : GSWIP in the xXR200 -- reg : memory range of the PMAC core inside of the GSWIP core -- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for - : the TX interrupt and "rx" for the RX interrupt. - -Example: - -ethernet@e10b308 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-net"; - reg = <0xe10b308 0xcf8>; - interrupts = <73>, <72>; - interrupt-names = "tx", "rx"; -}; diff --git a/dts/Bindings/net/lantiq,xrx200-net.yaml b/dts/Bindings/net/lantiq,xrx200-net.yaml new file mode 100644 index 0000000000..7bc074a423 --- /dev/null +++ b/dts/Bindings/net/lantiq,xrx200-net.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/lantiq,xrx200-net.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq xRX200 GSWIP PMAC Ethernet driver + +maintainers: + - Hauke Mehrtens + +properties: + $nodename: + pattern: "^ethernet@[0-9a-f]+$" + + compatible: + const: lantiq,xrx200-net + + reg: + maxItems: 1 + + interrupts: + items: + - description: TX interrupt + - description: RX interrupt + + interrupt-names: + items: + - const: tx + - const: rx + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - interrupt-parent + - interrupts + - interrupt-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + ethernet@e10b308 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = <0xe10b308 0xcf8>; + interrupt-parent = <&icu0>; + interrupts = <73>, <72>; + interrupt-names = "tx", "rx"; + }; diff --git a/dts/Bindings/net/macb.txt b/dts/Bindings/net/macb.txt index af9df2f01a..a1b06fd196 100644 --- a/dts/Bindings/net/macb.txt +++ b/dts/Bindings/net/macb.txt @@ -30,6 +30,10 @@ Required properties: Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +Optional properties: +- mdio: node containing PHY children. If this node is not present, then PHYs + will be direct children. + The MAC address will be determined using the optional properties defined in ethernet.txt. diff --git a/dts/Bindings/net/marvell-bluetooth.txt b/dts/Bindings/net/marvell-bluetooth.txt deleted file mode 100644 index 0e28422960..0000000000 --- a/dts/Bindings/net/marvell-bluetooth.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Bluetooth Chips ------------------------ - -This documents the binding structure and common properties for serial -attached Marvell Bluetooth devices. The following chips are included in -this binding: - -* Marvell 88W8897 Bluetooth devices - -Required properties: - - compatible: should be: - "mrvl,88w8897" - -Optional properties: -None so far - -Example: - -&serial0 { - compatible = "ns16550a"; - ... - bluetooth { - compatible = "mrvl,88w8897"; - }; -}; diff --git a/dts/Bindings/net/marvell-bluetooth.yaml b/dts/Bindings/net/marvell-bluetooth.yaml new file mode 100644 index 0000000000..309ef21a1e --- /dev/null +++ b/dts/Bindings/net/marvell-bluetooth.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/marvell-bluetooth.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Marvell Bluetooth chips + +description: | + This documents the binding structure and common properties for serial + attached Marvell Bluetooth devices. + +maintainers: + - Rob Herring + +properties: + compatible: + const: mrvl,88w8897 + +required: + - compatible + +additionalProperties: false + +examples: + - | + serial { + bluetooth { + compatible = "mrvl,88w8897"; + }; + }; diff --git a/dts/Bindings/net/nfc/marvell,nci.yaml b/dts/Bindings/net/nfc/marvell,nci.yaml new file mode 100644 index 0000000000..15a45db389 --- /dev/null +++ b/dts/Bindings/net/nfc/marvell,nci.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/marvell,nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell International Ltd. NCI NFC controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - marvell,nfc-i2c + - marvell,nfc-spi + - marvell,nfc-uart + + hci-muxed: + type: boolean + description: | + Specifies that the chip is muxing NCI over HCI frames + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + reset-n-io: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + maxItems: 1 + description: | + Output GPIO pin used to reset the chip (active low) + + i2c-int-falling: + type: boolean + description: | + For I2C type of connection. Specifies that the chip read event shall be + trigged on falling edge. + + i2c-int-rising: + type: boolean + description: | + For I2C type of connection. Specifies that the chip read event shall be + trigged on rising edge. + + break-control: + type: boolean + description: | + For UART type of connection. Specifies that the chip needs specific break + management. + + flow-control: + type: boolean + description: | + For UART type of connection. Specifies that the chip is using RTS/CTS. + + spi-cpha: true + spi-cpol: true + spi-max-frequency: true + +required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + const: marvell,nfc-i2c + then: + properties: + break-control: false + flow-control: false + spi-cpha: false + spi-cpol: false + spi-max-frequency: false + required: + - reg + + - if: + properties: + compatible: + contains: + const: marvell,nfc-spi + then: + properties: + break-control: false + flow-control: false + i2c-int-falling: false + i2c-int-rising: false + required: + - reg + + - if: + properties: + compatible: + contains: + const: marvell,nfc-uart + then: + properties: + i2c-int-falling: false + i2c-int-rising: false + interrupts: false + spi-cpha: false + spi-cpol: false + spi-max-frequency: false + reg: false + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@8 { + compatible = "marvell,nfc-i2c"; + reg = <0x8>; + + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + i2c-int-rising; + + reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; + + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "marvell,nfc-spi"; + reg = <0>; + + spi-max-frequency = <3000000>; + spi-cpha; + spi-cpol; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + + reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; + + - | + #include + + uart { + nfc { + compatible = "marvell,nfc-uart"; + + reset-n-io = <&gpio3 16 GPIO_ACTIVE_HIGH>; + + hci-muxed; + flow-control; + }; + }; diff --git a/dts/Bindings/net/nfc/nfcmrvl.txt b/dts/Bindings/net/nfc/nfcmrvl.txt deleted file mode 100644 index c9b35251bb..0000000000 --- a/dts/Bindings/net/nfc/nfcmrvl.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Marvell International Ltd. NCI NFC Controller - -Required properties: -- compatible: Should be: - - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices - - "marvell,nfc-i2c" for I2C devices - - "marvell,nfc-spi" for SPI devices - -Optional SoC specific properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- reset-n-io: Output GPIO pin used to reset the chip (active low). -- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. - -Optional UART-based chip specific properties: -- flow-control: Specifies that the chip is using RTS/CTS. -- break-control: Specifies that the chip needs specific break management. - -Optional I2C-based chip specific properties: -- i2c-int-falling: Specifies that the chip read event shall be trigged on - falling edge. -- i2c-int-rising: Specifies that the chip read event shall be trigged on - rising edge. - -Example (for ARM-based BeagleBoard Black with 88W8887 on UART5): - -&uart5 { - - nfcmrvluart: nfcmrvluart@5 { - compatible = "marvell,nfc-uart"; - - reset-n-io = <&gpio3 16 0>; - - hci-muxed; - flow-control; - } -}; - - -Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1): - -&i2c1 { - clock-frequency = <400000>; - - nfcmrvli2c0: i2c@1 { - compatible = "marvell,nfc-i2c"; - - reg = <0x8>; - - /* I2C INT configuration */ - interrupt-parent = <&gpio3>; - interrupts = <21 0>; - - /* I2C INT trigger configuration */ - i2c-int-rising; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; - - -Example (for ARM-based BeagleBoard Black on SPI0): - -&spi0 { - - mrvlnfcspi0: spi@0 { - compatible = "marvell,nfc-spi"; - - reg = <0>; - - /* SPI Bus configuration */ - spi-max-frequency = <3000000>; - spi-cpha; - spi-cpol; - - /* SPI INT configuration */ - interrupt-parent = <&gpio1>; - interrupts = <17 0>; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; diff --git a/dts/Bindings/net/nfc/nxp,nci.yaml b/dts/Bindings/net/nfc/nxp,nci.yaml new file mode 100644 index 0000000000..7465aea2e1 --- /dev/null +++ b/dts/Bindings/net/nfc/nxp,nci.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors NCI NFC controller + +maintainers: + - Charles Gorand + - Krzysztof Kozlowski + +properties: + compatible: + oneOf: + - const: nxp,nxp-nci-i2c + - items: + - const: nxp,pn547 + - const: nxp,nxp-nci-i2c + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the controller + + firmware-gpios: + description: Output GPIO pin used to enter firmware download mode + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - enable-gpios + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@29 { + compatible = "nxp,nxp-nci-i2c"; + + reg = <0x29>; + + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/net/nfc/nxp,pn532.yaml b/dts/Bindings/net/nfc/nxp,pn532.yaml new file mode 100644 index 0000000000..d8ba5a18db --- /dev/null +++ b/dts/Bindings/net/nfc/nxp,pn532.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,pn532.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors PN532 NFC controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + oneOf: + - const: nxp,pn532 + - description: Deprecated bindings + enum: + - nxp,pn532-i2c + - nxp,pn533-i2c + deprecated: true + + interrupts: + description: Required if connected via I2C + maxItems: 1 + + reg: + description: Required if connected via I2C + maxItems: 1 + +required: + - compatible + +dependencies: + interrupts: [ 'reg' ] + +additionalProperties: false + +examples: + # PN532 on I2C bus + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@24 { + compatible = "nxp,pn532"; + + reg = <0x24>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + # PN532 connected via UART + - | + serial@49042000 { + reg = <0x49042000 0x400>; + + nfc { + compatible = "nxp,pn532"; + }; + }; diff --git a/dts/Bindings/net/nfc/nxp,pn544.yaml b/dts/Bindings/net/nfc/nxp,pn544.yaml new file mode 100644 index 0000000000..d520414de4 --- /dev/null +++ b/dts/Bindings/net/nfc/nxp,pn544.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,pn544.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors PN544 NFC Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: nxp,pn544-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the PN544 + maxItems: 1 + + firmware-gpios: + description: Output GPIO pin used to enter firmware download mode + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - enable-gpios + - firmware-gpios + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/net/nfc/nxp-nci.txt b/dts/Bindings/net/nfc/nxp-nci.txt deleted file mode 100644 index 285a37c2f1..0000000000 --- a/dts/Bindings/net/nfc/nxp-nci.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors NXP NCI NFC Controllers - -Required properties: -- compatible: Should be "nxp,nxp-nci-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the chip - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2): - -&i2c2 { - - - npc100: npc100@29 { - - compatible = "nxp,nxp-nci-i2c"; - - reg = <0x29>; - clock-frequency = <100000>; - - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/dts/Bindings/net/nfc/pn532.txt b/dts/Bindings/net/nfc/pn532.txt deleted file mode 100644 index a5507dc499..0000000000 --- a/dts/Bindings/net/nfc/pn532.txt +++ /dev/null @@ -1,46 +0,0 @@ -* NXP Semiconductors PN532 NFC Controller - -Required properties: -- compatible: Should be - - "nxp,pn532" Place a node with this inside the devicetree node of the bus - where the NFC chip is connected to. - Currently the kernel has phy bindings for uart and i2c. - - "nxp,pn532-i2c" (DEPRECATED) only works for the i2c binding. - - "nxp,pn533-i2c" (DEPRECATED) only works for the i2c binding. - -Required properties if connected on i2c: -- clock-frequency: I²C work frequency. -- reg: for the I²C bus address. This is fixed at 0x24 for the PN532. -- interrupts: GPIO interrupt to which the chip is connected - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN532 on I2C2): - -&i2c2 { - - - pn532: nfc@24 { - - compatible = "nxp,pn532"; - - reg = <0x24>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - }; -}; - -Example (for PN532 connected via uart): - -uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - - pn532: nfc { - compatible = "nxp,pn532"; - }; -}; diff --git a/dts/Bindings/net/nfc/pn544.txt b/dts/Bindings/net/nfc/pn544.txt deleted file mode 100644 index 2bd82562ce..0000000000 --- a/dts/Bindings/net/nfc/pn544.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors PN544 NFC Controller - -Required properties: -- compatible: Should be "nxp,pn544-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the PN544 -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN544 on I2C2): - -&i2c2 { - - - pn544: pn544@28 { - - compatible = "nxp,pn544-i2c"; - - reg = <0x28>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/dts/Bindings/net/nfc/st,st-nci.yaml b/dts/Bindings/net/nfc/st,st-nci.yaml new file mode 100644 index 0000000000..a6a1bc788d --- /dev/null +++ b/dts/Bindings/net/nfc/st,st-nci.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics ST NCI NFC controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - st,st21nfcb-i2c + - st,st21nfcb-spi + - st,st21nfcc-i2c + + reset-gpios: + description: Output GPIO pin used for resetting the controller + + ese-present: + type: boolean + description: | + Specifies that an ese is physically connected to the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + spi-max-frequency: true + + uicc-present: + type: boolean + description: | + Specifies that the uicc swp signal can be physically connected to the + controller + +required: + - compatible + - interrupts + - reg + - reset-gpios + +if: + properties: + compatible: + contains: + enum: + - st,st21nfcb-i2c + - st,st21nfcc-i2c +then: + properties: + spi-max-frequency: false +else: + required: + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@8 { + compatible = "st,st21nfcb-i2c"; + reg = <0x08>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; + + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "st,st21nfcb-spi"; + reg = <0>; + + spi-max-frequency = <4000000>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; diff --git a/dts/Bindings/net/nfc/st,st21nfca.yaml b/dts/Bindings/net/nfc/st,st21nfca.yaml new file mode 100644 index 0000000000..4356eacde8 --- /dev/null +++ b/dts/Bindings/net/nfc/st,st21nfca.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st21nfca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SAS ST21NFCA NFC controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: st,st21nfca-i2c + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the controller + + ese-present: + type: boolean + description: | + Specifies that an ese is physically connected to the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + uicc-present: + type: boolean + description: | + Specifies that the uicc swp signal can be physically connected to the + controller + +required: + - compatible + - enable-gpios + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@1 { + compatible = "st,st21nfca-i2c"; + reg = <0x1>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; diff --git a/dts/Bindings/net/nfc/st,st95hf.yaml b/dts/Bindings/net/nfc/st,st95hf.yaml new file mode 100644 index 0000000000..d3bca37603 --- /dev/null +++ b/dts/Bindings/net/nfc/st,st95hf.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st95hf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics ST95HF NFC controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: st,st95hf + + enable-gpio: + description: Output GPIO pin used for enabling/disabling the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + st95hfvin-supply: + description: ST95HF transceiver's Vin regulator supply + + spi-max-frequency: true + +required: + - compatible + - enable-gpio + - interrupts + - reg + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0{ + compatible = "st,st95hf"; + reg = <0>; + + spi-max-frequency = <1000000>; + enable-gpio = <&pio4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&pio0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/dts/Bindings/net/nfc/st-nci-i2c.txt b/dts/Bindings/net/nfc/st-nci-i2c.txt deleted file mode 100644 index baa8f8133d..0000000000 --- a/dts/Bindings/net/nfc/st-nci-i2c.txt +++ /dev/null @@ -1,38 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): - -&i2c2 { - - - st21nfcb: st21nfcb@8 { - - compatible = "st,st21nfcb-i2c"; - - reg = <0x08>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/dts/Bindings/net/nfc/st-nci-spi.txt b/dts/Bindings/net/nfc/st-nci-spi.txt deleted file mode 100644 index d33343330b..0000000000 --- a/dts/Bindings/net/nfc/st-nci-spi.txt +++ /dev/null @@ -1,36 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-spi" -- spi-max-frequency: Maximum SPI frequency (<= 4000000). -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4): - -&mcspi4 { - - - st21nfcb: st21nfcb@0 { - - compatible = "st,st21nfcb-spi"; - - clock-frequency = <4000000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/dts/Bindings/net/nfc/st21nfca.txt b/dts/Bindings/net/nfc/st21nfca.txt deleted file mode 100644 index b8bd90f80e..0000000000 --- a/dts/Bindings/net/nfc/st21nfca.txt +++ /dev/null @@ -1,37 +0,0 @@ -* STMicroelectronics SAS. ST21NFCA NFC Controller - -Required properties: -- compatible: Should be "st,st21nfca-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- enable-gpios: Output GPIO pin used for enabling/disabling the ST21NFCA - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2): - -&i2c2 { - - - st21nfca: st21nfca@1 { - - compatible = "st,st21nfca-i2c"; - - reg = <0x01>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/dts/Bindings/net/nfc/st95hf.txt b/dts/Bindings/net/nfc/st95hf.txt deleted file mode 100644 index 3f373a1e20..0000000000 --- a/dts/Bindings/net/nfc/st95hf.txt +++ /dev/null @@ -1,45 +0,0 @@ -* STMicroelectronics : NFC Transceiver ST95HF - -ST NFC Transceiver is required to attach with SPI bus. -ST95HF node should be defined in DT as SPI slave device of SPI -master with which ST95HF transceiver is physically connected. -The properties defined below are required to be the part of DT -to include ST95HF transceiver into the platform. - -Required properties: -=================== -- reg: Address of SPI slave "ST95HF transceiver" on SPI master bus. - -- compatible: should be "st,st95hf" for ST95HF NFC transceiver - -- spi-max-frequency: Max. operating SPI frequency for ST95HF - transceiver. - -- enable-gpio: GPIO line to enable ST95HF transceiver. - -- interrupts : Standard way to define ST95HF transceiver's out - interrupt. - -Optional property: -================= -- st95hfvin-supply : This is an optional property. It contains a - phandle to ST95HF transceiver's regulator supply node in DT. - -Example: -======= -spi@9840000 { - reg = <0x9840000 0x110>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&pio0 4>; - - st95hf@0{ - reg = <0>; - compatible = "st,st95hf"; - spi-max-frequency = <1000000>; - enable-gpio = <&pio4 0>; - interrupt-parent = <&pio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - }; - -}; diff --git a/dts/Bindings/net/nfc/ti,trf7970a.yaml b/dts/Bindings/net/nfc/ti,trf7970a.yaml new file mode 100644 index 0000000000..40da2ac989 --- /dev/null +++ b/dts/Bindings/net/nfc/ti,trf7970a.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/ti,trf7970a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TRF7970A RFID/NFC/15693 Transceiver + +maintainers: + - Krzysztof Kozlowski + - Mark Greer + +properties: + compatible: + const: ti,trf7970a + + autosuspend-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specify autosuspend delay in milliseconds. + + clock-frequency: + description: | + Set to specify that the input frequency to the trf7970a is 13560000Hz or + 27120000Hz + + en2-rf-quirk: + type: boolean + description: | + Specify that the trf7970a being used has the "EN2 RF" erratum + + interrupts: + maxItems: 1 + + irq-status-read-quirk: + type: boolean + description: | + Specify that the trf7970a being used has the "IRQ Status Read" erratum + + reg: + maxItems: 1 + + spi-max-frequency: true + + ti,enable-gpios: + minItems: 1 + maxItems: 2 + description: | + One or two GPIO entries used for 'EN' and 'EN2' pins on the TRF7970A. EN2 + is optional. + + vdd-io-supply: + description: | + Regulator specifying voltage for VDD-IO + + vin-supply: + description: | + Regulator for supply voltage to VIN pin + +required: + - compatible + - interrupts + - reg + - spi-max-frequency + - ti,enable-gpios + - vin-supply + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&trf7970a_default>; + spi-max-frequency = <2000000>; + interrupt-parent = <&gpio2>; + interrupts = <14 0>; + + ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>, + <&gpio2 5 GPIO_ACTIVE_HIGH>; + vin-supply = <&ldo3_reg>; + vdd-io-supply = <&ldo2_reg>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + clock-frequency = <27120000>; + }; + }; diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt deleted file mode 100644 index ba1934b950..0000000000 --- a/dts/Bindings/net/nfc/trf7970a.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments TRF7970A RFID/NFC/15693 Transceiver - -Required properties: -- compatible: Should be "ti,trf7970a". -- spi-max-frequency: Maximum SPI frequency (<= 2000000). -- interrupts: A single interrupt specifier. -- ti,enable-gpios: One or two GPIO entries used for 'EN' and 'EN2' pins on the - TRF7970A. EN2 is optional. -- vin-supply: Regulator for supply voltage to VIN pin - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- autosuspend-delay: Specify autosuspend delay in milliseconds. -- irq-status-read-quirk: Specify that the trf7970a being used has the - "IRQ Status Read" erratum. -- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" - erratum. -- vdd-io-supply: Regulator specifying voltage for vdd-io -- clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz - -Example (for ARM-based BeagleBone with TRF7970A on SPI1): - -&spi1 { - - nfc@0 { - compatible = "ti,trf7970a"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&trf7970a_default>; - spi-max-frequency = <2000000>; - interrupt-parent = <&gpio2>; - interrupts = <14 0>; - ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>, - <&gpio2 5 GPIO_ACTIVE_HIGH>; - vin-supply = <&ldo3_reg>; - vdd-io-supply = <&ldo2_reg>; - autosuspend-delay = <30000>; - irq-status-read-quirk; - en2-rf-quirk; - clock-frequency = <27120000>; - }; -}; diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml index b8a0b392b2..b86edf67ce 100644 --- a/dts/Bindings/net/qcom,ipa.yaml +++ b/dts/Bindings/net/qcom,ipa.yaml @@ -64,7 +64,8 @@ properties: - const: gsi iommus: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 diff --git a/dts/Bindings/net/qcom,ipq8064-mdio.yaml b/dts/Bindings/net/qcom,ipq8064-mdio.yaml index 948677ade6..d7748dd331 100644 --- a/dts/Bindings/net/qcom,ipq8064-mdio.yaml +++ b/dts/Bindings/net/qcom,ipq8064-mdio.yaml @@ -51,6 +51,9 @@ examples: switch@10 { compatible = "qca,qca8337"; reg = <0x10>; - /* ... */ + + ports { + /* ... */ + }; }; }; diff --git a/dts/Bindings/net/realtek-bluetooth.yaml b/dts/Bindings/net/realtek-bluetooth.yaml index 0634e69dd9..157d606bf9 100644 --- a/dts/Bindings/net/realtek-bluetooth.yaml +++ b/dts/Bindings/net/realtek-bluetooth.yaml @@ -34,6 +34,8 @@ properties: maxItems: 1 description: GPIO specifier, used to wakeup the host processor + max-speed: true + required: - compatible diff --git a/dts/Bindings/net/renesas,ether.yaml b/dts/Bindings/net/renesas,ether.yaml index c101a1ec84..06b38c9bc6 100644 --- a/dts/Bindings/net/renesas,ether.yaml +++ b/dts/Bindings/net/renesas,ether.yaml @@ -100,15 +100,18 @@ additionalProperties: false examples: # Lager board - | - #include - #include + #include + #include + #include + #include ethernet@ee700000 { compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether"; reg = <0xee700000 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; phy-handle = <&phy1>; renesas,ether-link-active-low; @@ -116,8 +119,12 @@ examples: #size-cells = <0>; phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; }; }; diff --git a/dts/Bindings/net/renesas,etheravb.yaml b/dts/Bindings/net/renesas,etheravb.yaml index 4c927d2c17..bda821065a 100644 --- a/dts/Bindings/net/renesas,etheravb.yaml +++ b/dts/Bindings/net/renesas,etheravb.yaml @@ -287,6 +287,7 @@ examples: "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; iommus = <&ipmmu_ds0 16>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; @@ -298,6 +299,8 @@ examples: #size-cells = <0>; phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; diff --git a/dts/Bindings/net/snps,dwmac.yaml b/dts/Bindings/net/snps,dwmac.yaml index c115c95ee5..7ae70dc27f 100644 --- a/dts/Bindings/net/snps,dwmac.yaml +++ b/dts/Bindings/net/snps,dwmac.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare MAC Device Tree Bindings maintainers: - - Alexandre Torgue + - Alexandre Torgue - Giuseppe Cavallaro - Jose Abreu @@ -50,7 +50,7 @@ properties: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - loongson,ls2k-dwmac @@ -318,7 +318,7 @@ allOf: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - ingenic,jz4775-mac @@ -366,7 +366,7 @@ allOf: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - loongson,ls2k-dwmac diff --git a/dts/Bindings/net/socionext,uniphier-ave4.yaml b/dts/Bindings/net/socionext,uniphier-ave4.yaml index 8a03a24a20..6bc61c4241 100644 --- a/dts/Bindings/net/socionext,uniphier-ave4.yaml +++ b/dts/Bindings/net/socionext,uniphier-ave4.yaml @@ -24,6 +24,7 @@ properties: - socionext,uniphier-ld11-ave4 - socionext,uniphier-ld20-ave4 - socionext,uniphier-pxs3-ave4 + - socionext,uniphier-nx1-ave4 reg: maxItems: 1 diff --git a/dts/Bindings/net/stm32-dwmac.yaml b/dts/Bindings/net/stm32-dwmac.yaml index d3f05d5934..577f4e2844 100644 --- a/dts/Bindings/net/stm32-dwmac.yaml +++ b/dts/Bindings/net/stm32-dwmac.yaml @@ -8,8 +8,8 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STM32 / MCU DWMAC glue layer controller maintainers: - - Alexandre Torgue - - Christophe Roullier + - Alexandre Torgue + - Christophe Roullier description: This file documents platform glue layer for stmmac. diff --git a/dts/Bindings/net/ti,bluetooth.yaml b/dts/Bindings/net/ti,bluetooth.yaml new file mode 100644 index 0000000000..81616f9fb4 --- /dev/null +++ b/dts/Bindings/net/ti,bluetooth.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,bluetooth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Bluetooth Chips + +maintainers: + - David Lechner + +description: | + This documents the binding structure and common properties for serial + attached TI Bluetooth devices. The following chips are included in this + binding: + + * TI CC256x Bluetooth devices + * TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices + + TI WiLink devices have a UART interface for providing Bluetooth, FM radio, + and GPS over what's called "shared transport". The shared transport is + standard BT HCI protocol with additional channels for the other functions. + + TI WiLink devices also have a separate WiFi interface as described in + wireless/ti,wlcore.yaml. + + This bindings follows the UART slave device binding in ../serial/serial.yaml. + +properties: + compatible: + enum: + - ti,cc2560 + - ti,wl1271-st + - ti,wl1273-st + - ti,wl1281-st + - ti,wl1283-st + - ti,wl1285-st + - ti,wl1801-st + - ti,wl1805-st + - ti,wl1807-st + - ti,wl1831-st + - ti,wl1835-st + - ti,wl1837-st + + enable-gpios: + maxItems: 1 + + vio-supply: + description: Vio input supply (1.8V) + + vbat-supply: + description: Vbat input supply (2.9-4.8V) + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ext_clock + + max-speed: + default: 3000000 + + nvmem-cells: + maxItems: 1 + description: + Nvmem data cell that contains a 6 byte BD address with the most + significant byte first (big-endian). + + nvmem-cell-names: + items: + - const: bd-address + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + serial { + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + clocks = <&clk32k_wl18xx>; + clock-names = "ext_clock"; + nvmem-cells = <&bd_address>; + nvmem-cell-names = "bd-address"; + }; + }; diff --git a/dts/Bindings/net/ti-bluetooth.txt b/dts/Bindings/net/ti-bluetooth.txt deleted file mode 100644 index f48c17b38f..0000000000 --- a/dts/Bindings/net/ti-bluetooth.txt +++ /dev/null @@ -1,60 +0,0 @@ -Texas Instruments Bluetooth Chips ---------------------------------- - -This documents the binding structure and common properties for serial -attached TI Bluetooth devices. The following chips are included in this -binding: - -* TI CC256x Bluetooth devices -* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices - -TI WiLink devices have a UART interface for providing Bluetooth, FM radio, -and GPS over what's called "shared transport". The shared transport is -standard BT HCI protocol with additional channels for the other functions. - -TI WiLink devices also have a separate WiFi interface as described in -wireless/ti,wlcore.txt. - -This bindings follows the UART slave device binding in ../serial/serial.yaml. - -Required properties: - - compatible: should be one of the following: - "ti,cc2560" - "ti,wl1271-st" - "ti,wl1273-st" - "ti,wl1281-st" - "ti,wl1283-st" - "ti,wl1285-st" - "ti,wl1801-st" - "ti,wl1805-st" - "ti,wl1807-st" - "ti,wl1831-st" - "ti,wl1835-st" - "ti,wl1837-st" - -Optional properties: - - enable-gpios : GPIO signal controlling enabling of BT. Active high. - - vio-supply : Vio input supply (1.8V) - - vbat-supply : Vbat input supply (2.9-4.8V) - - clocks : Must contain an entry, for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names : Must include the following entry: - "ext_clock" (External clock provided to the TI combo chip). - - nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address - with the most significant byte first (big-endian). - - nvmem-cell-names: "bd-address" (required when nvmem-cells is specified) - -Example: - -&serial0 { - compatible = "ns16550a"; - ... - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - clocks = <&clk32k_wl18xx>; - clock-names = "ext_clock"; - nvmem-cells = <&bd_address>; - nvmem-cell-names = "bd-address"; - }; -}; diff --git a/dts/Bindings/net/wireless/esp,esp8089.txt b/dts/Bindings/net/wireless/esp,esp8089.txt deleted file mode 100644 index 6830c4786f..0000000000 --- a/dts/Bindings/net/wireless/esp,esp8089.txt +++ /dev/null @@ -1,30 +0,0 @@ -Espressif ESP8089 wireless SDIO devices - -This node provides properties for controlling the ESP8089 wireless device. -The node is expected to be specified as a child node to the SDIO controller -that connects the device to the system. - -Required properties: - - - compatible : Should be "esp,esp8089". - -Optional properties: - - esp,crystal-26M-en: Integer value for the crystal_26M_en firmware parameter - -Example: - -&mmc1 { - #address-cells = <1>; - #size-cells = <0>; - - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; diff --git a/dts/Bindings/net/wireless/esp,esp8089.yaml b/dts/Bindings/net/wireless/esp,esp8089.yaml new file mode 100644 index 0000000000..284ef45add --- /dev/null +++ b/dts/Bindings/net/wireless/esp,esp8089.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/esp,esp8089.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Espressif ESP8089 Device Tree Bindings + +maintainers: + - Hans de Goede + +properties: + compatible: + const: esp,esp8089 + + reg: + maxItems: 1 + + esp,crystal-26M-en: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Value for the crystal_26M_en firmware parameter + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + mmc { + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; + }; + +... diff --git a/dts/Bindings/net/wireless/mediatek,mt76.yaml b/dts/Bindings/net/wireless/mediatek,mt76.yaml index 3e2c2e4317..1489d3c1cd 100644 --- a/dts/Bindings/net/wireless/mediatek,mt76.yaml +++ b/dts/Bindings/net/wireless/mediatek,mt76.yaml @@ -47,6 +47,11 @@ properties: ieee80211-freq-limit: true + mediatek,eeprom-data: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + EEPROM data embedded as array. + mediatek,mtd-eeprom: $ref: /schemas/types.yaml#/definitions/phandle-array description: diff --git a/dts/Bindings/net/wireless/qca,ath9k.txt b/dts/Bindings/net/wireless/qca,ath9k.txt deleted file mode 100644 index aaaeeb5f93..0000000000 --- a/dts/Bindings/net/wireless/qca,ath9k.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Qualcomm Atheros ath9k wireless devices - -This node provides properties for configuring the ath9k wireless device. The -node is expected to be specified as a child node of the PCI controller to -which the wireless chip is connected. - -Required properties: -- compatible: For PCI and PCIe devices this should be an identifier following - the format as defined in "PCI Bus Binding to Open Firmware" - Revision 2.1. One of the possible formats is "pciVVVV,DDDD" - where VVVV is the PCI vendor ID and DDDD is PCI device ID. - Typically QCA's PCI vendor ID 168c is used while the PCI device - ID depends on the chipset - see the following (possibly - incomplete) list: - - 0023 for AR5416 - - 0024 for AR5418 - - 0027 for AR9160 - - 0029 for AR9220 and AR9223 - - 002a for AR9280 and AR9283 - - 002b for AR9285 - - 002c for AR2427 - - 002d for AR9227 - - 002e for AR9287 - - 0030 for AR9380, AR9381 and AR9382 - - 0032 for AR9485 - - 0033 for AR9580 and AR9590 - - 0034 for AR9462 - - 0036 for AR9565 - - 0037 for AR9485 -- reg: Address and length of the register set for the device. - -Optional properties: -- qca,no-eeprom: Indicates that there is no physical EEPROM connected to the - ath9k wireless chip (in this case the calibration / - EEPROM data will be loaded from userspace using the - kernel firmware loader). - -The MAC address will be determined using the optional properties defined in -net/ethernet.txt. - -In this example, the node is defined as child node of the PCI controller: -&pci0 { - wifi@168c,002d { - compatible = "pci168c,002d"; - reg = <0x7000 0 0 0 0x1000>; - qca,no-eeprom; - }; -}; diff --git a/dts/Bindings/net/wireless/qca,ath9k.yaml b/dts/Bindings/net/wireless/qca,ath9k.yaml new file mode 100644 index 0000000000..8cd0adbf70 --- /dev/null +++ b/dts/Bindings/net/wireless/qca,ath9k.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/qca,ath9k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros ath9k wireless devices Generic Binding + +maintainers: + - Kalle Valo + +description: | + This node provides properties for configuring the ath9k wireless device. + The node is expected to be specified as a child node of the PCI controller + to which the wireless chip is connected. + +allOf: + - $ref: ieee80211.yaml# + +properties: + compatible: + enum: + - pci168c,0023 # AR5416 + - pci168c,0024 # AR5418 + - pci168c,0027 # AR9160 + - pci168c,0029 # AR9220 and AR9223 + - pci168c,002a # AR9280 and AR9283 + - pci168c,002b # AR9285 + - pci168c,002c # AR2427 - 802.11n bonded out + - pci168c,002d # AR9227 + - pci168c,002e # AR9287 + - pci168c,0030 # AR9380, AR9381 and AR9382 + - pci168c,0032 # AR9485 + - pci168c,0033 # AR9580 and AR9590 + - pci168c,0034 # AR9462 + - pci168c,0036 # AR9565 + - pci168c,0037 # AR1111 and AR9485 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ieee80211-freq-limit: true + + qca,no-eeprom: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicates that there is no physical EEPROM connected + + nvmem-cells: + items: + - description: Reference to an nvmem node for the MAC address + - description: Reference to an nvmem node for calibration data + + nvmem-cell-names: + items: + - const: mac-address + - const: calibration + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pcie0 { + #address-cells = <3>; + #size-cells = <2>; + wifi@0,0 { + compatible = "pci168c,002d"; + reg = <0 0 0 0 0>; + interrupts = <3>; + qca,no-eeprom; + }; + }; + - | + pci0 { + #address-cells = <3>; + #size-cells = <2>; + wifi@0,11 { + compatible = "pci168c,0029"; + reg = <0x8800 0 0 0 0>; + nvmem-cells = <&macaddr_art_c>, <&cal_art_1000>; + nvmem-cell-names = "mac-address", "calibration"; + }; + }; diff --git a/dts/Bindings/net/wireless/ti,wlcore,spi.txt b/dts/Bindings/net/wireless/ti,wlcore,spi.txt deleted file mode 100644 index cb5c9e1569..0000000000 --- a/dts/Bindings/net/wireless/ti,wlcore,spi.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Texas Instruments wl12xx/wl18xx wireless lan controller - -The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This -document describes the binding for the SPI connected chip. - -Required properties: -- compatible : Should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" -- reg : Chip select address of device -- spi-max-frequency : Maximum SPI clocking speed of device in Hz -- interrupts : Should contain parameters for 1 interrupt line. -- vwlan-supply : Point the node of the regulator that powers/enable the - wl12xx/wl18xx chip - -Optional properties: -- ref-clock-frequency : Reference clock frequency (should be set for wl12xx) -- clock-xtal : boolean, clock is generated from XTAL - -- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt - for optional SPI connection related properties, - -Examples: - -For wl12xx family: -&spi1 { - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - reg = <1>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - clock-xtal; - ref-clock-frequency = <38400000>; - }; -}; - -For wl18xx family: -&spi0 { - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <0>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/dts/Bindings/net/wireless/ti,wlcore.txt b/dts/Bindings/net/wireless/ti,wlcore.txt deleted file mode 100644 index 9306c4dadd..0000000000 --- a/dts/Bindings/net/wireless/ti,wlcore.txt +++ /dev/null @@ -1,45 +0,0 @@ -TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices - -This node provides properties for controlling the wilink wireless device. The -node is expected to be specified as a child node to the SDIO controller that -connects the device to the system. - -Required properties: - - compatible: should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1285" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" - - interrupts : specifies attributes for the out-of-band interrupt. - -Optional properties: - - ref-clock-frequency : ref clock frequency in Hz - - tcxo-clock-frequency : tcxo clock frequency in Hz - -Note: the *-clock-frequency properties assume internal clocks. In case of external -clock, new bindings (for parsing the clock nodes) have to be added. - -Example: - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/dts/Bindings/net/wireless/ti,wlcore.yaml b/dts/Bindings/net/wireless/ti,wlcore.yaml new file mode 100644 index 0000000000..8dd164d102 --- /dev/null +++ b/dts/Bindings/net/wireless/ti,wlcore.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/ti,wlcore.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Wilink 6/7/8 (wl12xx/wl18xx) Wireless LAN Controller + +maintainers: + - Tony Lindgren + +description: + The wl12xx/wl18xx chips can be connected via SPI or via SDIO. + Note that the *-clock-frequency properties assume internal clocks. In case + of external clocks, new bindings (for parsing the clock nodes) have to be + added. + +properties: + compatible: + enum: + - ti,wl1271 + - ti,wl1273 + - ti,wl1281 + - ti,wl1283 + - ti,wl1285 + - ti,wl1801 + - ti,wl1805 + - ti,wl1807 + - ti,wl1831 + - ti,wl1835 + - ti,wl1837 + + reg: + maxItems: 1 + description: + This is required when connected via SPI, and optional when connected via + SDIO. + + spi-max-frequency: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: irq + - const: wakeup + + vwlan-supply: + description: + Points to the node of the regulator that powers/enable the wl12xx/wl18xx + chip. This is required when connected via SPI. + + + ref-clock-frequency: + description: Reference clock frequency. + + tcxo-clock-frequency: + description: TCXO clock frequency. + + clock-xtal: + $ref: /schemas/types.yaml#/definitions/flag + description: Indicates that the clock is generated from XTAL. + +required: + - compatible + - interrupts + +if: + properties: + compatible: + contains: + enum: + - ti,wl1271 + - ti,wl1273 + - ti,wl1281 + - ti,wl1283 +then: + required: + - ref-clock-frequency + +additionalProperties: false + +examples: + - | + #include + + // For wl12xx family: + spi1 { + #address-cells = <1>; + #size-cells = <0>; + + wlcore1: wlcore@1 { + compatible = "ti,wl1271"; + reg = <1>; + spi-max-frequency = <48000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + vwlan-supply = <&vwlan_fixed>; + clock-xtal; + ref-clock-frequency = <38400000>; + }; + }; + + // For wl18xx family: + spi2 { + #address-cells = <1>; + #size-cells = <0>; + + wlcore2: wlcore@0 { + compatible = "ti,wl1835"; + reg = <0>; + spi-max-frequency = <48000000>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + vwlan-supply = <&vwlan_fixed>; + }; + }; + + // SDIO example: + mmc3 { + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + wlcore3: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/dts/Bindings/numa.txt b/dts/Bindings/numa.txt index 21b35053ca..42f282c2f3 100644 --- a/dts/Bindings/numa.txt +++ b/dts/Bindings/numa.txt @@ -103,7 +103,51 @@ Example: }; ============================================================================== -4 - Example dts +4 - Empty memory nodes +============================================================================== + +Empty memory nodes, which no memory resides in, are allowed. There are no +device nodes for these empty memory nodes. However, the NUMA node IDs and +distance maps are still valid and memory may be added into them through +hotplug afterwards. + +Example: + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + numa-node-id = <0>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + numa-node-id = <1>; + }; + + /* Empty memory node 2 and 3 */ + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 20>, + <0 2 40>, + <0 3 20>, + <1 0 20>, + <1 1 10>, + <1 2 20>, + <1 3 40>, + <2 0 40>, + <2 1 20>, + <2 2 10>, + <2 3 20>, + <3 0 20>, + <3 1 40>, + <3 2 20>, + <3 3 10>; + }; + +============================================================================== +5 - Example dts ============================================================================== Dual socket system consists of 2 boards connected through ccn bus and diff --git a/dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml b/dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml index 1485d3fbab..bf84768228 100644 --- a/dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml +++ b/dts/Bindings/nvmem/ingenic,jz4780-efuse.yaml @@ -33,7 +33,7 @@ unevaluatedProperties: false examples: - | - #include + #include efuse@134100d0 { compatible = "ingenic,jz4780-efuse"; diff --git a/dts/Bindings/nvmem/st,stm32-romem.yaml b/dts/Bindings/nvmem/st,stm32-romem.yaml index 0b80ce22a2..a48c8fa56b 100644 --- a/dts/Bindings/nvmem/st,stm32-romem.yaml +++ b/dts/Bindings/nvmem/st,stm32-romem.yaml @@ -13,7 +13,7 @@ description: | internal vref (VREFIN_CAL), unique device ID... maintainers: - - Fabrice Gasnier + - Fabrice Gasnier allOf: - $ref: "nvmem.yaml#" diff --git a/dts/Bindings/opp/opp-v2-base.yaml b/dts/Bindings/opp/opp-v2-base.yaml index ae3ae4d398..15a76bcd6d 100644 --- a/dts/Bindings/opp/opp-v2-base.yaml +++ b/dts/Bindings/opp/opp-v2-base.yaml @@ -33,7 +33,7 @@ properties: type: boolean patternProperties: - '^opp-?[0-9]+$': + '^opp(-?[0-9]+)*$': type: object description: One or more OPP nodes describing voltage-current-frequency combinations. diff --git a/dts/Bindings/pci/apple,pcie.yaml b/dts/Bindings/pci/apple,pcie.yaml new file mode 100644 index 0000000000..ef1d424ec2 --- /dev/null +++ b/dts/Bindings/pci/apple,pcie.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple PCIe host controller + +maintainers: + - Mark Kettenis + +description: | + The Apple PCIe host controller is a PCIe host controller with + multiple root ports present in Apple ARM SoC platforms, including + various iPhone and iPad devices and the "Apple Silicon" Macs. + The controller incorporates Synopsys DesigWare PCIe logic to + implements its root ports. But the ATU found on most DesignWare + PCIe host bridges is absent. + + All root ports share a single ECAM space, but separate GPIOs are + used to take the PCI devices on those ports out of reset. Therefore + the standard "reset-gpios" and "max-link-speed" properties appear on + the child nodes that represent the PCI bridges that correspond to + the individual root ports. + + MSIs are handled by the PCIe controller and translated into regular + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be + distributed over the root ports as the OS sees fit by programming + the PCIe controller's port registers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - const: apple,t8103-pcie + - const: apple,pcie + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + items: + - const: config + - const: rc + - const: port0 + - const: port1 + - const: port2 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: + Interrupt specifiers, one for each root port. + minItems: 1 + maxItems: 3 + + msi-parent: true + + msi-ranges: + maxItems: 1 + + iommu-map: true + iommu-map-mask: true + +required: + - compatible + - reg + - reg-names + - bus-range + - interrupts + - msi-controller + - msi-parent + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &dart0 1 1>, + <0x200 &dart1 1 1>, + <0x300 &dart2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; diff --git a/dts/Bindings/pci/brcm,stb-pcie.yaml b/dts/Bindings/pci/brcm,stb-pcie.yaml index b9589a0daa..1fe102743f 100644 --- a/dts/Bindings/pci/brcm,stb-pcie.yaml +++ b/dts/Bindings/pci/brcm,stb-pcie.yaml @@ -88,6 +88,7 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# - if: properties: compatible: diff --git a/dts/Bindings/pci/mediatek,mt7621-pcie.yaml b/dts/Bindings/pci/mediatek,mt7621-pcie.yaml new file mode 100644 index 0000000000..044fa967bc --- /dev/null +++ b/dts/Bindings/pci/mediatek,mt7621-pcie.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7621 PCIe controller + +maintainers: + - Sergio Paracuellos + +description: |+ + MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) + with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: mediatek,mt7621-pci + + reg: + items: + - description: host-pci bridge registers + - description: pcie port 0 RC control registers + - description: pcie port 1 RC control registers + - description: pcie port 2 RC control registers + + ranges: + maxItems: 2 + +patternProperties: + 'pcie@[0-2],0': + type: object + $ref: /schemas/pci/pci-bus.yaml# + + properties: + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + required: + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - resets + - clocks + - phys + - phy-names + - ranges + + unevaluatedProperties: false + +required: + - compatible + - reg + - ranges + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pcie: pcie@1e140000 { + compatible = "mediatek,mt7621-pci"; + reg = <0x1e140000 0x100>, + <0x1e142000 0x100>, + <0x1e143000 0x100>, + <0x1e144000 0x100>; + + #address-cells = <3>; + #size-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + device_type = "pci"; + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 24>; + clocks = <&clkctrl 24>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 25>; + clocks = <&clkctrl 25>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 26>; + clocks = <&clkctrl 26>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; + ranges; + }; + }; +... diff --git a/dts/Bindings/pci/microchip,pcie-host.yaml b/dts/Bindings/pci/microchip,pcie-host.yaml index fb95c276a9..7b07764571 100644 --- a/dts/Bindings/pci/microchip,pcie-host.yaml +++ b/dts/Bindings/pci/microchip,pcie-host.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: diff --git a/dts/Bindings/pci/nvidia,tegra194-pcie.txt b/dts/Bindings/pci/nvidia,tegra194-pcie.txt index 6a99d2aa80..8e4f9bfb31 100644 --- a/dts/Bindings/pci/nvidia,tegra194-pcie.txt +++ b/dts/Bindings/pci/nvidia,tegra194-pcie.txt @@ -197,7 +197,7 @@ Tegra194 RC mode: Tegra194 EP mode: ----------------- - pcie_ep@141a0000 { + pcie-ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ diff --git a/dts/Bindings/pci/qcom,pcie-ep.yaml b/dts/Bindings/pci/qcom,pcie-ep.yaml new file mode 100644 index 0000000000..3d23599e5e --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-ep.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe Endpoint Controller binding + +maintainers: + - Manivannan Sadhasivam + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: qcom,sdx55-pcie-ep + + reg: + items: + - description: Qualcomm-specific PARF configuration registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: BAR memory region + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: mmio + + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + + qcom,perst-regs: + description: Reference to a syscon representing TCSR followed by the two + offsets within syscon for Perst enable and Perst separation + enable registers + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + minItems: 3 + maxItems: 3 + + interrupts: + items: + - description: PCIe Global interrupt + - description: PCIe Doorbell interrupt + + interrupt-names: + items: + - const: global + - const: doorbell + + reset-gpios: + description: GPIO used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# output signal + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: core + + power-domains: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pciephy + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - qcom,perst-regs + - interrupts + - interrupt-names + - reset-gpios + - resets + - reset-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + pcie_ep: pcie-ep@40000000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x1000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + }; diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt index 3f646875f8..a0ae024c2d 100644 --- a/dts/Bindings/pci/qcom,pcie.txt +++ b/dts/Bindings/pci/qcom,pcie.txt @@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 @@ -156,7 +157,7 @@ - "pipe" PIPE clock - clock-names: - Usage: required for sm8250 + Usage: required for sc8180x and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -245,7 +246,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 and sm8250 + Usage: required for sc8180x, sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset diff --git a/dts/Bindings/pci/rcar-pci-ep.yaml b/dts/Bindings/pci/rcar-pci-ep.yaml index 295840cf61..32a3b7665f 100644 --- a/dts/Bindings/pci/rcar-pci-ep.yaml +++ b/dts/Bindings/pci/rcar-pci-ep.yaml @@ -19,6 +19,7 @@ properties: - renesas,r8a774b1-pcie-ep # RZ/G2N - renesas,r8a774c0-pcie-ep # RZ/G2E - renesas,r8a774e1-pcie-ep # RZ/G2H + - renesas,r8a7795-pcie-ep # R-Car H3 - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2 reg: diff --git a/dts/Bindings/pci/rockchip-dw-pcie.yaml b/dts/Bindings/pci/rockchip-dw-pcie.yaml new file mode 100644 index 0000000000..142bbe5777 --- /dev/null +++ b/dts/Bindings/pci/rockchip-dw-pcie.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +# We need a select here so we don't match all nodes with 'snps,dw-pcie' +select: + properties: + compatible: + contains: + const: rockchip,rk3568-pcie + required: + - compatible + +properties: + compatible: + items: + - const: rockchip,rk3568-pcie + - const: snps,dw-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Rockchip designed configuration registers + - description: Config registers + + reg-names: + items: + - const: dbi + - const: apb + - const: config + + clocks: + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + + clock-names: + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + + msi-map: true + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + ranges: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + const: pipe + + vpcie3v3-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - msi-map + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + reg = <0x3 0xc0800000 0x0 0x390000>, + <0x0 0xfe280000 0x0 0x10000>, + <0x3 0x80000000 0x0 0x100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru 143>, <&cru 144>, + <&cru 145>, <&cru 146>, + <&cru 147>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power 15>; + ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>, + <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; + resets = <&cru 193>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + }; + }; +... diff --git a/dts/Bindings/phy/bcm-ns-usb2-phy.yaml b/dts/Bindings/phy/bcm-ns-usb2-phy.yaml index 05b4dcd800..426101530a 100644 --- a/dts/Bindings/phy/bcm-ns-usb2-phy.yaml +++ b/dts/Bindings/phy/bcm-ns-usb2-phy.yaml @@ -18,13 +18,21 @@ properties: const: brcm,ns-usb2-phy reg: - items: - - description: iomem address range of DMU (Device Management Unit) + anyOf: + - maxItems: 1 + description: PHY control register + - maxItems: 1 + description: iomem address range of DMU (Device Management Unit) + deprecated: true reg-names: items: - const: dmu + brcm,syscon-clkset: + description: phandle to syscon for clkset register + $ref: /schemas/types.yaml#/definitions/phandle + clocks: items: - description: USB PHY reference clock @@ -39,20 +47,25 @@ properties: required: - compatible - reg - - reg-names - clocks - clock-names - "#phy-cells" +oneOf: + - required: + - brcm,syscon-clkset + - required: + - reg-names + additionalProperties: false examples: - | #include - phy@1800c000 { + phy@1800c164 { compatible = "brcm,ns-usb2-phy"; - reg = <0x1800c000 0x1000>; - reg-names = "dmu"; + reg = <0x1800c164 0x4>; + brcm,syscon-clkset = <&clkset>; clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; clock-names = "phy-ref-clk"; #phy-cells = <0>; diff --git a/dts/Bindings/phy/ingenic,phy-usb.yaml b/dts/Bindings/phy/ingenic,phy-usb.yaml index 0fd93d71fe..5cab216486 100644 --- a/dts/Bindings/phy/ingenic,phy-usb.yaml +++ b/dts/Bindings/phy/ingenic,phy-usb.yaml @@ -46,7 +46,7 @@ additionalProperties: false examples: - | - #include + #include otg_phy: usb-phy@3c { compatible = "ingenic,jz4770-phy"; reg = <0x3c 0x10>; diff --git a/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt b/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt deleted file mode 100644 index 1aa6f2674a..0000000000 --- a/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,-usb-phy" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS diff --git a/dts/Bindings/phy/nvidia,tegra20-usb-phy.yaml b/dts/Bindings/phy/nvidia,tegra20-usb-phy.yaml new file mode 100644 index 0000000000..dfde0eaf66 --- /dev/null +++ b/dts/Bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -0,0 +1,373 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra USB PHY + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra124-usb-phy + - nvidia,tegra114-usb-phy + - enum: + - nvidia,tegra30-usb-phy + - items: + - enum: + - nvidia,tegra30-usb-phy + - nvidia,tegra20-usb-phy + + reg: + minItems: 1 + maxItems: 2 + description: | + PHY0 and PHY2 share power and ground, PHY0 contains shared registers. + PHY0 and PHY2 must specify two register sets, where the first set is + PHY own registers and the second set is the PHY0 registers. + + clocks: + anyOf: + - items: + - description: Registers clock + - description: Main PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: ULPI PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI pads control registers clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI timeout clock + - description: UTMI pads control registers clock + + clock-names: + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + - items: + - const: reg + - const: pll_u + - const: utmi-pads + + - items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + interrupts: + maxItems: 1 + + resets: + oneOf: + - maxItems: 1 + description: PHY reset + + - items: + - description: PHY reset + - description: UTMI pads reset + + reset-names: + oneOf: + - const: usb + + - items: + - const: usb + - const: utmi-pads + + "#phy-cells": + const: 0 + + phy_type: + $ref: /schemas/types.yaml#/definitions/string + enum: [utmi, ulpi, hsic] + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + default: host + + vbus-supply: + description: Regulator controlling USB VBUS. + + nvidia,has-legacy-mode: + description: | + Indicates whether this controller can operate in legacy mode + (as APX 2500 / 2600). In legacy mode some registers are accessed + through the APB_MISC base address instead of the USB controller. + type: boolean + + nvidia,is-wired: + description: | + Indicates whether we can do certain kind of power optimizations for + the devices that are always connected. e.g. modem. + type: boolean + + nvidia,has-utmi-pad-registers: + description: | + Indicates whether this controller contains the UTMI pad control + registers common to all USB controllers. + type: boolean + + nvidia,hssync-start-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles to wait before start of sync launches + RxActive. + + nvidia,elastic-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Variable FIFO Depth of elastic input store. + + nvidia,idle-wait-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles of idle to wait before declare IDLE. + + nvidia,term-range-adj: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Range adjustment on terminations. + + nvidia,xcvr-setup: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 127 + description: Input of XCVR cell, HS driver output control. + + nvidia,xcvr-setup-use-fuses: + description: Indicates that the value is read from the on-chip fuses. + type: boolean + + nvidia,xcvr-lsfslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS falling slew rate control. + + nvidia,xcvr-lsrslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS rising slew rate control. + + nvidia,xcvr-hsslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 511 + description: HS slew rate control. + + nvidia,hssquelch-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: HS squelch detector level. + + nvidia,hsdiscon-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: HS disconnect detector level. + + nvidia,phy-reset-gpio: + maxItems: 1 + description: GPIO used to reset the PHY. + + nvidia,pmc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to Power Management controller. + - description: USB controller ID. + description: + Phandle to Power Management controller. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + - phy_type + +additionalProperties: false + +allOf: + - if: + properties: + phy_type: + const: utmi + + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + + required: + - nvidia,hssync-start-delay + - nvidia,elastic-limit + - nvidia,idle-wait-delay + - nvidia,term-range-adj + - nvidia,xcvr-lsfslew + - nvidia,xcvr-lsrslew + + anyOf: + - required: ["nvidia,xcvr-setup"] + - required: ["nvidia,xcvr-setup-use-fuses"] + + if: + properties: + compatible: + contains: + const: nvidia,tegra30-usb-phy + + then: + properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: reg + - const: pll_u + - const: utmi-pads + + required: + - nvidia,xcvr-hsslew + - nvidia,hssquelch-level + - nvidia,hsdiscon-level + + else: + properties: + clocks: + maxItems: 4 + + clock-names: + items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + - if: + properties: + phy_type: + const: ulpi + + then: + properties: + reg: + minItems: 1 + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + + usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + interrupts = <0 97 4>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; + }; + + - | + #include + + usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; + interrupts = <0 21 4>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; + }; diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.yaml b/dts/Bindings/phy/phy-stm32-usbphyc.yaml index 3329f1d33a..267b695215 100644 --- a/dts/Bindings/phy/phy-stm32-usbphyc.yaml +++ b/dts/Bindings/phy/phy-stm32-usbphyc.yaml @@ -24,7 +24,7 @@ description: |_ UTMI switch_______| OTG controller maintainers: - - Amelie Delaunay + - Amelie Delaunay properties: compatible: @@ -81,6 +81,119 @@ patternProperties: properties: vbus-supply: true + # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due + # to USB connector/receptacle, routing, ESD protection component,... Here is the list of + # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- + # Speed, LS for Low-Speed) + + st,current-boost-microamp: + description: Current boosting in uA + enum: [ 1000, 2000 ] + + st,no-lsfs-fb-cap: + description: Disables the LS/FS feedback capacitor + type: boolean + + st,decrease-hs-slew-rate: + description: Decreases the HS driver slew rate by 10% + type: boolean + + st,tune-hs-dc-level: + description: | + Tunes the HS driver DC level + - <0> normal level + - <1> increases the level by 5 to 7 mV + - <2> increases the level by 10 to 14 mV + - <3> decreases the level by 5 to 7 mV + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + st,enable-fs-rftime-tuning: + description: Enables the FS rise/fall tuning option + type: boolean + + st,enable-hs-rftime-reduction: + description: Enables the HS rise/fall reduction feature + type: boolean + + st,trim-hs-current: + description: | + Controls HS driver current trimming for choke compensation + - <0> = 18.87 mA target current / nominal + 0% + - <1> = 19.165 mA target current / nominal + 1.56% + - <2> = 19.46 mA target current / nominal + 3.12% + - <3> = 19.755 mA target current / nominal + 4.68% + - <4> = 20.05 mA target current / nominal + 6.24% + - <5> = 20.345 mA target current / nominal + 7.8% + - <6> = 20.64 mA target current / nominal + 9.36% + - <7> = 20.935 mA target current / nominal + 10.92% + - <8> = 21.23 mA target current / nominal + 12.48% + - <9> = 21.525 mA target current / nominal + 14.04% + - <10> = 21.82 mA target current / nominal + 15.6% + - <11> = 22.115 mA target current / nominal + 17.16% + - <12> = 22.458 mA target current / nominal + 19.01% + - <13> = 22.755 mA target current / nominal + 20.58% + - <14> = 23.052 mA target current / nominal + 22.16% + - <15> = 23.348 mA target current / nominal + 23.73% + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 0 + + st,trim-hs-impedance: + description: | + Controls HS driver impedance tuning for choke compensation + - <0> = no impedance offset + - <1> = reduce the impedance by 2 ohms + - <2> = reduce the impedance by 4 ohms + - <3> = reduce the impedance by 6 ohms + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + st,tune-squelch-level: + description: | + Tunes the squelch DC threshold value + - <0> = no shift in threshold + - <1> = threshold shift by +7 mV + - <2> = threshold shift by -5 mV + - <3> = threshold shift by +14 mV + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + st,enable-hs-rx-gain-eq: + description: Enables the HS Rx gain equalizer + type: boolean + + st,tune-hs-rx-offset: + description: | + Adjusts the HS Rx offset + - <0> = no offset + - <1> = offset of +5 mV + - <2> = offset of +10 mV + - <3> = offset of -5 mV + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + + st,no-hs-ftime-ctrl: + description: Disables the HS fall time control of single ended signals during pre-emphasis + type: boolean + + st,no-lsfs-sc: + description: Disables the short circuit protection in LS/FS driver + type: boolean + + st,enable-hs-tx-staggering: + description: Enables the basic staggering in HS Tx mode + type: boolean + allOf: - if: properties: @@ -137,6 +250,14 @@ examples: reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; @@ -147,6 +268,14 @@ examples: reg = <1>; phy-supply = <&vdd_usb>; #phy-cells = <1>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; }; ... diff --git a/dts/Bindings/phy/qcom,qmp-phy.yaml b/dts/Bindings/phy/qcom,qmp-phy.yaml index 75be5650a1..630ceaf915 100644 --- a/dts/Bindings/phy/qcom,qmp-phy.yaml +++ b/dts/Bindings/phy/qcom,qmp-phy.yaml @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Qualcomm QMP PHY controller maintainers: - - Manu Gautam + - Vinod Koul description: QMP phy controller supports physical layer functionality for a number of @@ -27,6 +27,7 @@ properties: - qcom,msm8998-qmp-pcie-phy - qcom,msm8998-qmp-ufs-phy - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy - qcom,sc7180-qmp-usb3-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sc8180x-qmp-ufs-phy @@ -116,8 +117,6 @@ required: - clock-names - resets - reset-names - - vdda-phy-supply - - vdda-pll-supply additionalProperties: false @@ -150,6 +149,9 @@ allOf: items: - const: phy - const: common + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -176,6 +178,9 @@ allOf: items: - const: phy - const: common + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -204,6 +209,9 @@ allOf: - const: phy - const: common - const: cfg + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -233,6 +241,9 @@ allOf: items: - const: phy - const: common + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -253,6 +264,9 @@ allOf: reset-names: items: - const: ufsphy + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -278,34 +292,16 @@ allOf: reset-names: items: - const: ufsphy - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq8074-qmp-pcie-phy - then: - properties: - clocks: - items: - - description: pipe clk. - clock-names: - items: - - const: pipe_clk - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: contains: enum: - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-pcie-phy then: properties: clocks: @@ -356,6 +352,9 @@ allOf: reset-names: items: - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -387,6 +386,9 @@ allOf: items: - const: phy - const: common + required: + - vdda-phy-supply + - vdda-pll-supply - if: properties: compatible: @@ -414,6 +416,38 @@ allOf: items: - const: phy - const: common + required: + - vdda-phy-supply + - vdda-pll-supply + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + then: + properties: + clocks: + items: + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + items: + - description: phy_phy reset. + - description: reset of phy block. + reset-names: + items: + - const: phy_phy + - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply examples: - | diff --git a/dts/Bindings/phy/qcom,qusb2-phy.yaml b/dts/Bindings/phy/qcom,qusb2-phy.yaml index ec9ccaaba0..aa2e409a1a 100644 --- a/dts/Bindings/phy/qcom,qusb2-phy.yaml +++ b/dts/Bindings/phy/qcom,qusb2-phy.yaml @@ -21,6 +21,7 @@ properties: - qcom,ipq8074-qusb2-phy - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy + - qcom,qcm2290-qusb2-phy - qcom,sdm660-qusb2-phy - qcom,ipq6018-qusb2-phy - qcom,sm4250-qusb2-phy @@ -50,6 +51,10 @@ properties: - const: ref - const: iface + vdd-supply: + description: + Phandle to 0.9V regulator supply to PHY digital circuit. + vdda-pll-supply: description: Phandle to 1.8V regulator supply to PHY refclk pll block. @@ -156,6 +161,7 @@ required: - "#phy-cells" - clocks - clock-names + - vdd-supply - vdda-pll-supply - vdda-phy-dpdm-supply - resets @@ -174,6 +180,7 @@ examples: <&gcc GCC_RX1_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; + vdd-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-dpdm-supply = <&pm8994_l24>; diff --git a/dts/Bindings/phy/rockchip-usb-phy.yaml b/dts/Bindings/phy/rockchip-usb-phy.yaml index f0fc8275dc..499d55131a 100644 --- a/dts/Bindings/phy/rockchip-usb-phy.yaml +++ b/dts/Bindings/phy/rockchip-usb-phy.yaml @@ -11,13 +11,10 @@ maintainers: properties: compatible: - oneOf: - - const: rockchip,rk3288-usb-phy - - items: - - enum: - - rockchip,rk3066a-usb-phy - - rockchip,rk3188-usb-phy - - const: rockchip,rk3288-usb-phy + enum: + - rockchip,rk3066a-usb-phy + - rockchip,rk3188-usb-phy + - rockchip,rk3288-usb-phy "#address-cells": const: 1 diff --git a/dts/Bindings/pinctrl/apple,pinctrl.yaml b/dts/Bindings/pinctrl/apple,pinctrl.yaml index d50571affd..07b00de797 100644 --- a/dts/Bindings/pinctrl/apple,pinctrl.yaml +++ b/dts/Bindings/pinctrl/apple,pinctrl.yaml @@ -34,6 +34,10 @@ properties: gpio-ranges: maxItems: 1 + apple,npins: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of pins in this GPIO controller. + interrupts: description: One interrupt for each of the (up to 7) interrupt groups supported by the controller sorted by interrupt group @@ -43,6 +47,9 @@ properties: interrupt-controller: true + '#interrupt-cells': + const: 2 + patternProperties: '-pins$': type: object @@ -66,6 +73,7 @@ required: - gpio-controller - '#gpio-cells' - gpio-ranges + - apple,npins additionalProperties: false @@ -86,8 +94,10 @@ examples: gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 212>; + apple,npins = <212>; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&aic>; interrupts = , , diff --git a/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml new file mode 100644 index 0000000000..7602b11e8b --- /dev/null +++ b/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -0,0 +1,363 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT7986 Pin Controller Device Tree Bindings + +maintainers: + - Sean Wang + +description: |+ + The MediaTek's MT7986 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7986a-pinctrl + - mediatek,mt7986b-pinctrl + + reg: + minItems: 8 + maxItems: 8 + + reg-names: + items: + - const: gpio + - const: iocfg_rt + - const: iocfg_rb + - const: iocfg_lt + - const: iocfg_lb + - const: iocfg_tr + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '.*mux.*': + type: object + additionalProperties: false + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "pcie_clk" "pcie" 9 + "pcie_wake" "pcie" 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32 + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2" "uart" 29, 30, 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0" "uart" 29, 30, 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "uart0" "uart" 39, 40 + "pcie_pereset" "pcie" 41 + "uart1" "uart" 42, 43, 44, 45 + "uart2" "uart" 46, 47, 48, 49 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57, + 59, 60, 61 + "pcm" "audio" 62, 63, 64, 65 + "i2s" "audio" 62, 63, 64, 65 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + + $ref: "/schemas/pinctrl/pinmux-node.yaml" + properties: + function: + description: | + A string containing the name of the function to mux to the group. + There is no "audio", "pcie" functions on mt7986b, you can only use + those functions on mt7986a. + enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, + watchdog, wifi] + groups: + description: | + An array of strings. Each string contains the name of a group. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", + and "i2s" groups on mt7986b, you can only use those groups on + mt7986a. + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: audio + then: + properties: + groups: + enum: [pcm, i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc, emmc_rst] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [switch_int, mdc_mdio] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [wifi_led] + - if: + properties: + function: + const: flash + then: + properties: + groups: + enum: [snfi] + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [pcie_clk, pcie_wake, pcie_pereset] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [pwm0, pwm1_0, pwm1_1] + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + - if: + properties: + function: + const: uart + then: + properties: + groups: + enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx, + uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2] + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: wifi + then: + properties: + groups: + enum: [wf_2g, wf_5g, wf_dbdc] + '.*conf.*': + type: object + additionalProperties: false + description: | + pinconf configuration nodes. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: | + An array of strings. Each string contains the name of a pin. + There is no PIN 41 to PIN 65 above on mt7686b, you can only use + those pins on mt7986a. + enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, + GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, + GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, + SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, + SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, + UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, + UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, + UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, + EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, + EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, + PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, + WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, + WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, + WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, + WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ, + WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3, + WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7, + WF1_HB8] + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + }; + }; diff --git a/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml b/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml index 4fe35e6509..cb554084bd 100644 --- a/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -68,6 +68,13 @@ properties: clock, and larger than zero. default: 12500000 + resets: + maxItems: 1 + + reset-names: + items: + - const: switch + patternProperties: "^gpio@[0-1]$": type: object diff --git a/dts/Bindings/pinctrl/pinctrl-mt8195.yaml b/dts/Bindings/pinctrl/pinctrl-mt8195.yaml index e17a399e09..5e2bb2bf3a 100644 --- a/dts/Bindings/pinctrl/pinctrl-mt8195.yaml +++ b/dts/Bindings/pinctrl/pinctrl-mt8195.yaml @@ -49,6 +49,12 @@ properties: description: The interrupt outputs to sysirq. maxItems: 1 + mediatek,rsel_resistance_in_si_unit: + type: boolean + description: | + Identifying i2c pins pull up/down type which is RSEL. It can support + RSEL define or si unit value(ohm) to set different resistance. + #PIN CONFIGURATION NODES patternProperties: '-pins$': @@ -82,9 +88,85 @@ patternProperties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] - bias-pull-down: true + bias-pull-down: + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8195. + For pull down type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" + & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195. + oneOf: + - enum: [100, 101, 102, 103] + - description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + - description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + - description: mt8195 pull down RSEL type si unit value(ohm). + + An example of using RSEL define: + pincontroller { + i2c0_pin { + pinmux = ; + bias-pull-down = ; + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel_resistance_in_si_unit; + } + pincontroller { + i2c0_pin { + pinmux = ; + bias-pull-down = <75000>; + }; + }; - bias-pull-up: true + bias-pull-up: + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8195. + For pull up type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" + & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. + oneOf: + - enum: [100, 101, 102, 103] + - description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + - description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + - description: mt8195 pull up RSEL type si unit value(ohm). + An example of using RSEL define: + pincontroller { + i2c0_pin { + pinmux = ; + bias-pull-up = ; + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel_resistance_in_si_unit; + } + pincontroller { + i2c0_pin { + pinmux = ; + bias-pull-up = <1000>; + }; + }; bias-disable: true diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml b/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml index 9bd01db37d..8952b4cc12 100644 --- a/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml @@ -21,6 +21,7 @@ properties: - qcom,pm660l-gpio - qcom,pm6150-gpio - qcom,pm6150l-gpio + - qcom,pm6350-gpio - qcom,pm7325-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio @@ -103,6 +104,7 @@ $defs: this subnode. Valid pins are - gpio1-gpio10 for pm6150 - gpio1-gpio12 for pm6150l + - gpio1-gpio9 for pm6350 - gpio1-gpio10 for pm7325 - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 @@ -170,6 +172,8 @@ $defs: input-enable: true output-high: true output-low: true + output-enable: true + output-disable: true power-source: true qcom,drive-strength: diff --git a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt b/dts/Bindings/pinctrl/qcom,pmic-mpp.txt deleted file mode 100644 index 5363d44cbb..0000000000 --- a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt +++ /dev/null @@ -1,187 +0,0 @@ -Qualcomm PMIC Multi-Purpose Pin (MPP) block - -This binding describes the MPP block(s) found in the 8xxx series -of PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,pm8018-mpp", - "qcom,pm8019-mpp", - "qcom,pm8038-mpp", - "qcom,pm8058-mpp", - "qcom,pm8821-mpp", - "qcom,pm8841-mpp", - "qcom,pm8916-mpp", - "qcom,pm8917-mpp", - "qcom,pm8921-mpp", - "qcom,pm8941-mpp", - "qcom,pm8950-mpp", - "qcom,pmi8950-mpp", - "qcom,pm8994-mpp", - "qcom,pma8084-mpp", - "qcom,pmi8994-mpp", - - And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" - if the device is on an spmi bus or an ssbi bus respectively. - -- reg: - Usage: required - Value type: - Definition: Register base of the MPP block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available MPP - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define MPP number and the - second denotes the flags for this MPP - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of MPP pins affected by the properties specified in - this subnode. Valid pins are: - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 - mpp1-mpp4 for pma8084 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "digital", - "analog", - "sink" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - Valid values are 600, 10000 and 30000 in bidirectional mode - only, i.e. when operating in qcom,analog-mode and input and - outputs are enabled. The hardware ignores the configuration - when operating in other modes. - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode, i.e. their input - buffer is enabled - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid power - sources are defined in - -- qcom,analog-level: - Usage: optional - Value type: - Definition: Selects the source for analog output. Valued values are - defined in - PMIC_MPP_AOUT_LVL_* - -- qcom,dtest: - Usage: optional - Value type: - Definition: Selects which dtest rail to be routed in the various functions. - Valid values are 1-4 - -- qcom,amux-route: - Usage: optional - Value type: - Definition: Selects the source for analog input. Valid values are - defined in - PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... -- qcom,paired: - Usage: optional - Value type: - Definition: Indicates that the pin should be operating in paired mode. - -Example: - - mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pm8841_default>; - - pm8841_default: default { - gpio { - pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "digital"; - input-enable; - power-source = ; - }; - }; - }; diff --git a/dts/Bindings/pinctrl/qcom,pmic-mpp.yaml b/dts/Bindings/pinctrl/qcom,pmic-mpp.yaml new file mode 100644 index 0000000000..35c846f599 --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,pmic-mpp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC Multi-Purpose Pin (MPP) block + +maintainers: + - Bjorn Andersson + +description: + This binding describes the MPP block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + items: + - enum: + - qcom,pm8018-mpp + - qcom,pm8019-mpp + - qcom,pm8038-mpp + - qcom,pm8058-mpp + - qcom,pm8821-mpp + - qcom,pm8841-mpp + - qcom,pm8916-mpp + - qcom,pm8917-mpp + - qcom,pm8921-mpp + - qcom,pm8941-mpp + - qcom,pm8950-mpp + - qcom,pmi8950-mpp + - qcom,pm8994-mpp + - qcom,pma8084-mpp + - qcom,pmi8994-mpp + + - enum: + - qcom,spmi-mpp + - qcom,ssbi-mpp + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-pmic-mpp-state" + - patternProperties: + "mpp": + $ref: "#/$defs/qcom-pmic-mpp-state" + additionalProperties: false + +$defs: + qcom-pmic-mpp-state: + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - mpp1-mpp4 for pm8841 + - mpp1-mpp4 for pm8916 + - mpp1-mpp8 for pm8941 + - mpp1-mpp4 for pm8950 + - mpp1-mpp4 for pmi8950 + - mpp1-mpp4 for pma8084 + + items: + pattern: "^mpp([0-9]+)$" + + function: + items: + - enum: + - digital + - analog + - sink + + bias-disable: true + bias-pull-up: true + bias-high-impedance: true + input-enable: true + output-high: true + output-low: true + power-source: true + + qcom,analog-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog output. Valued values are defined in + PMIC_MPP_AOUT_LVL_* + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + qcom,amux-route: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog input. Valid values are defined in + PMIC_MPP_AMUX_ROUTE_CH5, + PMIC_MPP_AMUX_ROUTE_CH6... + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,paired: + - description: + Indicates that the pin should be operating in paired mode. + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + + pm8841_mpp: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000 0>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpp 0 0 4>; + gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", + "BT_LED_CTRL", "GPIO-F"; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8841_default>; + + mpp1-state { + pins = "mpp1"; + function = "digital"; + input-enable; + power-source = ; + }; + + default-state { + gpio-mpp { + pins = "mpp1", "mpp2", "mpp3", "mpp4"; + function = "digital"; + input-enable; + power-source = ; + }; + }; + }; +... diff --git a/dts/Bindings/pinctrl/qcom,qcm2290-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,qcm2290-pinctrl.yaml new file mode 100644 index 0000000000..13f338619d --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,qcm2290-pinctrl.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCM2290 TLMM block + +maintainers: + - Shawn Guo + +description: + This binding describes the Top Level Mode Multiplexer block found in the + QCM2290 platform. + +properties: + compatible: + const: qcom,qcm2290-tlmm + + reg: + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-qcm2290-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-qcm2290-tlmm-state" + +'$defs': + qcom-qcm2290-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec, + cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, + gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, + jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, + mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1, + pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11, + pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist, + pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3, + pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio, + qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write, + ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1, + vsense_trigger, wlan1_adc0, wlan1_adc1 ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@500000 { + compatible = "qcom,qcm2290-tlmm"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 127>; + + sdc2_on_state: sdc2-on-state { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml new file mode 100644 index 0000000000..554992a681 --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM6350 TLMM block + +maintainers: + - Konrad Dybcio + +description: | + This binding describes the Top Level Mode Multiplexer (TLMM) block found + in the SM6350 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6350-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sm6350-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sm6350-tlmm-state" + +$defs: + qcom-sm6350-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22, + atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, + cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, + dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, + gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk, + mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, + mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, + phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, + phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, + pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, + qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11, + qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data, + rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write, + sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, + wlan2_adc0, wlan2_adc1, ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,sm6350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio25"; + function = "qup13_f2"; + bias-disable; + }; + + tx { + pins = "gpio26"; + function = "qup13_f2"; + bias-disable; + }; + }; + }; +... diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 84c4111293..0000000000 --- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: should be - "rockchip,px30-pinctrl": for Rockchip PX30 - "rockchip,rv1108-pinctrl": for Rockchip RV1108 - "rockchip,rk2928-pinctrl": for Rockchip RK2928 - "rockchip,rk3066a-pinctrl": for Rockchip RK3066a - "rockchip,rk3066b-pinctrl": for Rockchip RK3066b - "rockchip,rk3128-pinctrl": for Rockchip RK3128 - "rockchip,rk3188-pinctrl": for Rockchip RK3188 - "rockchip,rk3228-pinctrl": for Rockchip RK3228 - "rockchip,rk3288-pinctrl": for Rockchip RK3288 - "rockchip,rk3308-pinctrl": for Rockchip RK3308 - "rockchip,rk3328-pinctrl": for Rockchip RK3328 - "rockchip,rk3368-pinctrl": for Rockchip RK3368 - "rockchip,rk3399-pinctrl": for Rockchip RK3399 - "rockchip,rk3568-pinctrl": for Rockchip RK3568 - - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. On the rk3368 this should - point to the PMUGRF syscon. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: -See rockchip,gpio-bank.yaml - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = . - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.yaml b/dts/Bindings/pinctrl/rockchip,pinctrl.yaml new file mode 100644 index 0000000000..07c0a98ef9 --- /dev/null +++ b/dts/Bindings/pinctrl/rockchip,pinctrl.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pinmux Controller + +maintainers: + - Heiko Stuebner + +description: | + The Rockchip Pinmux Controller enables the IC to share one PAD + to several functional blocks. The sharing is done by multiplexing + the PAD input/output signals. For each PAD there are several muxing + options with option 0 being used as a GPIO. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The Rockchip pin configuration node is a node of a group of pins which can be + used for a specific device or function. This node represents both mux and + config of the pins in that group. The 'pins' selects the function mode + (also named pin mode) this pin can work on and the 'config' configures + various pad settings such as pull-up, etc. + + The pins are grouped into up to 9 individual pin banks which need to be + defined as gpio sub-nodes of the pinmux controller. + +properties: + compatible: + enum: + - rockchip,px30-pinctrl + - rockchip,rk2928-pinctrl + - rockchip,rk3066a-pinctrl + - rockchip,rk3066b-pinctrl + - rockchip,rk3128-pinctrl + - rockchip,rk3188-pinctrl + - rockchip,rk3228-pinctrl + - rockchip,rk3288-pinctrl + - rockchip,rk3308-pinctrl + - rockchip,rk3328-pinctrl + - rockchip,rk3368-pinctrl + - rockchip,rk3399-pinctrl + - rockchip,rk3568-pinctrl + - rockchip,rv1108-pinctrl + + rockchip,grf: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + The phandle of the syscon node for the GRF registers. + + rockchip,pmu: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + The phandle of the syscon node for the PMU registers, + as some SoCs carry parts of the iomux controller registers there. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + + ranges: true + +required: + - compatible + - rockchip,grf + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "gpio@[0-9a-f]+$": + type: object + + $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#" + + unevaluatedProperties: false + + "pcfg-[a-z0-9-]+$": + type: object + properties: + bias-disable: true + + bias-pull-down: true + + bias-pull-pin-default: true + + bias-pull-up: true + + drive-strength: + minimum: 0 + maximum: 20 + + input-enable: true + + input-schmitt-enable: true + + output-high: true + + output-low: true + + additionalProperties: false + +additionalProperties: + type: object + additionalProperties: + type: object + properties: + rockchip,pins: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + minItems: 1 + items: + items: + - minimum: 0 + maximum: 8 + description: + Pin bank. + - minimum: 0 + maximum: 31 + description: + Pin bank index. + - minimum: 0 + maximum: 6 + description: + Mux 0 means GPIO and mux 1 to N means + the specific device function. + - description: + The phandle of a node contains the generic pinconfig options + to use as described in pinctrl-bindings.txt. + +examples: + - | + #include + #include + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = ; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + }; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = ; + clocks = <&mux_uart2>; + pinctrl-0 = <&uart2_xfer>; + pinctrl-names = "default"; + reg-io-width = <1>; + reg-shift = <2>; + }; diff --git a/dts/Bindings/pinctrl/samsung-pinctrl.txt b/dts/Bindings/pinctrl/samsung-pinctrl.txt index e7a1b18803..b8b475967f 100644 --- a/dts/Bindings/pinctrl/samsung-pinctrl.txt +++ b/dts/Bindings/pinctrl/samsung-pinctrl.txt @@ -23,6 +23,7 @@ Required Properties: - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. + - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. diff --git a/dts/Bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/dts/Bindings/pinctrl/socionext,uniphier-pinctrl.yaml index 502480a19f..a804d9bc16 100644 --- a/dts/Bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/dts/Bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -24,6 +24,7 @@ properties: - socionext,uniphier-ld11-pinctrl - socionext,uniphier-ld20-pinctrl - socionext,uniphier-pxs3-pinctrl + - socionext,uniphier-nx1-pinctrl required: - compatible diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml index dfee6d38a7..ac88e01ec4 100644 --- a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32 GPIO and Pin Mux/Config controller maintainers: - - Alexandre TORGUE + - Alexandre TORGUE description: | STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware diff --git a/dts/Bindings/power/qcom,rpmpd.yaml b/dts/Bindings/power/qcom,rpmpd.yaml index 239f37881c..e810480e3e 100644 --- a/dts/Bindings/power/qcom,rpmpd.yaml +++ b/dts/Bindings/power/qcom,rpmpd.yaml @@ -19,6 +19,7 @@ properties: - qcom,mdm9607-rpmpd - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd + - qcom,msm8953-rpmpd - qcom,msm8976-rpmpd - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd @@ -31,6 +32,7 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm6115-rpmpd + - qcom,sm6350-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd diff --git a/dts/Bindings/power/supply/maxim,max17040.yaml b/dts/Bindings/power/supply/maxim,max17040.yaml index f792d06db4..ffb344987a 100644 --- a/dts/Bindings/power/supply/maxim,max17040.yaml +++ b/dts/Bindings/power/supply/maxim,max17040.yaml @@ -62,7 +62,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/power/supply/samsung,battery.yaml b/dts/Bindings/power/supply/samsung,battery.yaml new file mode 100644 index 0000000000..40292d581b --- /dev/null +++ b/dts/Bindings/power/supply/samsung,battery.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/samsung,battery.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SDI Batteries + +maintainers: + - Linus Walleij + +description: | + Samsung SDI (Samsung Digital Interface) batteries are all different versions + of lithium ion chemistry devices used for mobile phones, laptops and other + portable electronics. The batteries are adapted to a specific product and + the physical restrictions make it impossible to use another battery with the + product, so product device trees can specify these batteries. Operating + systems should determine hardware characteristics of the batteries from the + compatible string. + +properties: + compatible: + oneOf: + - const: samsung,eb-l1m7flu + description: 3.8V 1500 mAh battery used in Samsung GT-I8190 + - const: samsung,eb425161la + description: 3.8V 1500 mAh battery used in Samsung SGH-T599 and SGH-I407 + - const: samsung,eb425161lu + description: 3.8V 1500 mAh battery used in Samsung GT-I8160 + - const: samsung,eb485159lu + description: 3.8V 1700 mAh battery used in Samsung GT-S7710 + - const: samsung,eb535151vu + description: 3.8V 1500 mAh battery used in Samsung GT-I9070 + - const: samsung,eb585157lu + description: 3.8V 2000 mAh battery used in Samsung GT-I8530 + +required: + - compatible + +additionalProperties: false + +examples: + - | + power { + #address-cells = <1>; + #size-cells = <0>; + + battery: battery { + compatible = "samsung,eb425161la"; + }; + + charger@11 { + reg = <0x11>; + monitored-battery = <&battery>; + }; + }; diff --git a/dts/Bindings/power/supply/stericsson,ab8500-btemp.yaml b/dts/Bindings/power/supply/stericsson,ab8500-btemp.yaml index 2f57aa5a5f..4b8a00cec3 100644 --- a/dts/Bindings/power/supply/stericsson,ab8500-btemp.yaml +++ b/dts/Bindings/power/supply/stericsson,ab8500-btemp.yaml @@ -17,10 +17,14 @@ properties: compatible: const: stericsson,ab8500-btemp - battery: + monitored-battery: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to battery node + battery: + $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true + interrupts: maxItems: 5 @@ -42,7 +46,7 @@ properties: required: - compatible - - battery + - monitored-battery - interrupts - interrupt-names - io-channels @@ -56,7 +60,7 @@ examples: pmic { battery-temperature { compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; + monitored-battery = <&battery>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/Bindings/power/supply/stericsson,ab8500-chargalg.yaml b/dts/Bindings/power/supply/stericsson,ab8500-chargalg.yaml index 0897231c2f..6799224f7f 100644 --- a/dts/Bindings/power/supply/stericsson,ab8500-chargalg.yaml +++ b/dts/Bindings/power/supply/stericsson,ab8500-chargalg.yaml @@ -17,13 +17,17 @@ properties: compatible: const: stericsson,ab8500-chargalg - battery: + monitored-battery: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to battery node + battery: + $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true + required: - compatible - - battery + - monitored-battery additionalProperties: false @@ -32,6 +36,6 @@ examples: pmic { charging-algorithm { compatible = "stericsson,ab8500-chargalg"; - battery = <&ab8500_battery>; + monitored-battery = <&ab8500_battery>; }; }; diff --git a/dts/Bindings/power/supply/stericsson,ab8500-charger.yaml b/dts/Bindings/power/supply/stericsson,ab8500-charger.yaml index e13305afea..9518eb7289 100644 --- a/dts/Bindings/power/supply/stericsson,ab8500-charger.yaml +++ b/dts/Bindings/power/supply/stericsson,ab8500-charger.yaml @@ -17,10 +17,14 @@ properties: compatible: const: stericsson,ab8500-charger - battery: + monitored-battery: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to battery node + battery: + $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true + vddadc-supply: description: Supply for USB and Main charger @@ -66,7 +70,7 @@ properties: required: - compatible - - battery + - monitored-battery - vddadc-supply - interrupts - interrupt-names @@ -81,7 +85,7 @@ examples: pmic { charger { compatible = "stericsson,ab8500-charger"; - battery = <&ab8500_battery>; + monitored-battery = <&battery>; vddadc-supply = <&ab8500_ldo_tvout_reg>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, <11 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/Bindings/power/supply/stericsson,ab8500-fg.yaml b/dts/Bindings/power/supply/stericsson,ab8500-fg.yaml index db342e5ac0..54ac42a9d3 100644 --- a/dts/Bindings/power/supply/stericsson,ab8500-fg.yaml +++ b/dts/Bindings/power/supply/stericsson,ab8500-fg.yaml @@ -17,10 +17,14 @@ properties: compatible: const: stericsson,ab8500-fg - battery: + monitored-battery: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to battery node + battery: + $ref: /schemas/types.yaml#/definitions/phandle + deprecated: true + interrupts: maxItems: 5 @@ -41,7 +45,7 @@ properties: required: - compatible - - battery + - monitored-battery - interrupts - interrupt-names - io-channels @@ -55,7 +59,7 @@ examples: pmic { fuel-gauge { compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; + monitored-battery = <&battery>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_LEVEL_HIGH>, <28 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/Bindings/pwm/renesas,tpu-pwm.yaml b/dts/Bindings/pwm/renesas,tpu-pwm.yaml index 81ccb21101..1f5c638418 100644 --- a/dts/Bindings/pwm/renesas,tpu-pwm.yaml +++ b/dts/Bindings/pwm/renesas,tpu-pwm.yaml @@ -35,9 +35,11 @@ properties: - renesas,tpu-r8a7794 # R-Car E2 - renesas,tpu-r8a7795 # R-Car H3 - renesas,tpu-r8a7796 # R-Car M3-W + - renesas,tpu-r8a77961 # R-Car M3-W+ - renesas,tpu-r8a77965 # R-Car M3-N - renesas,tpu-r8a77970 # R-Car V3M - renesas,tpu-r8a77980 # R-Car V3H + - renesas,tpu-r8a779a0 # R-Car V3U - const: renesas,tpu reg: diff --git a/dts/Bindings/regulator/max77686.txt b/dts/Bindings/regulator/max77686.txt index e9f7578ca0..ff3d2dec8c 100644 --- a/dts/Bindings/regulator/max77686.txt +++ b/dts/Bindings/regulator/max77686.txt @@ -43,7 +43,7 @@ Example: max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 IRQ_TYPE_NONE>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; voltage-regulators { diff --git a/dts/Bindings/regulator/max8952.txt b/dts/Bindings/regulator/max8952.txt deleted file mode 100644 index 866fcdd0f4..0000000000 --- a/dts/Bindings/regulator/max8952.txt +++ /dev/null @@ -1,52 +0,0 @@ -Maxim MAX8952 voltage regulator - -Required properties: -- compatible: must be equal to "maxim,max8952" -- reg: I2C slave address, usually 0x60 -- max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages - in microvolts. All values must be from range <770000, 1400000> -- any required generic properties defined in regulator.txt - -Optional properties: -- max8952,vid-gpios: array of two GPIO pins used for DVS voltage selection -- max8952,en-gpio: GPIO used to control enable status of regulator -- max8952,default-mode: index of default DVS voltage, from <0, 3> range -- max8952,sync-freq: sync frequency, must be one of following values: - - 0: 26 MHz - - 1: 13 MHz - - 2: 19.2 MHz - Defaults to 26 MHz if not specified. -- max8952,ramp-speed: voltage ramp speed, must be one of following values: - - 0: 32mV/us - - 1: 16mV/us - - 2: 8mV/us - - 3: 4mV/us - - 4: 2mV/us - - 5: 1mV/us - - 6: 0.5mV/us - - 7: 0.25mV/us - Defaults to 32mV/us if not specified. -- any available generic properties defined in regulator.txt - -Example: - - vdd_arm_reg: pmic@60 { - compatible = "maxim,max8952"; - reg = <0x60>; - - /* max8952-specific properties */ - max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; - max8952,en-gpio = <&gpx0 1 0>; - max8952,default-mode = <0>; - max8952,dvs-mode-microvolt = <1250000>, <1200000>, - <1050000>, <950000>; - max8952,sync-freq = <0>; - max8952,ramp-speed = <0>; - - /* generic regulator properties */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <770000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; diff --git a/dts/Bindings/regulator/max8973-regulator.txt b/dts/Bindings/regulator/max8973-regulator.txt deleted file mode 100644 index c2c68fcc1b..0000000000 --- a/dts/Bindings/regulator/max8973-regulator.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Maxim MAX8973 Voltage Regulator - -Required properties: - -- compatible: must be one of following: - "maxim,max8973" - "maxim,max77621". -- reg: the i2c slave address of the regulator. It should be 0x1b. - -Any standard regulator properties can be used to configure the single max8973 -DCDC. - -Optional properties: - --maxim,externally-enable: boolean, externally control the regulator output - enable/disable. --maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided - then externally enable control will be considered. --maxim,dvs-gpio: GPIO which is connected to DVS pin of device. --maxim,dvs-default-state: Default state of GPIO during initialisation. - 1 for HIGH and 0 for LOW. --maxim,enable-remote-sense: boolean, enable reote sense. --maxim,enable-falling-slew-rate: boolean, enable falling slew rate. --maxim,enable-active-discharge: boolean: enable active discharge. --maxim,enable-frequency-shift: boolean, enable 9% frequency shift. --maxim,enable-bias-control: boolean, enable bias control. By enabling this - startup delay can be reduce to 20us from 220us. --maxim,enable-etr: boolean, enable Enhanced Transient Response. --maxim,enable-high-etr-sensitivity: boolean, Enhanced transient response - circuit is enabled and set for high sensitivity. If this - property is available then etr will be enable default. - -Enhanced transient response (ETR) will affect the configuration of CKADV. - --junction-warn-millicelsius: u32, junction warning temperature threshold - in millicelsius. If die temperature crosses this level then - device generates the warning interrupts. - -Please note that thermal functionality is only supported on MAX77621. The -supported threshold warning temperature for MAX77621 are 120 degC and 140 degC. - -Example: - - max8973@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; diff --git a/dts/Bindings/regulator/max8997-regulator.txt b/dts/Bindings/regulator/max8997-regulator.txt deleted file mode 100644 index b53c5e2b33..0000000000 --- a/dts/Bindings/regulator/max8997-regulator.txt +++ /dev/null @@ -1,145 +0,0 @@ -* Maxim MAX8997 Voltage and Current Regulator - -The Maxim MAX8997 is a multi-function device which includes voltage and -current regulators, rtc, charger controller and other sub-blocks. It is -interfaced to the host controller using a i2c interface. Each sub-block is -addressed by the host system using different i2c slave address. This document -describes the bindings for 'pmic' sub-block of max8997. - -Required properties: -- compatible: Should be "maxim,max8997-pmic". -- reg: Specifies the i2c slave address of the pmic block. It should be 0x66. - -- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck1 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck2 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck5 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - -[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional - property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage' - property should specify atleast one voltage level (which would be a - safe operating voltage). - - If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional - property is specified, then all the eight voltage values for the - 'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified. - -Optional properties: -- interrupts: Interrupt specifiers for two interrupt sources. - - First interrupt specifier is for 'irq1' interrupt. - - Second interrupt specifier is for 'alert' interrupt. -- charger-supply: regulator node for charging current. -- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs. -- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. -- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs. - -Additional properties required if either of the optional properties are used: -- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for - multiple bucks, changing the voltage value of one of the bucks may affect - that of another buck, which is the side effect of the change (set_voltage). - Use this property to ignore such side effects and change the voltage. - -- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from - the possible 8 options selectable by the dvs gpios. The value of this - property should be between 0 and 7. If not specified or if out of range, the - default value of this property is set to 0. - -- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used - for dvs. The format of the gpio specifier depends in the gpio controller. - -Regulators: The regulators of max8997 that have to be instantiated should be -included in a sub-node named 'regulators'. Regulator nodes included in this -sub-node should be of the format as listed below. - - regulator_name { - standard regulator bindings here - }; - -The following are the names of the regulators that the max8997 pmic block -supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of max8997. - - - LDOn - - valid values for n are 1 to 18 and 21 - - Example: LDO0, LD01, LDO2, LDO21 - - BUCKn - - valid values for n are 1 to 7. - - Example: BUCK1, BUCK2, BUCK3, BUCK7 - - - ENVICHG: Battery Charging Current Monitor Output. This is a fixed - voltage type regulator - - - ESAFEOUT1: (ldo19) - - ESAFEOUT2: (ld020) - - - CHARGER_CV: main battery charger voltage control - - CHARGER: main battery charger current control - - CHARGER_TOPOFF: end of charge current threshold level - -The bindings inside the regulator nodes use the standard regulator bindings -which are documented elsewhere. - -Example: - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - interrupt-parent = <&wakeup_eint>; - reg = <0x66>; - interrupts = <4 0>, <3 0>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */ - <&gpx0 1 1 0 0>, /* SET2 */ - <&gpx0 2 1 0 0>; /* SET3 */ - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_ARM_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; diff --git a/dts/Bindings/regulator/maxim,max8952.yaml b/dts/Bindings/regulator/maxim,max8952.yaml new file mode 100644 index 0000000000..e4e8c58f60 --- /dev/null +++ b/dts/Bindings/regulator/maxim,max8952.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max8952.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX8952 voltage regulator + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: maxim,max8952 + + max8952,default-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + index of default DVS voltage + + max8952,dvs-mode-microvolt: + minItems: 4 + maxItems: 4 + items: + minimum: 770000 + maximum: 1400000 + description: | + Array of 4 integer values defining DVS voltages in microvolts. All values + must be from range <770000, 1400000>. + + max8952,en-gpio: + maxItems: 1 + description: | + GPIO used to control enable status of regulator + + max8952,ramp-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + default: 0 + description: | + Voltage ramp speed, values map to: + - 0: 32mV/us + - 1: 16mV/us + - 2: 8mV/us + - 3: 4mV/us + - 4: 2mV/us + - 5: 1mV/us + - 6: 0.5mV/us + - 7: 0.25mV/us + Defaults to 32mV/us if not specified. + + max8952,sync-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + description: | + Sync frequency, values map to: + - 0: 26 MHz + - 1: 13 MHz + - 2: 19.2 MHz + Defaults to 26 MHz if not specified. + + max8952,vid-gpios: + minItems: 2 + maxItems: 2 + description: | + Array of two GPIO pins used for DVS voltage selection + + reg: + maxItems: 1 + +required: + - compatible + - max8952,dvs-mode-microvolt + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + + max8952,vid-gpios = <&gpx0 3 GPIO_ACTIVE_HIGH>, + <&gpx0 4 GPIO_ACTIVE_HIGH>; + max8952,default-mode = <0>; + max8952,dvs-mode-microvolt = <1250000>, <1200000>, + <1050000>, <950000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <770000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + }; diff --git a/dts/Bindings/regulator/maxim,max8973.yaml b/dts/Bindings/regulator/maxim,max8973.yaml new file mode 100644 index 0000000000..5452282726 --- /dev/null +++ b/dts/Bindings/regulator/maxim,max8973.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max8973.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX8973/MAX77621 voltage regulator + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + enum: + - maxim,max8973 + - maxim,max77621 + + junction-warn-millicelsius: + description: | + Junction warning temperature threshold in millicelsius. If die + temperature crosses this level then device generates the warning + interrupts. + Please note that thermal functionality is only supported on MAX77621. The + supported threshold warning temperature for MAX77621 are 120 degC and 140 + degC. + + maxim,dvs-gpio: + maxItems: 1 + description: | + GPIO which is connected to DVS pin of device. + + maxim,dvs-default-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Default state of GPIO during initialisation. + 1 for HIGH and 0 for LOW. + + maxim,externally-enable: + type: boolean + description: | + Externally control the regulator output enable/disable. + + maxim,enable-gpio: + maxItems: 1 + description: | + GPIO for enable control. If the valid GPIO is provided then externally + enable control will be considered. + + maxim,enable-remote-sense: + type: boolean + description: Enable remote sense. + + maxim,enable-falling-slew-rate: + type: boolean + description: Enable falling slew rate. + + maxim,enable-active-discharge: + type: boolean + description: Eable active discharge. + + maxim,enable-frequency-shift: + type: boolean + description: Enable 9% frequency shift. + + maxim,enable-bias-control: + type: boolean + description: | + Enable bias control which can reduce the startup delay to 20us from 220us. + + maxim,enable-etr: + type: boolean + description: Enable Enhanced Transient Response. + + maxim,enable-high-etr-sensitivity: + type: boolean + description: | + Enhanced transient response circuit is enabled and set for high + sensitivity. If this property is available then etr will be enable + default. + Enhanced transient response (ETR) will affect the configuration of CKADV. + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@1b { + compatible = "maxim,max8973"; + reg = <0x1b>; + + regulator-min-microvolt = <935000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@1b { + compatible = "maxim,max77621"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = ; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1231250>; + regulator-name = "PPVAR_CPU"; + regulator-ramp-delay = <12500>; + maxim,dvs-default-state = <1>; + maxim,enable-active-discharge; + maxim,enable-bias-control; + maxim,enable-etr; + maxim,enable-gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; + maxim,externally-enable; + }; + }; diff --git a/dts/Bindings/regulator/maxim,max8997.yaml b/dts/Bindings/regulator/maxim,max8997.yaml new file mode 100644 index 0000000000..d5a44ca3df --- /dev/null +++ b/dts/Bindings/regulator/maxim,max8997.yaml @@ -0,0 +1,445 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max8997.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX8997 Power Management IC + +maintainers: + - Krzysztof Kozlowski + +description: | + The Maxim MAX8997 is a Power Management IC which includes voltage and current + regulators, charger controller with fuel gauge, RTC, clock outputs, haptic + motor driver, flash LED driver and Micro-USB Interface Controller. + + The binding here is not complete and describes only regulator and charger + controller parts. + +properties: + compatible: + const: maxim,max8997-pmic + + charger-supply: + description: | + Regulator node for charging current. + + interrupts: + items: + - description: irq1 interrupt + - description: alert interrupt + + max8997,pmic-buck1-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck1 when + changing voltage using GPIO DVS. + If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is + specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should + specify at least one voltage level (which would be a safe operating + voltage). + + max8997,pmic-buck2-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck2 when + changing voltage using GPIO DVS. + If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is + specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should + specify at least one voltage level (which would be a safe operating + voltage). + + max8997,pmic-buck5-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck5 when + changing voltage using GPIO DVS. + If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is + specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should + specify at least one voltage level (which would be a safe operating + voltage). + + max8997,pmic-buck1-uses-gpio-dvs: + type: boolean + description: | + buck1 can be controlled by GPIO DVS. + + max8997,pmic-buck2-uses-gpio-dvs: + type: boolean + description: | + buck2 can be controlled by GPIO DVS. + + max8997,pmic-buck5-uses-gpio-dvs: + type: boolean + description: | + buck5 can be controlled by GPIO DVS. + + max8997,pmic-buck125-default-dvs-idx: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 0 + description: | + Default voltage setting selected from the possible 8 options selectable + by the dvs gpios. The value of this property should be between 0 and 7. + If not specified or if out of range, the default value of this property + is set to 0. + + max8997,pmic-buck125-dvs-gpios: + minItems: 3 + maxItems: 3 + description: | + GPIO specifiers for three host gpio's used for DVS. + + max8997,pmic-ignore-gpiodvs-side-effect: + type: boolean + description: | + When GPIO-DVS mode is used for multiple bucks, changing the voltage value + of one of the bucks may affect that of another buck, which is the side + effect of the change (set_voltage). Use this property to ignore such + side effects and change the voltage. + + reg: + maxItems: 1 + + regulators: + type: object + description: + List of child nodes that specify the regulators. + + patternProperties: + # 1-18 and 21 LDOs + "^LDO([1-9]|1[0-8]|21)$": + type: object + $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + # 7 bucks + "^BUCK[1-7]$": + type: object + $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + "^EN32KHZ_[AC]P$": + type: object + $ref: regulator.yaml# + description: + 32768 Hz clock output (modelled as regulator) + + properties: + regulator-name: true + regulator-always-on: true + regulator-boot-on: true + + required: + - regulator-name + + additionalProperties: false + + properties: + CHARGER: + type: object + $ref: regulator.yaml# + description: main battery charger current control + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + CHARGER_CV: + type: object + $ref: regulator.yaml# + description: main battery charger voltage control + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + CHARGER_TOPOFF: + type: object + $ref: regulator.yaml# + description: end of charge current threshold level + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + ENVICHG: + type: object + $ref: regulator.yaml# + description: | + Battery Charging Current Monitor Output. This is a fixed voltage type + regulator + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + ESAFEOUT1: + type: object + $ref: regulator.yaml# + description: LDO19 + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + + ESAFEOUT2: + type: object + $ref: regulator.yaml# + description: LDO20 + + properties: + regulator-name: true + + required: + - regulator-name + + unevaluatedProperties: false + +required: + - compatible + - max8997,pmic-buck1-dvs-voltage + - max8997,pmic-buck2-dvs-voltage + - max8997,pmic-buck5-dvs-voltage + - reg + - regulators + +dependencies: + max8997,pmic-buck1-uses-gpio-dvs: [ 'max8997,pmic-buck125-dvs-gpios' ] + max8997,pmic-buck2-uses-gpio-dvs: [ 'max8997,pmic-buck125-dvs-gpios' ] + max8997,pmic-buck5-uses-gpio-dvs: [ 'max8997,pmic-buck125-dvs-gpios' ] + +additionalProperties: false + +if: + anyOf: + - required: + - max8997,pmic-buck1-uses-gpio-dvs + - required: + - max8997,pmic-buck2-uses-gpio-dvs + - required: + - max8997,pmic-buck5-uses-gpio-dvs +then: + properties: + max8997,pmic-buck1-dvs-voltage: + minItems: 8 + maxItems: 8 + max8997,pmic-buck2-dvs-voltage: + minItems: 8 + maxItems: 8 + max8997,pmic-buck5-dvs-voltage: + minItems: 8 + maxItems: 8 + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; + pinctrl-names = "default"; + + charger-supply = <&charger_reg>; + + regulators { + LDO1 { + regulator-name = "VADC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + // ... + + BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; + + CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <200000>; + regulator-max-microamp = <950000>; + }; + + CHARGER_CV { + regulator-name = "CHARGER_CV"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + }; + + CHARGER_TOPOFF { + regulator-name = "CHARGER_TOPOFF"; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + }; + }; + }; + + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>, + <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max8997_irq>; + + max8997,pmic-buck1-dvs-voltage = <1350000>; + max8997,pmic-buck2-dvs-voltage = <1100000>; + max8997,pmic-buck5-dvs-voltage = <1200000>; + + regulators { + LDO1 { + regulator-name = "VDD_ABB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + // ... + + BUCK1 { + regulator-name = "VDD_ARM_1.2V"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + // ... + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + }; + }; + }; diff --git a/dts/Bindings/regulator/qcom,rpmh-regulator.yaml b/dts/Bindings/regulator/qcom,rpmh-regulator.yaml index 34de38377a..b959504e0e 100644 --- a/dts/Bindings/regulator/qcom,rpmh-regulator.yaml +++ b/dts/Bindings/regulator/qcom,rpmh-regulator.yaml @@ -35,6 +35,7 @@ description: | PMIC. Supported regulator node names are For PM6150, smps1 - smps5, ldo1 - ldo19 For PM6150L, smps1 - smps8, ldo1 - ldo11, bob + For PM6350, smps1 - smps5, ldo1 - ldo22 For PM7325, smps1 - smps8, ldo1 - ldo19 For PM8005, smps1 - smps4 For PM8009, smps1 - smps2, ldo1 - ldo7 @@ -52,6 +53,7 @@ properties: enum: - qcom,pm6150-rpmh-regulators - qcom,pm6150l-rpmh-regulators + - qcom,pm6350-rpmh-regulators - qcom,pm7325-rpmh-regulators - qcom,pm8005-rpmh-regulators - qcom,pm8009-rpmh-regulators diff --git a/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml index 83b53579f4..f052e03be4 100644 --- a/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -65,6 +65,9 @@ description: For pms405, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13 + For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 + maintainers: - Kathiravan T @@ -86,6 +89,7 @@ properties: - qcom,rpm-pmi8994-regulators - qcom,rpm-pmi8998-regulators - qcom,rpm-pms405-regulators + - qcom,rpm-pm2250-regulators patternProperties: ".*-supply$": diff --git a/dts/Bindings/regulator/samsung,s2mpa01.txt b/dts/Bindings/regulator/samsung,s2mpa01.txt deleted file mode 100644 index bae3c7f838..0000000000 --- a/dts/Bindings/regulator/samsung,s2mpa01.txt +++ /dev/null @@ -1,79 +0,0 @@ -Binding for Samsung S2MPA01 regulator block -=========================================== - -This is a part of device tree bindings for S2M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPA01 device provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Names of regulators supported by S2MPA01 device: - - LDOn - - valid values for n are 1 to 26 - - Example: LDO1, LD02, LDO26 - - BUCKn - - valid values for n are 1 to 10. - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of buck regulator nodes under "regulators" sub-node: - - regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500 - (default), 25000, or 50000. May be 0 for disabling the ramp delay on - BUCK{1,2,3,4}. - - In the absence of the regulator-ramp-delay property, the default ramp - delay will be used. - - Note: Some bucks share the ramp rate setting i.e. same ramp value - will be set for a particular group of bucks so provide the same - regulator-ramp-delay value for them. - Groups sharing ramp rate: - - buck{1,6}, - - buck{2,4}, - - buck{8,9,10}. - -Example: - - s2mpa01_pmic@66 { - compatible = "samsung,s2mpa01-pmic"; - reg = <0x66>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_MMC2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/dts/Bindings/regulator/samsung,s2mpa01.yaml b/dts/Bindings/regulator/samsung,s2mpa01.yaml new file mode 100644 index 0000000000..0627dec513 --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mpa01.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpa01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPA01 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPA01 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mpa01.yaml for + additional information and example. + +patternProperties: + # 26 LDOs + "^LDO([1-9]|1[0-9]|2[0-6])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 10 bucks + "^BUCK([1-9]|10)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + properties: + regulator-ramp-delay: + enum: [0, 6250, 12500, 25000, 50000] + default: 12500 + description: | + May be 0 for disabling the ramp delay on BUCK{1,2,3,4}. + + In the absence of the regulator-ramp-delay property, the default ramp + delay will be used. + + Note: Some bucks share the ramp rate setting i.e. same ramp value + will be set for a particular group of bucks so provide the same + regulator-ramp-delay value for them. + Groups sharing ramp rate: + * buck{1,6}, + * buck{2,4}, + * buck{8,9,10}. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s2mps11.txt b/dts/Bindings/regulator/samsung,s2mps11.txt deleted file mode 100644 index 27a48bf1b1..0000000000 --- a/dts/Bindings/regulator/samsung,s2mps11.txt +++ /dev/null @@ -1,102 +0,0 @@ -Binding for Samsung S2M family regulator block -============================================== - -This is a part of device tree bindings for S2M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPS11/13/14/15 and S2MPU02 devices provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Names of regulators supported by different devices: - - LDOn - - valid values for n are: - - S2MPS11: 1 to 38 - - S2MPS13: 1 to 40 - - S2MPS14: 1 to 25 - - S2MPS15: 1 to 27 - - S2MPU02: 1 to 28 - - Example: LDO1, LDO2, LDO28 - - BUCKn - - valid values for n are: - - S2MPS11: 1 to 10 - - S2MPS13: 1 to 10 - - S2MPS14: 1 to 5 - - S2MPS15: 1 to 10 - - S2MPU02: 1 to 7 - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of the nodes under "regulators" sub-node: - - regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500, - 25000 (default) or 50000. - - Additionally S2MPS11 supports disabling ramp delay for BUCK{2,3,4,6} - by setting it to <0>. - - Note: On S2MPS11 some bucks share the ramp rate setting i.e. same ramp value - will be set for a particular group of bucks so provide the same - regulator-ramp-delay value for them. - Groups sharing ramp rate: - - buck{1,6}, - - buck{3,4}, - - buck{7,8,10}. - - - samsung,ext-control-gpios: On S2MPS14 the LDO10, LDO11 and LDO12 can be - configured to external control over GPIO. To turn this feature on this - property must be added to the regulator sub-node: - - samsung,ext-control-gpios: GPIO specifier for one GPIO - controlling this regulator (enable/disable) - Example: - LDO12 { - regulator-name = "V_EMMC_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - samsung,ext-control-gpios = <&gpk0 2 0>; - }; - - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/dts/Bindings/regulator/samsung,s2mps11.yaml b/dts/Bindings/regulator/samsung,s2mps11.yaml new file mode 100644 index 0000000000..e3b780715f --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mps11.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mps11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS11 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS11 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 38 LDOs + "^LDO([1-9]|[1-2][0-9]|3[0-8])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 10 bucks + "^BUCK([1-9]|10)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s2mps13.yaml b/dts/Bindings/regulator/samsung,s2mps13.yaml new file mode 100644 index 0000000000..579d77aefc --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mps13.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mps13.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS13 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS13 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 40 LDOs + "^LDO([1-9]|[1-3][0-9]|40)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 10 bucks + "^BUCK([1-9]|10)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s2mps14.yaml b/dts/Bindings/regulator/samsung,s2mps14.yaml new file mode 100644 index 0000000000..fdea290b3e --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mps14.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mps14.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS14 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS14 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 25 LDOs + "^LDO([1-9]|[1][0-9]|2[0-5])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 5 bucks + "^BUCK[1-5]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s2mps15.yaml b/dts/Bindings/regulator/samsung,s2mps15.yaml new file mode 100644 index 0000000000..b3a883c946 --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mps15.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mps15.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS15 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS15 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 27 LDOs + "^LDO([1-9]|[1][0-9]|2[0-7])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 10 bucks + "^BUCK([1-9]|10)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s2mpu02.yaml b/dts/Bindings/regulator/samsung,s2mpu02.yaml new file mode 100644 index 0000000000..0ded6953e3 --- /dev/null +++ b/dts/Bindings/regulator/samsung,s2mpu02.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpu02.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPU02 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPU02 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 28 LDOs + "^LDO([1-9]|1[0-9]|2[0-8])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + + # 7 bucks + "^BUCK[1-7]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/samsung,s5m8767.txt b/dts/Bindings/regulator/samsung,s5m8767.txt deleted file mode 100644 index 093edda0c8..0000000000 --- a/dts/Bindings/regulator/samsung,s5m8767.txt +++ /dev/null @@ -1,145 +0,0 @@ -Binding for Samsung S5M8767 regulator block -=========================================== - -This is a part of device tree bindings for S5M family multi-function devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S5M8767 device provide buck and LDO regulators. - -To register these with regulator framework instantiate under main device node -a sub-node named "regulators" with more sub-nodes for each regulator using the -common regulator binding documented in: - - Documentation/devicetree/bindings/regulator/regulator.txt - - -Required properties of the main device node (the parent!): - - s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck2 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck3-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck3 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck4-dvs-voltage: A set of 8 voltage values in micro-volt (uV) - units for buck4 when changing voltage using gpio dvs. Refer to [1] below - for additional information. - - - s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used - for selecting GPIO DVS lines. It is one-to-one mapped to dvs gpio lines. - - [1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional - property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage' - property should specify atleast one voltage level (which would be a - safe operating voltage). - - If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional - property is specified, then all the eight voltage values for the - 's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified. - -Optional properties of the main device node (the parent!): - - s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. - - s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs. - - s5m8767,pmic-buck4-uses-gpio-dvs: 'buck4' can be controlled by gpio dvs. - -Additional properties required if either of the optional properties are used: - - - s5m8767,pmic-buck234-default-dvs-idx: Default voltage setting selected from - the possible 8 options selectable by the dvs gpios. The value of this - property should be between 0 and 7. If not specified or if out of range, the - default value of this property is set to 0. - - - s5m8767,pmic-buck-dvs-gpios: GPIO specifiers for three host gpio's used - for dvs. The format of the gpio specifier depends in the gpio controller. - - -Names of regulators supported by S5M8767 device: - - LDOn - - valid values for n are 1 to 28 - - Example: LDO1, LDO2, LDO28 - - BUCKn - - valid values for n are 1 to 9. - - Example: BUCK1, BUCK2, BUCK9 -Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number -as per the datasheet of device. - - -Optional properties of the nodes under "regulators" sub-node: - - op_mode: describes the different operating modes of the LDO's with - power mode change in SOC. The different possible values are, - 0 - always off mode - 1 - on in normal mode - 2 - low power mode - 3 - suspend mode - - s5m8767,pmic-ext-control-gpios: (optional) GPIO specifier for one - GPIO controlling this regulator - (enable/disable); This is valid only - for buck9. - -Example: - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck2-uses-gpio-dvs; - s5m8767,pmic-buck3-uses-gpio-dvs; - s5m8767,pmic-buck4-uses-gpio-dvs; - - s5m8767,pmic-buck-default-dvs-idx = <0>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx0 0 0>, /* DVS1 */ - <&gpx0 1 0>, /* DVS2 */ - <&gpx0 2 0>; /* DVS3 */ - - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, /* SET1 */ - <&gpx2 4 0>, /* SET2 */ - <&gpx2 5 0>; /* SET3 */ - - s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vemmc_reg: BUCK9 { - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <3>; /* Standby Mode */ - s5m8767,pmic-ext-control-gpios = <&gpk0 2 0>; - }; - }; - }; diff --git a/dts/Bindings/regulator/samsung,s5m8767.yaml b/dts/Bindings/regulator/samsung,s5m8767.yaml new file mode 100644 index 0000000000..80a63d4779 --- /dev/null +++ b/dts/Bindings/regulator/samsung,s5m8767.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s5m8767.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5M8767 Power Management IC regulators + +maintainers: + - Krzysztof Kozlowski + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S5M8767 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s5m8767.yaml for + additional information and example. + +patternProperties: + # 28 LDOs + "^LDO([1-9]|1[0-9]|2[0-8])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + op_mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + description: | + Describes the different operating modes of the LDO's with power mode + change in SOC. The different possible values are: + 0 - always off mode + 1 - on in normal mode + 2 - low power mode + 3 - suspend mode + + required: + - regulator-name + + # 8 bucks + "^BUCK[1-8]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + + # 9 buck + "^BUCK9$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + properties: + s5m8767,pmic-ext-control-gpios: + maxItems: 1 + description: | + GPIO specifier for one GPIO controlling this regulator on/off. + + required: + - regulator-name + +additionalProperties: false diff --git a/dts/Bindings/regulator/silergy,sy8106a.yaml b/dts/Bindings/regulator/silergy,sy8106a.yaml new file mode 100644 index 0000000000..a52a67c869 --- /dev/null +++ b/dts/Bindings/regulator/silergy,sy8106a.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/silergy,sy8106a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silergy SY8106A Voltage Regulator Device Tree Bindings + +maintainers: + - Ondrej Jirman + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: silergy,sy8106a + + reg: + maxItems: 1 + + silergy,fixed-microvolt: + description: > + The voltage when I2C regulating is disabled (set by external resistor + like a fixed voltage) + +required: + - compatible + - reg + - silergy,fixed-microvolt + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@65 { + compatible = "silergy,sy8106a"; + reg = <0x65>; + regulator-name = "sy8106a-vdd"; + silergy,fixed-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + }; + +... diff --git a/dts/Bindings/regulator/socionext,uniphier-regulator.yaml b/dts/Bindings/regulator/socionext,uniphier-regulator.yaml index 861d5f3c79..1218f21ba3 100644 --- a/dts/Bindings/regulator/socionext,uniphier-regulator.yaml +++ b/dts/Bindings/regulator/socionext,uniphier-regulator.yaml @@ -27,6 +27,7 @@ properties: - socionext,uniphier-pxs2-usb3-regulator - socionext,uniphier-ld20-usb3-regulator - socionext,uniphier-pxs3-usb3-regulator + - socionext,uniphier-nx1-usb3-regulator reg: maxItems: 1 diff --git a/dts/Bindings/regulator/st,stm32-booster.yaml b/dts/Bindings/regulator/st,stm32-booster.yaml index 9f1c70381b..df0191b1ce 100644 --- a/dts/Bindings/regulator/st,stm32-booster.yaml +++ b/dts/Bindings/regulator/st,stm32-booster.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 booster for ADC analog input switches bindings maintainers: - - Fabrice Gasnier + - Fabrice Gasnier description: | Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used diff --git a/dts/Bindings/regulator/st,stm32-vrefbuf.yaml b/dts/Bindings/regulator/st,stm32-vrefbuf.yaml index 3cd4a254e4..836d4156d5 100644 --- a/dts/Bindings/regulator/st,stm32-vrefbuf.yaml +++ b/dts/Bindings/regulator/st,stm32-vrefbuf.yaml @@ -12,7 +12,7 @@ description: | components through the dedicated VREF+ pin. maintainers: - - Fabrice Gasnier + - Fabrice Gasnier allOf: - $ref: "regulator.yaml#" diff --git a/dts/Bindings/regulator/st,stm32mp1-pwr-reg.yaml b/dts/Bindings/regulator/st,stm32mp1-pwr-reg.yaml index e6322bc3e4..bd07b9c815 100644 --- a/dts/Bindings/regulator/st,stm32mp1-pwr-reg.yaml +++ b/dts/Bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STM32MP1 PWR voltage regulators maintainers: - - Pascal Paillet + - Pascal Paillet properties: compatible: diff --git a/dts/Bindings/regulator/sy8106a-regulator.txt b/dts/Bindings/regulator/sy8106a-regulator.txt deleted file mode 100644 index 39a8ca73f5..0000000000 --- a/dts/Bindings/regulator/sy8106a-regulator.txt +++ /dev/null @@ -1,23 +0,0 @@ -SY8106A Voltage regulator - -Required properties: -- compatible: Must be "silergy,sy8106a" -- reg: I2C slave address - must be <0x65> -- silergy,fixed-microvolt - the voltage when I2C regulating is disabled (set - by external resistor like a fixed voltage) - -Any property defined as part of the core regulator binding, defined in -./regulator.txt, can also be used. - -Example: - - sy8106a { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "sy8106a-vdd"; - silergy,fixed-microvolt = <1200000>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; diff --git a/dts/Bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/dts/Bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml new file mode 100644 index 0000000000..d892d29a65 --- /dev/null +++ b/dts/Bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson AO ARC Remote Processor bindings + +description: + Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core + controller for always-on operations, typically used for managing + system suspend. Meson6 and older use a ARC core based on the ARCv1 + ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA) + core. + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + items: + - enum: + - amlogic,meson8-ao-arc + - amlogic,meson8b-ao-arc + - const: amlogic,meson-mx-ao-arc + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + + reg: + description: + Address ranges of the remap and CPU control addresses for the + remote processor. + minItems: 2 + + reg-names: + items: + - const: remap + - const: cpu + + resets: + minItems: 1 + + clocks: + minItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandles to a reserved SRAM region which is used as the memory of + the ARC core. The region should be defined as child nodes of the + AHB SRAM node as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + amlogic,secbus2: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the SECBUS2 region which contains some configuration + bits of this remote processor + +required: + - compatible + - reg + - reg-names + - resets + - clocks + - sram + - amlogic,secbus2 + +additionalProperties: false + +examples: + - | + remoteproc@1c { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + resets = <&media_cpu_reset>; + clocks = <&media_cpu_clock>; + sram = <&ahb_sram_ao_arc>; + amlogic,secbus2 = <&secbus2>; + }; + +... diff --git a/dts/Bindings/remoteproc/ingenic,vpu.yaml b/dts/Bindings/remoteproc/ingenic,vpu.yaml index d0aa91bbf5..aaaaabad46 100644 --- a/dts/Bindings/remoteproc/ingenic,vpu.yaml +++ b/dts/Bindings/remoteproc/ingenic,vpu.yaml @@ -58,7 +58,7 @@ additionalProperties: false examples: - | - #include + #include vpu: video-decoder@132a0000 { compatible = "ingenic,jz4770-vpu-rproc"; diff --git a/dts/Bindings/remoteproc/mtk,scp.txt b/dts/Bindings/remoteproc/mtk,scp.txt deleted file mode 100644 index 3f5f78764b..0000000000 --- a/dts/Bindings/remoteproc/mtk,scp.txt +++ /dev/null @@ -1,36 +0,0 @@ -Mediatek SCP Bindings ----------------------------------------- - -This binding provides support for ARM Cortex M4 Co-processor found on some -Mediatek SoCs. - -Required properties: -- compatible Should be "mediatek,mt8183-scp" -- reg Should contain the address ranges for memory regions: - SRAM, CFG, and L1TCM. -- reg-names Contains the corresponding names for the memory regions: - "sram", "cfg", and "l1tcm". -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- clock-names Contains the corresponding name for the clock. This - should be named "main". - -Subnodes --------- - -Subnodes of the SCP represent rpmsg devices. The names of the devices are not -important. The properties of these nodes are defined by the individual bindings -for the rpmsg devices - but must contain the following property: - -- mtk,rpmsg-name Contains the name for the rpmsg device. Used to match - the subnode to rpmsg device announced by SCP. - -Example: - - scp: scp@10500000 { - compatible = "mediatek,mt8183-scp"; - reg = <0 0x10500000 0 0x80000>, - <0 0x105c0000 0 0x5000>; - reg-names = "sram", "cfg"; - clocks = <&infracfg CLK_INFRA_SCPSYS>; - clock-names = "main"; - }; diff --git a/dts/Bindings/remoteproc/mtk,scp.yaml b/dts/Bindings/remoteproc/mtk,scp.yaml new file mode 100644 index 0000000000..d21a25ee96 --- /dev/null +++ b/dts/Bindings/remoteproc/mtk,scp.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SCP Bindings + +maintainers: + - Tinghan Shen + +description: + This binding provides support for ARM Cortex M4 Co-processor found on some + Mediatek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8183-scp + - mediatek,mt8192-scp + - mediatek,mt8195-scp + + reg: + description: + Should contain the address ranges for memory regions SRAM, CFG, and + L1TCM. + maxItems: 3 + + reg-names: + items: + - const: sram + - const: cfg + - const: l1tcm + + clocks: + description: + Clock for co-processor (see ../clock/clock-bindings.txt). + Required by mt8183 and mt8192. + maxItems: 1 + + clock-names: + const: main + +required: + - compatible + - reg + - reg-names + +if: + properties: + compatible: + enum: + - mediatek,mt8183-scp + - mediatek,mt8192-scp +then: + required: + - clocks + - clock-names + +additionalProperties: + type: object + description: + Subnodes of the SCP represent rpmsg devices. The names of the devices + are not important. The properties of these nodes are defined by the + individual bindings for the rpmsg devices. + properties: + mediatek,rpmsg-name: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Contains the name for the rpmsg device. Used to match + the subnode to rpmsg device announced by SCP. + + required: + - mediatek,rpmsg-name + +examples: + - | + #include + + scp@10500000 { + compatible = "mediatek,mt8183-scp"; + reg = <0x10500000 0x80000>, + <0x10700000 0x8000>, + <0x10720000 0xe0000>; + reg-names = "sram", "cfg", "l1tcm"; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + + cros_ec { + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + }; diff --git a/dts/Bindings/remoteproc/qcom,adsp.yaml b/dts/Bindings/remoteproc/qcom,adsp.yaml index 0c112f3264..63e06d93bc 100644 --- a/dts/Bindings/remoteproc/qcom,adsp.yaml +++ b/dts/Bindings/remoteproc/qcom,adsp.yaml @@ -25,6 +25,7 @@ properties: - qcom,qcs404-cdsp-pas - qcom,qcs404-wcss-pas - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas - qcom,sc8180x-mpss-pas @@ -93,6 +94,10 @@ properties: maxItems: 1 description: Reference to the reserved-memory for the Hexagon core + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: States used by the AP to signal the Hexagon core @@ -147,6 +152,7 @@ allOf: - qcom,msm8998-adsp-pas - qcom,qcs404-adsp-pas - qcom,qcs404-wcss-pas + - qcom,sc7280-mpss-pas - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas - qcom,sc8180x-mpss-pas @@ -292,6 +298,7 @@ allOf: contains: enum: - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas - qcom,sc8180x-mpss-pas - qcom,sdx55-mpss-pas - qcom,sm8150-mpss-pas @@ -369,13 +376,11 @@ allOf: properties: power-domains: items: - - description: Load State power domain - description: CX power domain - description: MX power domain - description: MSS power domain power-domain-names: items: - - const: load_state - const: cx - const: mx - const: mss @@ -391,39 +396,17 @@ allOf: properties: power-domains: items: - - description: Load State power domain - description: CX power domain - power-domain-names: - items: - - const: load_state - - const: cx - if: properties: compatible: contains: enum: + - qcom,sc7280-mpss-pas + - qcom,sdx55-mpss-pas - qcom,sm8150-mpss-pas - qcom,sm8350-mpss-pas - then: - properties: - power-domains: - items: - - description: Load State power domain - - description: CX power domain - - description: MSS power domain - power-domain-names: - items: - - const: load_state - - const: cx - - const: mss - - - if: - properties: - compatible: - contains: - enum: - - qcom,sdx55-mpss-pas then: properties: power-domains: @@ -451,12 +434,10 @@ allOf: properties: power-domains: items: - - description: Load State power domain - description: LCX power domain - description: LMX power domain power-domain-names: items: - - const: load_state - const: lcx - const: lmx @@ -470,12 +451,10 @@ allOf: properties: power-domains: items: - - description: Load State power domain - description: CX power domain - description: MXC power domain power-domain-names: items: - - const: load_state - const: cx - const: mxc @@ -500,6 +479,7 @@ allOf: contains: enum: - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas then: properties: resets: @@ -511,6 +491,25 @@ allOf: - const: mss_restart - const: pdc_reset + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8974-adsp-pil + - qcom,msm8996-adsp-pil + - qcom,msm8996-slpi-pil + - qcom,msm8998-adsp-pas + - qcom,msm8998-slpi-pas + - qcom,qcs404-adsp-pas + - qcom,qcs404-cdsp-pas + - qcom,qcs404-wcss-pas + - qcom,sdm660-adsp-pas + - qcom,sdx55-mpss-pas + then: + properties: + qcom,qmp: false + examples: - | #include diff --git a/dts/Bindings/remoteproc/qcom,q6v5.txt b/dts/Bindings/remoteproc/qcom,q6v5.txt index 69c49c7b2c..8f1507052a 100644 --- a/dts/Bindings/remoteproc/qcom,q6v5.txt +++ b/dts/Bindings/remoteproc/qcom,q6v5.txt @@ -15,6 +15,7 @@ on the Qualcomm Hexagon core. "qcom,msm8996-mss-pil" "qcom,msm8998-mss-pil" "qcom,sc7180-mss-pil" + "qcom,sc7280-mss-pil" "qcom,sdm845-mss-pil" - reg: @@ -47,6 +48,7 @@ on the Qualcomm Hexagon core. qcom,msm8996-mss-pil: qcom,msm8998-mss-pil: qcom,sc7180-mss-pil: + qcom,sc7280-mss-pil: qcom,sdm845-mss-pil: must be "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack" @@ -87,6 +89,8 @@ on the Qualcomm Hexagon core. qcom,sc7180-mss-pil: must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi", "nav" + qcom,sc7280-mss-pil: + must be "iface", "xo", "snoc_axi", "offline", "pka" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" @@ -98,7 +102,7 @@ on the Qualcomm Hexagon core. reference to the list of 3 reset-controllers for the wcss sub-system reference to the list of 2 reset-controllers for the modem - sub-system on SC7180, SDM845 SoCs + sub-system on SC7180, SC7280, SDM845 SoCs - reset-names: Usage: required @@ -107,7 +111,7 @@ on the Qualcomm Hexagon core. must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" for the wcss sub-system must be "mss_restart", "pdc_reset" for the modem - sub-system on SC7180, SDM845 SoCs + sub-system on SC7180, SC7280, SDM845 SoCs For devices where the mba and mpss sub-nodes are not specified, mba/mpss region should be referenced as follows: @@ -173,8 +177,16 @@ For the compatible string below the following supplies are required: qcom,msm8998-mss-pil: must be "cx", "mx" qcom,sc7180-mss-pil: + must be "cx", "mx", "mss" + qcom,sc7280-mss-pil: + must be "cx", "mss" qcom,sdm845-mss-pil: - must be "cx", "mx", "mss", "load_state" + must be "cx", "mx", "mss" + +- qcom,qmp: + Usage: optional + Value type: + Definition: reference to the AOSS side-channel message RAM. - qcom,smem-states: Usage: required @@ -193,6 +205,9 @@ For the compatible string below the following supplies are required: Definition: a phandle reference to a syscon representing TCSR followed by the three offsets within syscon for q6, modem and nc halt registers. + a phandle reference to a syscon representing TCSR followed + by the four offsets within syscon for q6, modem, nc and vq6 + halt registers on SC7280 SoCs. For the compatible strings below the following phandle references are required: "qcom,sc7180-mss-pil" @@ -203,6 +218,24 @@ For the compatible strings below the following phandle references are required: by the offset within syscon for conn_box_spare0 register used by the modem sub-system running on SC7180 SoC. +For the compatible strings below the following phandle references are required: + "qcom,sc7280-mss-pil" +- qcom,ext-regs: + Usage: required + Value type: + Definition: two phandle references to syscons representing TCSR_REG and + TCSR register space followed by the two offsets within the syscon + to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off + registers respectively. + +- qcom,qaccept-regs: + Usage: required + Value type: + Definition: a phandle reference to a syscon representing TCSR followed + by the three offsets within syscon for mdm, cx and axi + qaccept registers used by the modem sub-system running on + SC7280 SoC. + The Hexagon node must contain iommus property as described in ../iommu/iommu.txt on platforms which do not have TrustZone. diff --git a/dts/Bindings/remoteproc/st,stm32-rproc.yaml b/dts/Bindings/remoteproc/st,stm32-rproc.yaml index 1e6225677e..b587c97c28 100644 --- a/dts/Bindings/remoteproc/st,stm32-rproc.yaml +++ b/dts/Bindings/remoteproc/st,stm32-rproc.yaml @@ -11,8 +11,8 @@ description: boots firmwares on the ST32MP family chipset. maintainers: - - Fabien Dessenne - - Arnaud Pouliquen + - Fabien Dessenne + - Arnaud Pouliquen properties: compatible: diff --git a/dts/Bindings/remoteproc/ti,k3-dsp-rproc.yaml b/dts/Bindings/remoteproc/ti,k3-dsp-rproc.yaml index 6070456a7b..5ec6505ac4 100644 --- a/dts/Bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/dts/Bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -133,9 +133,7 @@ unevaluatedProperties: false examples: - | - / { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml b/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml index 130fbaacc4..eeef255c40 100644 --- a/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -230,9 +230,7 @@ additionalProperties: false examples: - | - / { - model = "Texas Instruments K3 AM654 SoC"; - compatible = "ti,am654-evm", "ti,am654"; + soc { #address-cells = <2>; #size-cells = <2>; diff --git a/dts/Bindings/reserved-memory/memory-region.yaml b/dts/Bindings/reserved-memory/memory-region.yaml new file mode 100644 index 0000000000..83dfe499a2 --- /dev/null +++ b/dts/Bindings/reserved-memory/memory-region.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/memory-region.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Reserved Memory Region Device Tree Binding + +maintainers: + - devicetree-spec@vger.kernel.org + +description: | + Regions in the /reserved-memory node may be referenced by other device + nodes by adding a memory-region property to the device node. + +select: true + +properties: + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: > + Phandle to a /reserved-memory child node assigned to the device. + + memory-region-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + A list of names, one for each corresponding entry in the + memory-region property + +additionalProperties: true + +examples: + - | + fb0: video@12300000 { + /* ... */ + reg = <0x12300000 0x1000>; + memory-region = <&display_reserved>; + }; + +... diff --git a/dts/Bindings/reserved-memory/ramoops.txt b/dts/Bindings/reserved-memory/ramoops.txt deleted file mode 100644 index b571ef6dab..0000000000 --- a/dts/Bindings/reserved-memory/ramoops.txt +++ /dev/null @@ -1,66 +0,0 @@ -Ramoops oops/panic logger -========================= - -ramoops provides persistent RAM storage for oops and panics, so they can be -recovered after a reboot. This is a child-node of "/reserved-memory", and -is named "ramoops" after the backend, rather than "pstore" which is the -subsystem. - -Parts of this storage may be set aside for other persistent log buffers, such -as kernel log messages, or for optional ECC error-correction data. The total -size of these optional buffers must fit in the reserved region. - -Any remaining space will be used for a circular buffer of oops and panic -records. These records have a configurable size, with a size of 0 indicating -that they should be disabled. - -At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size" -must be set non-zero, but are otherwise optional as listed below. - - -Required properties: - -- compatible: must be "ramoops" - -- reg: region of memory that is preserved between reboots - - -Optional properties: - -- ecc-size: enables ECC support and specifies ECC buffer size in bytes - (defaults to 0: no ECC) - -- record-size: maximum size in bytes of each kmsg dump. - (defaults to 0: disabled) - -- console-size: size in bytes of log buffer reserved for kernel messages - (defaults to 0: disabled) - -- ftrace-size: size in bytes of log buffer reserved for function tracing and - profiling (defaults to 0: disabled) - -- pmsg-size: size in bytes of log buffer reserved for userspace messages - (defaults to 0: disabled) - -- mem-type: if present, sets the type of mapping is to be used to map the - reserved region. mem-type: 0 = write-combined (default), 1 = unbuffered, - 2 = cached. - -- unbuffered: deprecated, use mem_type instead. If present, and mem_type is - not specified, it is equivalent to mem_type = 1 and uses unbuffered mappings - to map the reserved region (defaults to buffered mappings mem_type = 0). If - both are specified -- "mem_type" overrides "unbuffered". - -- max-reason: if present, sets maximum type of kmsg dump reasons to store - (defaults to 2: log Oopses and Panics). This can be set to INT_MAX to - store all kmsg dumps. See include/linux/kmsg_dump.h KMSG_DUMP_* for other - kmsg dump reason values. Setting this to 0 (KMSG_DUMP_UNDEF), means the - reason filtering will be controlled by the printk.always_kmsg_dump boot - param: if unset, it will be KMSG_DUMP_OOPS, otherwise KMSG_DUMP_MAX. - -- no-dump-oops: deprecated, use max_reason instead. If present, and - max_reason is not specified, it is equivalent to max_reason = 1 - (KMSG_DUMP_PANIC). - -- flags: if present, pass ramoops behavioral flags (defaults to 0, - see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). diff --git a/dts/Bindings/reserved-memory/ramoops.yaml b/dts/Bindings/reserved-memory/ramoops.yaml new file mode 100644 index 0000000000..f4c351a695 --- /dev/null +++ b/dts/Bindings/reserved-memory/ramoops.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reserved-memory/ramoops.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Ramoops oops/panic logger + +description: | + ramoops provides persistent RAM storage for oops and panics, so they can be + recovered after a reboot. This is a child-node of "/reserved-memory", and + is named "ramoops" after the backend, rather than "pstore" which is the + subsystem. + + Parts of this storage may be set aside for other persistent log buffers, such + as kernel log messages, or for optional ECC error-correction data. The total + size of these optional buffers must fit in the reserved region. + + Any remaining space will be used for a circular buffer of oops and panic + records. These records have a configurable size, with a size of 0 indicating + that they should be disabled. + + At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size" + must be set non-zero, but are otherwise optional as listed below. + +maintainers: + - Kees Cook + +allOf: + - $ref: "reserved-memory.yaml" + +properties: + compatible: + const: ramoops + + reg: + description: region of memory that is preserved between reboots + + ecc-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: enables ECC support and specifies ECC buffer size in bytes + default: 0 # no ECC + + record-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: maximum size in bytes of each kmsg dump + default: 0 + + console-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for kernel messages + default: 0 + + ftrace-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for function tracing and profiling + default: 0 + + pmsg-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for userspace messages + default: 0 + + mem-type: + $ref: /schemas/types.yaml#/definitions/uint32 + description: if present, sets the type of mapping is to be used to map the reserved region. + default: 0 + oneOf: + - const: 0 + description: write-combined + - const: 1 + description: unbuffered + - const: 2 + description: cached + + max-reason: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 # log oopses and panics + maximum: 0x7fffffff + description: | + If present, sets maximum type of kmsg dump reasons to store. + This can be set to INT_MAX to store all kmsg dumps. + See include/linux/kmsg_dump.h KMSG_DUMP_* for other kmsg dump reason values. + Setting this to 0 (KMSG_DUMP_UNDEF), means the reason filtering will be + controlled by the printk.always_kmsg_dump boot param. + If unset, it will be 2 (KMSG_DUMP_OOPS), otherwise 5 (KMSG_DUMP_MAX). + + flags: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: | + If present, pass ramoops behavioral flags + (see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). + + no-dump-oops: + deprecated: true + type: boolean + description: | + Use max_reason instead. If present, and max_reason is not specified, + it is equivalent to max_reason = 1 (KMSG_DUMP_PANIC). + + unbuffered: + deprecated: true + type: boolean + description: | + Use mem_type instead. If present, and mem_type is not specified, + it is equivalent to mem_type = 1 and uses unbuffered mappings to map + the reserved region (defaults to buffered mappings mem_type = 0). + If both are specified -- "mem_type" overrides "unbuffered". + +unevaluatedProperties: false + +required: + - compatible + - reg + +anyOf: + - required: [record-size] + - required: [console-size] + - required: [ftrace-size] + - required: [pmsg-size] + +examples: + - | + / { + compatible = "foo"; + model = "foo"; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + }; + }; + diff --git a/dts/Bindings/reserved-memory/reserved-memory.txt b/dts/Bindings/reserved-memory/reserved-memory.txt index 39b5f4c5a5..1810701a85 100644 --- a/dts/Bindings/reserved-memory/reserved-memory.txt +++ b/dts/Bindings/reserved-memory/reserved-memory.txt @@ -1,171 +1 @@ -*** Reserved memory regions *** - -Reserved memory is specified as a node under the /reserved-memory node. -The operating system shall exclude reserved memory from normal usage -one can create child nodes describing particular reserved (excluded from -normal use) memory regions. Such memory regions are usually designed for -the special usage by various device drivers. - -Parameters for each memory region can be encoded into the device tree -with the following nodes: - -/reserved-memory node ---------------------- -#address-cells, #size-cells (required) - standard definition - - Should use the same values as the root node -ranges (required) - standard definition - - Should be empty - -/reserved-memory/ child nodes ------------------------------ -Each child of the reserved-memory node specifies one or more regions of -reserved memory. Each child node may either use a 'reg' property to -specify a specific range of reserved memory, or a 'size' property with -optional constraints to request a dynamically allocated block of memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit -address (@
) should be appended to the name if the node is a -static allocation. - -Properties: -Requires either a) or b) below. -a) static allocation - reg (required) - standard definition -b) dynamic allocation - size (required) - length based on parent's #size-cells - - Size in bytes of memory to reserve. - alignment (optional) - length based on parent's #size-cells - - Address boundary for alignment of allocation. - alloc-ranges (optional) - prop-encoded-array (address, length pairs). - - Specifies regions of memory that are - acceptable to allocate from. - -If both reg and size are present, then the reg property takes precedence -and size is ignored. - -Additional properties: -compatible (optional) - standard definition - - may contain the following strings: - - shared-dma-pool: This indicates a region of memory meant to be - used as a shared pool of DMA buffers for a set of devices. It can - be used by an operating system to instantiate the necessary pool - management subsystem if necessary. - - restricted-dma-pool: This indicates a region of memory meant to be - used as a pool of restricted DMA buffers for a set of devices. The - memory region would be the only region accessible to those devices. - When using this, the no-map and reusable properties must not be set, - so the operating system can create a virtual mapping that will be used - for synchronization. The main purpose for restricted DMA is to - mitigate the lack of DMA access control on systems without an IOMMU, - which could result in the DMA accessing the system memory at - unexpected times and/or unexpected addresses, possibly leading to data - leakage or corruption. The feature on its own provides a basic level - of protection against the DMA overwriting buffer contents at - unexpected times. However, to protect against general data leakage and - system memory corruption, the system needs to provide way to lock down - the memory access, e.g., MPU. Note that since coherent allocation - needs remapping, one must set up another device coherent pool by - shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic - coherent allocation. - - vendor specific string in the form ,[-] -no-map (optional) - empty property - - Indicates the operating system must not create a virtual mapping - of the region as part of its standard mapping of system memory, - nor permit speculative access to it under any circumstances other - than under the control of the device driver using the region. -reusable (optional) - empty property - - The operating system can use the memory in this region with the - limitation that the device driver(s) owning the region need to be - able to reclaim it back. Typically that means that the operating - system can use that region to store volatile or cached data that - can be otherwise regenerated or migrated elsewhere. - -A node must not carry both the no-map and the reusable property as these are -logically contradictory. - -Linux implementation note: -- If a "linux,cma-default" property is present, then Linux will use the - region for the default pool of the contiguous memory allocator. - -- If a "linux,dma-default" property is present, then Linux will use the - region for the default pool of the consistent DMA allocator. - -Device node references to reserved memory ------------------------------------------ -Regions in the /reserved-memory node may be referenced by other device -nodes by adding a memory-region property to the device node. - -memory-region (optional) - phandle, specifier pairs to children of /reserved-memory -memory-region-names (optional) - a list of names, one for each corresponding - entry in the memory-region property - -Example -------- -This example defines 4 contiguous regions for Linux kernel: -one default of all device drivers (named linux,cma@72000000 and 64MiB in size), -one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), -one for multimedia processing (named multimedia-memory@77000000, 64MiB), and -one for restricted dma pool (named restricted_dma_reserved@0x50000000, 64MiB). - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0x40000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x4000000>; - alignment = <0x2000>; - linux,cma-default; - }; - - display_reserved: framebuffer@78000000 { - reg = <0x78000000 0x800000>; - }; - - multimedia_reserved: multimedia@77000000 { - compatible = "acme,multimedia-memory"; - reg = <0x77000000 0x4000000>; - }; - - restricted_dma_reserved: restricted_dma_reserved { - compatible = "restricted-dma-pool"; - reg = <0x50000000 0x4000000>; - }; - }; - - /* ... */ - - fb0: video@12300000 { - memory-region = <&display_reserved>; - /* ... */ - }; - - scaler: scaler@12500000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; - - codec: codec@12600000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; - - pcie_device: pcie_device@0,0 { - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; - memory-region = <&restricted_dma_reserved>; - /* ... */ - }; -}; +This file has been moved to reserved-memory.yaml. diff --git a/dts/Bindings/reserved-memory/reserved-memory.yaml b/dts/Bindings/reserved-memory/reserved-memory.yaml new file mode 100644 index 0000000000..7a0744052f --- /dev/null +++ b/dts/Bindings/reserved-memory/reserved-memory.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: /reserved-memory Child Node Common Device Tree Bindings + +maintainers: + - devicetree-spec@vger.kernel.org + +description: > + Reserved memory is specified as a node under the /reserved-memory node. The + operating system shall exclude reserved memory from normal usage one can + create child nodes describing particular reserved (excluded from normal use) + memory regions. Such memory regions are usually designed for the special + usage by various device drivers. + + Each child of the reserved-memory node specifies one or more regions + of reserved memory. Each child node may either use a 'reg' property to + specify a specific range of reserved memory, or a 'size' property with + optional constraints to request a dynamically allocated block of + memory. + + Following the generic-names recommended practice, node names should + reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). + Unit address (@
) should be appended to the name if the node + is a static allocation. + +properties: + reg: true + + size: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + description: > + Length based on parent's \#size-cells. Size in bytes of memory to + reserve. + + alignment: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + description: > + Length based on parent's \#size-cells. Address boundary for + alignment of allocation. + + alloc-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + Address and Length pairs. Specifies regions of memory that are + acceptable to allocate from. + + no-map: + type: boolean + description: > + Indicates the operating system must not create a virtual mapping + of the region as part of its standard mapping of system memory, + nor permit speculative access to it under any circumstances other + than under the control of the device driver using the region. + + reusable: + type: boolean + description: > + The operating system can use the memory in this region with the + limitation that the device driver(s) owning the region need to be + able to reclaim it back. Typically that means that the operating + system can use that region to store volatile or cached data that + can be otherwise regenerated or migrated elsewhere. + +allOf: + - if: + required: + - no-map + + then: + not: + required: + - reusable + + - if: + required: + - reusable + + then: + not: + required: + - no-map + +oneOf: + - required: + - reg + + - required: + - size + +additionalProperties: true + +... diff --git a/dts/Bindings/reserved-memory/shared-dma-pool.yaml b/dts/Bindings/reserved-memory/shared-dma-pool.yaml new file mode 100644 index 0000000000..a4bf757d68 --- /dev/null +++ b/dts/Bindings/reserved-memory/shared-dma-pool.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: /reserved-memory DMA pool node bindings + +maintainers: + - devicetree-spec@vger.kernel.org + +allOf: + - $ref: "reserved-memory.yaml" + +properties: + compatible: + oneOf: + - const: shared-dma-pool + description: > + This indicates a region of memory meant to be used as a shared + pool of DMA buffers for a set of devices. It can be used by an + operating system to instantiate the necessary pool management + subsystem if necessary. + + - const: restricted-dma-pool + description: > + This indicates a region of memory meant to be used as a pool + of restricted DMA buffers for a set of devices. The memory + region would be the only region accessible to those devices. + When using this, the no-map and reusable properties must not + be set, so the operating system can create a virtual mapping + that will be used for synchronization. The main purpose for + restricted DMA is to mitigate the lack of DMA access control + on systems without an IOMMU, which could result in the DMA + accessing the system memory at unexpected times and/or + unexpected addresses, possibly leading to data leakage or + corruption. The feature on its own provides a basic level of + protection against the DMA overwriting buffer contents at + unexpected times. However, to protect against general data + leakage and system memory corruption, the system needs to + provide way to lock down the memory access, e.g., MPU. Note + that since coherent allocation needs remapping, one must set + up another device coherent pool by shared-dma-pool and use + dma_alloc_from_dev_coherent instead for atomic coherent + allocation. + + linux,cma-default: + type: boolean + description: > + If this property is present, then Linux will use the region for + the default pool of the contiguous memory allocator. + + linux,dma-default: + type: boolean + description: > + If this property is present, then Linux will use the region for + the default pool of the consistent DMA allocator. + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + display_reserved: framebuffer@78000000 { + reg = <0x78000000 0x800000>; + }; + + restricted_dma_reserved: restricted-dma-pool@50000000 { + compatible = "restricted-dma-pool"; + reg = <0x50000000 0x4000000>; + }; + }; + +... diff --git a/dts/Bindings/reset/microchip,rst.yaml b/dts/Bindings/reset/microchip,rst.yaml index 370579aeec..578bfa529b 100644 --- a/dts/Bindings/reset/microchip,rst.yaml +++ b/dts/Bindings/reset/microchip,rst.yaml @@ -20,7 +20,9 @@ properties: pattern: "^reset-controller@[0-9a-f]+$" compatible: - const: microchip,sparx5-switch-reset + enum: + - microchip,sparx5-switch-reset + - microchip,lan966x-switch-reset reg: items: diff --git a/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml b/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml index 29e4a900ca..bfbd3e9b41 100644 --- a/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml +++ b/dts/Bindings/reset/socionext,uniphier-glue-reset.yaml @@ -23,6 +23,7 @@ properties: - socionext,uniphier-pxs2-usb3-reset - socionext,uniphier-ld20-usb3-reset - socionext,uniphier-pxs3-usb3-reset + - socionext,uniphier-nx1-usb3-reset - socionext,uniphier-pro4-ahci-reset - socionext,uniphier-pxs2-ahci-reset - socionext,uniphier-pxs3-ahci-reset diff --git a/dts/Bindings/reset/socionext,uniphier-reset.yaml b/dts/Bindings/reset/socionext,uniphier-reset.yaml index 4c9b0ebf68..377a7d2423 100644 --- a/dts/Bindings/reset/socionext,uniphier-reset.yaml +++ b/dts/Bindings/reset/socionext,uniphier-reset.yaml @@ -23,6 +23,7 @@ properties: - socionext,uniphier-ld11-reset - socionext,uniphier-ld20-reset - socionext,uniphier-pxs3-reset + - socionext,uniphier-nx1-reset - description: Media I/O (MIO) reset, SD reset enum: - socionext,uniphier-ld4-mio-reset @@ -34,6 +35,7 @@ properties: - socionext,uniphier-ld11-sd-reset - socionext,uniphier-ld20-sd-reset - socionext,uniphier-pxs3-sd-reset + - socionext,uniphier-nx1-sd-reset - description: Peripheral reset enum: - socionext,uniphier-ld4-peri-reset @@ -44,6 +46,7 @@ properties: - socionext,uniphier-ld11-peri-reset - socionext,uniphier-ld20-peri-reset - socionext,uniphier-pxs3-peri-reset + - socionext,uniphier-nx1-peri-reset - description: Analog signal amplifier reset enum: - socionext,uniphier-ld11-adamv-reset diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml index e534f6a7cf..aa5fb64d57 100644 --- a/dts/Bindings/riscv/cpus.yaml +++ b/dts/Bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set diff --git a/dts/Bindings/rng/ingenic,trng.yaml b/dts/Bindings/rng/ingenic,trng.yaml index 808f247c84..044d9a0656 100644 --- a/dts/Bindings/rng/ingenic,trng.yaml +++ b/dts/Bindings/rng/ingenic,trng.yaml @@ -32,7 +32,7 @@ additionalProperties: false examples: - | - #include + #include dtrng: trng@10072000 { compatible = "ingenic,x1830-dtrng"; diff --git a/dts/Bindings/rng/omap_rng.txt b/dts/Bindings/rng/omap_rng.txt deleted file mode 100644 index ea434ce50f..0000000000 --- a/dts/Bindings/rng/omap_rng.txt +++ /dev/null @@ -1,38 +0,0 @@ -OMAP SoC and Inside-Secure HWRNG Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - RNG versions: - - "ti,omap2-rng" for OMAP2. - - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX. - - "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block - Note that these two versions are incompatible. -- ti,hwmods: Name of the hwmod associated with the RNG module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt number for the RNG module. - Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76" -- clocks: the trng clock source. Only mandatory for the - "inside-secure,safexcel-eip76" compatible, the second clock is - needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - - -Example: -/* AM335x */ -rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; -}; - -/* SafeXcel IP-76 */ -trng: rng@f2760000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xf2760000 0x7d>; - interrupts = ; - clocks = <&cpm_syscon0 1 25>; -}; diff --git a/dts/Bindings/rng/omap_rng.yaml b/dts/Bindings/rng/omap_rng.yaml new file mode 100644 index 0000000000..010188cdbe --- /dev/null +++ b/dts/Bindings/rng/omap_rng.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/omap_rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP SoC and Inside-Secure HWRNG Module + +maintainers: + - Jayesh Choudhary + +properties: + compatible: + enum: + - ti,omap2-rng + - ti,omap4-rng + - inside-secure,safexcel-eip76 + + ti,hwmods: + const: rng + deprecated: true + description: Name of the hwmod associated with the RNG module + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: EIP150 gatable clock + - description: Main gatable clock + + clock-names: + minItems: 1 + items: + - const: core + - const: reg + + +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,omap4-rng + - inside-secure,safexcel-eip76 + + then: + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - inside-secure,safexcel-eip76 + + then: + required: + - clocks + + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + /* AM335x */ + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = <111>; + }; + - | + /* SafeXcel IP-76 */ + trng: rng@f2760000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0xf2760000 0x7d>; + interrupts = <0 59 4>; + clocks = <&cpm_syscon0 1 25>; + }; + +... diff --git a/dts/Bindings/rng/st,stm32-rng.yaml b/dts/Bindings/rng/st,stm32-rng.yaml index 82bb2e97e8..9a6e4eaf4d 100644 --- a/dts/Bindings/rng/st,stm32-rng.yaml +++ b/dts/Bindings/rng/st,stm32-rng.yaml @@ -11,7 +11,7 @@ description: | IP and is fully separated from other crypto functions. maintainers: - - Lionel Debieve + - Lionel Debieve properties: compatible: diff --git a/dts/Bindings/rtc/ingenic,rtc.yaml b/dts/Bindings/rtc/ingenic,rtc.yaml index 60e93e86ad..b235b24419 100644 --- a/dts/Bindings/rtc/ingenic,rtc.yaml +++ b/dts/Bindings/rtc/ingenic,rtc.yaml @@ -72,7 +72,7 @@ unevaluatedProperties: false examples: - | - #include + #include rtc_dev: rtc@10003000 { compatible = "ingenic,jz4740-rtc"; reg = <0x10003000 0x40>; diff --git a/dts/Bindings/rtc/mstar,msc313-rtc.yaml b/dts/Bindings/rtc/mstar,msc313-rtc.yaml new file mode 100644 index 0000000000..114199cf4d --- /dev/null +++ b/dts/Bindings/rtc/mstar,msc313-rtc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mstar,msc313-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e RTC Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + enum: + - mstar,msc313-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + start-year: true + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + rtc@2400 { + compatible = "mstar,msc313-rtc"; + reg = <0x2400 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/dts/Bindings/rtc/nxp,pcf85063.txt b/dts/Bindings/rtc/nxp,pcf85063.txt index 627bb533ef..6439682c93 100644 --- a/dts/Bindings/rtc/nxp,pcf85063.txt +++ b/dts/Bindings/rtc/nxp,pcf85063.txt @@ -13,10 +13,19 @@ Optional property: expressed in femto Farad (fF). Valid values are 7000 and 12500. Default value (if no value is specified) is 7000fF. +Optional child node: +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. + Example: pcf85063: rtc@51 { compatible = "nxp,pcf85063"; reg = <0x51>; quartz-load-femtofarads = <12500>; + + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; diff --git a/dts/Bindings/rtc/st,stm32-rtc.yaml b/dts/Bindings/rtc/st,stm32-rtc.yaml index 5456604b1c..2359f541b7 100644 --- a/dts/Bindings/rtc/st,stm32-rtc.yaml +++ b/dts/Bindings/rtc/st,stm32-rtc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Real Time Clock Bindings maintainers: - - Gabriel Fernandez + - Gabriel Fernandez properties: compatible: diff --git a/dts/Bindings/serial/8250_omap.yaml b/dts/Bindings/serial/8250_omap.yaml index 70ca61688b..7b34ec8fa9 100644 --- a/dts/Bindings/serial/8250_omap.yaml +++ b/dts/Bindings/serial/8250_omap.yaml @@ -86,7 +86,7 @@ required: - reg - interrupts -additionalProperties: false +unevaluatedProperties: false if: properties: diff --git a/dts/Bindings/serial/brcm,bcm6345-uart.txt b/dts/Bindings/serial/brcm,bcm6345-uart.txt deleted file mode 100644 index 8b2b046025..0000000000 --- a/dts/Bindings/serial/brcm,bcm6345-uart.txt +++ /dev/null @@ -1,36 +0,0 @@ -* BCM63xx UART - -Required properties: - -- compatible: "brcm,bcm6345-uart" - -- reg: The base address of the UART register bank. - -- interrupts: A single interrupt specifier. - -- clocks: Clock driving the hardware; used to figure out the baud rate - divisor. - - -Optional properties: - -- clock-names: Should be "refclk". - -Example: - - uart0: serial@14e00520 { - compatible = "brcm,bcm6345-uart"; - reg = <0x14e00520 0x18>; - interrupt-parent = <&periph_intc>; - interrupts = <2>; - clocks = <&periph_clk>; - clock-names = "refclk"; - }; - - clocks { - periph_clk: periph_clk@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <54000000>; - }; - }; diff --git a/dts/Bindings/serial/brcm,bcm6345-uart.yaml b/dts/Bindings/serial/brcm,bcm6345-uart.yaml new file mode 100644 index 0000000000..a22285c43f --- /dev/null +++ b/dts/Bindings/serial/brcm,bcm6345-uart.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/brcm,bcm6345-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM63xx UART + +maintainers: + - Rafał Miłecki + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: brcm,bcm6345-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: refclk + +unevaluatedProperties: false + +required: + - reg + - interrupts + - clocks + +examples: + - | + serial@14e00520 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00520 0x18>; + interrupt-parent = <&periph_intc>; + interrupts = <2>; + clocks = <&periph_clk>; + clock-names = "refclk"; + }; diff --git a/dts/Bindings/serial/fsl,s32-linflexuart.txt b/dts/Bindings/serial/fsl,s32-linflexuart.txt deleted file mode 100644 index f1bbe0826b..0000000000 --- a/dts/Bindings/serial/fsl,s32-linflexuart.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Freescale LINFlexD UART - -The LINFlexD controller implements several LIN protocol versions, as well as -support for full-duplex UART communication through 8-bit and 9-bit frames. - -See chapter 47 ("LINFlexD") in the reference manual[1]. - -Required properties: -- compatible : - - "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which - is compatible with the one integrated on S32V234 SoC -- reg : Address and length of the register set for the device -- interrupts : Should contain uart interrupt - -Example: -uart0: serial@40053000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x40053000 0x0 0x1000>; - interrupts = <0 59 4>; -}; - -[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/dts/Bindings/serial/fsl,s32-linflexuart.yaml b/dts/Bindings/serial/fsl,s32-linflexuart.yaml new file mode 100644 index 0000000000..8b643bae3c --- /dev/null +++ b/dts/Bindings/serial/fsl,s32-linflexuart.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale LINFlexD UART + +description: | + The LINFlexD controller implements several LIN protocol versions, as well + as support for full-duplex UART communication through 8-bit and 9-bit + frames. See chapter 47 ("LINFlexD") in the reference manual + https://www.nxp.com/webapp/Download?colCode=S32V234RM. + +maintainers: + - Chester Lin + +allOf: + - $ref: "serial.yaml" + +properties: + compatible: + oneOf: + - const: fsl,s32v234-linflexuart + - items: + - const: nxp,s32g2-linflexuart + - const: fsl,s32v234-linflexuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@40053000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x40053000 0x1000>; + interrupts = <0 59 4>; + }; diff --git a/dts/Bindings/serial/ingenic,uart.yaml b/dts/Bindings/serial/ingenic,uart.yaml index b432d4dff7..9ca7a18ecd 100644 --- a/dts/Bindings/serial/ingenic,uart.yaml +++ b/dts/Bindings/serial/ingenic,uart.yaml @@ -71,7 +71,7 @@ unevaluatedProperties: false examples: - | - #include + #include #include #include serial@10032000 { diff --git a/dts/Bindings/serial/samsung_uart.yaml b/dts/Bindings/serial/samsung_uart.yaml index f064e5b76c..2940afb874 100644 --- a/dts/Bindings/serial/samsung_uart.yaml +++ b/dts/Bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 diff --git a/dts/Bindings/serial/sprd-uart.yaml b/dts/Bindings/serial/sprd-uart.yaml index 09f6283f3c..a444bebd2c 100644 --- a/dts/Bindings/serial/sprd-uart.yaml +++ b/dts/Bindings/serial/sprd-uart.yaml @@ -19,6 +19,7 @@ properties: - enum: - sprd,sc9860-uart - sprd,sc9863a-uart + - sprd,ums512-uart - const: sprd,sc9836-uart - const: sprd,sc9836-uart diff --git a/dts/Bindings/serial/st,stm32-uart.yaml b/dts/Bindings/serial/st,stm32-uart.yaml index f50f4ca893..333dc42722 100644 --- a/dts/Bindings/serial/st,stm32-uart.yaml +++ b/dts/Bindings/serial/st,stm32-uart.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# maintainers: - - Erwan Le Ray + - Erwan Le Ray title: STMicroelectronics STM32 USART bindings diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.txt b/dts/Bindings/serial/xlnx,opb-uartlite.txt deleted file mode 100644 index c37deb44de..0000000000 --- a/dts/Bindings/serial/xlnx,opb-uartlite.txt +++ /dev/null @@ -1,23 +0,0 @@ -Xilinx Axi Uartlite controller Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Can be either of - "xlnx,xps-uartlite-1.00.a" - "xlnx,opb-uartlite-1.00.b" -- reg : Physical base address and size of the Axi Uartlite - registers map. -- interrupts : Should contain the UART controller interrupt. - -Optional properties: -- port-number : Set Uart port number -- clock-names : Should be "s_axi_aclk" -- clocks : Input clock specifier. Refer to common clock bindings. - -Example: -serial@800c0000 { - compatible = "xlnx,xps-uartlite-1.00.a"; - reg = <0x0 0x800c0000 0x10000>; - interrupts = <0x0 0x6e 0x1>; - port-number = <0>; -}; diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.yaml b/dts/Bindings/serial/xlnx,opb-uartlite.yaml new file mode 100644 index 0000000000..f7617b88c7 --- /dev/null +++ b/dts/Bindings/serial/xlnx,opb-uartlite.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Axi Uartlite + +maintainers: + - Peter Korsgaard + +properties: + compatible: + contains: + enum: + - xlnx,xps-uartlite-1.00.a + - xlnx,opb-uartlite-1.00.b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set Uart port number + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The fixed baud rate that the device was configured for. + + xlnx,data-bits: + enum: [5, 6, 7, 8] + description: + The fixed number of data bits that the device was configured for. + + xlnx,use-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Whether parity checking was enabled when the device was configured. + + xlnx,odd-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Whether odd parity was configured. + +required: + - compatible + - reg + - interrupts + - current-speed + - xlnx,data-bits + - xlnx,use-parity + +allOf: + - $ref: /schemas/serial.yaml# + - if: + properties: + xlnx,use-parity: + contains: + const: 1 + then: + required: + - xlnx,odd-parity + +unevaluatedProperties: false + +examples: + - | + serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; + }; +... diff --git a/dts/Bindings/soc/aspeed/uart-routing.yaml b/dts/Bindings/soc/aspeed/uart-routing.yaml new file mode 100644 index 0000000000..6876407124 --- /dev/null +++ b/dts/Bindings/soc/aspeed/uart-routing.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2018 Google LLC +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Aspeed UART Routing Controller + +maintainers: + - Oskar Senft + - Chia-Wei Wang + +description: + The Aspeed UART routing control allow to dynamically route the inputs for + the built-in UARTS and physical serial I/O ports. + + This allows, for example, to connect the output of UART to another UART. + This can be used to enable Host <-> BMC communication via UARTs, e.g. to + allow access to the Host's serial console. + + This driver is for the BMC side. The sysfs files allow the BMC userspace + which owns the system configuration policy, to configure how UARTs and + physical serial I/O ports are routed. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-uart-routing + - aspeed,ast2500-uart-routing + - aspeed,ast2600-uart-routing + reg: + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + }; + }; diff --git a/dts/Bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml new file mode 100644 index 0000000000..ecd86cfb3d --- /dev/null +++ b/dts/Bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display and MIPI CSI + peripherals located in the DISP domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-disp-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 5 + maxItems: 5 + + power-domain-names: + items: + - const: bus + - const: csi-bridge + - const: lcdif + - const: mipi-dsi + - const: mipi-csi + + clocks: + minItems: 10 + maxItems: 10 + + clock-names: + items: + - const: csi-bridge-axi + - const: csi-bridge-apb + - const: csi-bridge-core + - const: lcdif-axi + - const: lcdif-apb + - const: lcdif-pix + - const: dsi-pclk + - const: dsi-ref + - const: csi-aclk + - const: csi-pclk + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + disp_blk_ctl: blk_ctrl@32e28000 { + compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_mipi>, <&pgc_mipi>; + power-domain-names = "bus", "csi-bridge", "lcdif", + "mipi-dsi", "mipi-csi"; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>, + <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core", + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", + "dsi-ref", "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; diff --git a/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml new file mode 100644 index 0000000000..26487daa64 --- /dev/null +++ b/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MM VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mm-vpu-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 4 + maxItems: 4 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: h1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: g1 + - const: g2 + - const: h1 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; diff --git a/dts/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/Bindings/soc/qcom/qcom,aoss-qmp.yaml index 93e4b737ee..e2e173dfad 100644 --- a/dts/Bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/dts/Bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -19,8 +19,7 @@ description: The AOSS side channel exposes control over a set of resources, used to control a set of debug related clocks and to affect the low power state of resources - related to the secondary subsystems. These resources are exposed as a set of - power-domains. + related to the secondary subsystems. properties: compatible: @@ -30,6 +29,7 @@ properties: - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp - qcom,sdm845-aoss-qmp + - qcom,sm6350-aoss-qmp - qcom,sm8150-aoss-qmp - qcom,sm8250-aoss-qmp - qcom,sm8350-aoss-qmp @@ -57,13 +57,6 @@ properties: description: The single clock represents the QDSS clock. - "#power-domain-cells": - const: 1 - description: | - The provided power-domains are: - CDSP state (0), LPASS state (1), modem state (2), SLPI - state (3), SPSS state (4) and Venus state (5). - required: - compatible - reg @@ -101,7 +94,6 @@ examples: mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; cx_cdev: cx { #cooling-cells = <2>; diff --git a/dts/Bindings/soc/qcom/qcom,apr.txt b/dts/Bindings/soc/qcom/qcom,apr.txt deleted file mode 100644 index 2e2f6dc351..0000000000 --- a/dts/Bindings/soc/qcom/qcom,apr.txt +++ /dev/null @@ -1,134 +0,0 @@ -Qualcomm APR (Asynchronous Packet Router) binding - -This binding describes the Qualcomm APR. APR is a IPC protocol for -communication between Application processor and QDSP. APR is mainly -used for audio/voice services on the QDSP. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apr-v", example "qcom,apr-v2" - -- qcom,apr-domain - Usage: required - Value type: - Definition: Destination processor ID. - Possible values are : - 1 - APR simulator - 2 - PC - 3 - MODEM - 4 - ADSP - 5 - APPS - 6 - MODEM2 - 7 - APPS2 - -= APR SERVICES -Each subnode of the APR node represents service tied to this apr. The name -of the nodes are not important. The properties of these nodes are defined -by the individual bindings for the specific service -- All APR services MUST contain the following property: - -- reg - Usage: required - Value type: - Definition: APR Service ID - Possible values are : - 3 - DSP Core Service - 4 - Audio Front End Service. - 5 - Voice Stream Manager Service. - 6 - Voice processing manager. - 7 - Audio Stream Manager Service. - 8 - Audio Device Manager Service. - 9 - Multimode voice manager. - 10 - Core voice stream. - 11 - Core voice processor. - 12 - Ultrasound stream manager. - 13 - Listen stream manager. - -- qcom,protection-domain - Usage: optional - Value type: - Definition: Must list the protection domain service name and path - that the particular apr service has a dependency on. - Possible values are : - "avs/audio", "msm/adsp/audio_pd". - "kernel/elf_loader", "msm/modem/wlan_pd". - "tms/servreg", "msm/adsp/audio_pd". - "tms/servreg", "msm/modem/wlan_pd". - "tms/servreg", "msm/slpi/sensor_pd". - -= EXAMPLE -The following example represents a QDSP based sound card on a MSM8996 device -which uses apr as communication between Apps and QDSP. - - apr { - compatible = "qcom,apr-v2"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - - dais { - #sound-dai-cells = <1>; - dai@1 { - reg = ; - }; - }; - }; - - apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - ... - }; - - apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - ... - }; - }; - -= EXAMPLE 2 -The following example represents a QDSP based sound card with protection domain -dependencies specified. Here some of the apr services are dependent on services -running on protection domain hosted on ADSP/SLPI remote processors while others -have no such dependency. - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - q6afe: apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - - q6asm: apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd"; - ... - }; - - q6adm: apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - }; diff --git a/dts/Bindings/soc/qcom/qcom,apr.yaml b/dts/Bindings/soc/qcom/qcom,apr.yaml new file mode 100644 index 0000000000..028c5d105a --- /dev/null +++ b/dts/Bindings/soc/qcom/qcom,apr.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for + communication between Application processor and QDSP. APR/GPR is mainly + used for audio/voice services on the QDSP. + +properties: + compatible: + enum: + - qcom,apr-v2 + - qcom,gpr + + qcom,apr-domain: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6, 7] + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain + deprecated: true + + qcom,domain: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 7 + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain + Selects the processor domain for gpr + 1 = Modem Domain + 2 = Audio DSP Domain + 3 = Application Processor Domain + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#APR/GPR Services +patternProperties: + "^service@[1-9a-d]$": + type: object + description: + APR/GPR node's client devices use subnodes for desired static port services. + + properties: + compatible: + enum: + - qcom,q6core + - qcom,q6asm + - qcom,q6afe + - qcom,q6adm + - qcom,q6apm + - qcom,q6prm + + reg: + minimum: 1 + maximum: 13 + description: + APR Service ID + 3 = DSP Core Service + 4 = Audio Front End Service. + 5 = Voice Stream Manager Service. + 6 = Voice processing manager. + 7 = Audio Stream Manager Service. + 8 = Audio Device Manager Service. + 9 = Multimode voice manager. + 10 = Core voice stream. + 11 = Core voice processor. + 12 = Ultrasound stream manager. + 13 = Listen stream manager. + GPR Service ID + 1 = Audio Process Manager Service + 2 = Proxy Resource Manager Service. + 3 = AMDB Service. + 4 = Voice processing manager. + + qcom,protection-domain: + $ref: /schemas/types.yaml#/definitions/string-array + description: protection domain service name and path for apr service + possible values are + "avs/audio", "msm/adsp/audio_pd". + "kernel/elf_loader", "msm/modem/wlan_pd". + "tms/servreg", "msm/adsp/audio_pd". + "tms/servreg", "msm/modem/wlan_pd". + "tms/servreg", "msm/slpi/sensor_pd". + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^.*@[0-9a-f]+$": + type: object + description: + Service based devices like clock controllers or digital audio interfaces. + + additionalProperties: false + +required: + - compatible + - qcom,domain + +additionalProperties: false + +examples: + - | + #include + apr { + compatible = "qcom,apr-v2"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core: service@3 { + compatible = "qcom,q6core"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; + + - | + #include + gpr { + compatible = "qcom,gpr"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@1 { + compatible = "qcom,q6apm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; diff --git a/dts/Bindings/soc/qcom/qcom,smd-rpm.yaml b/dts/Bindings/soc/qcom/qcom,smd-rpm.yaml index cc3fe5ed74..b32457c2fc 100644 --- a/dts/Bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/dts/Bindings/soc/qcom/qcom,smd-rpm.yaml @@ -34,6 +34,7 @@ properties: - qcom,rpm-ipq6018 - qcom,rpm-msm8226 - qcom,rpm-msm8916 + - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8996 @@ -41,6 +42,7 @@ properties: - qcom,rpm-sdm660 - qcom,rpm-sm6115 - qcom,rpm-sm6125 + - qcom,rpm-qcm2290 - qcom,rpm-qcs404 qcom,smd-channels: @@ -57,6 +59,7 @@ if: - qcom,rpm-apq8084 - qcom,rpm-msm8916 - qcom,rpm-msm8974 + - qcom,rpm-msm8953 then: required: - qcom,smd-channels diff --git a/dts/Bindings/soc/qcom/qcom,smem.yaml b/dts/Bindings/soc/qcom/qcom,smem.yaml index f7e17713b3..4149cf2b66 100644 --- a/dts/Bindings/soc/qcom/qcom,smem.yaml +++ b/dts/Bindings/soc/qcom/qcom,smem.yaml @@ -10,14 +10,18 @@ maintainers: - Andy Gross - Bjorn Andersson -description: | - This binding describes the Qualcomm Shared Memory Manager, used to share data - between various subsystems and OSes in Qualcomm platforms. +description: + This binding describes the Qualcomm Shared Memory Manager, a region of + reserved-memory used to share data between various subsystems and OSes in + Qualcomm platforms. properties: compatible: const: qcom,smem + reg: + maxItems: 1 + memory-region: maxItems: 1 description: handle to memory reservation for main SMEM memory region. @@ -29,11 +33,19 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: handle to RPM message memory resource + no-map: true + required: - compatible - - memory-region - hwlocks +oneOf: + - required: + - reg + - no-map + - required: + - memory-region + additionalProperties: false examples: @@ -43,6 +55,20 @@ examples: #size-cells = <1>; ranges; + smem@fa00000 { + compatible = "qcom,smem"; + reg = <0xfa00000 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + }; + - | + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + smem_region: smem@fa00000 { reg = <0xfa00000 0x200000>; no-map; diff --git a/dts/Bindings/soc/qcom/qcom,spm.yaml b/dts/Bindings/soc/qcom/qcom,spm.yaml new file mode 100644 index 0000000000..07d2d53983 --- /dev/null +++ b/dts/Bindings/soc/qcom/qcom,spm.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Subsystem Power Manager binding + +maintainers: + - Andy Gross + - Bjorn Andersson + +description: | + This binding describes the Qualcomm Subsystem Power Manager, used to control + the peripheral logic surrounding the application cores in Qualcomm platforms. + +properties: + compatible: + items: + - enum: + - qcom,sdm660-gold-saw2-v4.1-l2 + - qcom,sdm660-silver-saw2-v4.1-l2 + - qcom,msm8998-gold-saw2-v4.1-l2 + - qcom,msm8998-silver-saw2-v4.1-l2 + - qcom,msm8916-saw2-v3.0-cpu + - qcom,msm8226-saw2-v2.1-cpu + - qcom,msm8974-saw2-v2.1-cpu + - qcom,apq8084-saw2-v2.1-cpu + - qcom,apq8064-saw2-v1.1-cpu + - const: qcom,saw2 + + reg: + description: Base address and size of the SPM register region + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,kryo"; + device_type = "cpu"; + enable-method = "qcom,kpss-acc-v2"; + qcom,saw = <&saw0>; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + saw0: power-manager@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>; + }; + + - | + + /* + * Example 2: New-gen multi cluster SoC using SAW only for L2; + * This does not require any cpuidle driver, nor any cpu phandle. + */ + power-manager@17812000 { + compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2"; + reg = <0x17812000 0x1000>; + }; + + power-manager@17912000 { + compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2"; + reg = <0x17912000 0x1000>; + }; + +... diff --git a/dts/Bindings/soc/qcom/qcom-stats.yaml b/dts/Bindings/soc/qcom/qcom-stats.yaml new file mode 100644 index 0000000000..99dff7d73b --- /dev/null +++ b/dts/Bindings/soc/qcom/qcom-stats.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) Stats bindings + +maintainers: + - Maulik Shah + +description: + Always On Processor/Resource Power Manager maintains statistics of the SoC + sleep modes involving powering down of the rails and oscillator clock. + + Statistics includes SoC sleep mode type, number of times low power mode were + entered, time of last entry, time of last exit and accumulated sleep duration. + +properties: + compatible: + enum: + - qcom,rpmh-stats + - qcom,rpm-stats + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Example of rpmh sleep stats + - | + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0c3f0000 0x400>; + }; + # Example of rpm sleep stats + - | + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x04690000 0x10000>; + }; +... diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml index 39b66e9ce3..7d48ea094c 100644 --- a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -20,6 +20,9 @@ properties: - const: allwinner,sun6i-a31-i2s - const: allwinner,sun8i-a83t-i2s - const: allwinner,sun8i-h3-i2s + - items: + - const: allwinner,sun8i-r40-i2s + - const: allwinner,sun8i-h3-i2s - items: - const: allwinner,sun8i-v3-i2s - const: allwinner,sun8i-h3-i2s diff --git a/dts/Bindings/sound/amlogic,t9015.yaml b/dts/Bindings/sound/amlogic,t9015.yaml index c7613ea728..db7b04da0b 100644 --- a/dts/Bindings/sound/amlogic,t9015.yaml +++ b/dts/Bindings/sound/amlogic,t9015.yaml @@ -34,6 +34,10 @@ properties: resets: maxItems: 1 + AVDD-supply: + description: + Analogue power supply. + required: - "#sound-dai-cells" - compatible @@ -41,6 +45,7 @@ required: - clocks - clock-names - resets + - AVDD-supply additionalProperties: false @@ -56,4 +61,5 @@ examples: clocks = <&clkc CLKID_AUDIO_CODEC>; clock-names = "pclk"; resets = <&reset RESET_AUDIO_CODEC>; + AVDD-supply = <&vddao_1v8>; }; diff --git a/dts/Bindings/sound/audio-graph-card2.yaml b/dts/Bindings/sound/audio-graph-card2.yaml new file mode 100644 index 0000000000..f7e94b1e0e --- /dev/null +++ b/dts/Bindings/sound/audio-graph-card2.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/audio-graph-card2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Graph Card2 Device Tree Bindings + +maintainers: + - Kuninori Morimoto + +properties: + compatible: + enum: + - audio-graph-card2 + links: + $ref: /schemas/types.yaml#/definitions/phandle-array + label: + maxItems: 1 + routing: + description: | + A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + multi: + description: Multi-CPU/Codec node + dpcm: + description: DPCM node + codec2codec: + description: Codec to Codec node + +required: + - compatible + - links + +additionalProperties: false + +examples: + - | + sound { + compatible = "audio-graph-card2"; + + links = <&cpu_port>; + }; + + cpu { + compatible = "cpu-driver"; + + cpu_port: port { cpu_ep: endpoint { remote-endpoint = <&codec_ep>; }; }; + }; + + codec { + compatible = "codec-driver"; + + port { codec_ep: endpoint { remote-endpoint = <&cpu_ep>; }; }; + }; diff --git a/dts/Bindings/sound/bt-sco.txt b/dts/Bindings/sound/bt-sco.txt deleted file mode 100644 index 641edf75e1..0000000000 --- a/dts/Bindings/sound/bt-sco.txt +++ /dev/null @@ -1,13 +0,0 @@ -Bluetooth-SCO audio CODEC - -This device support generic Bluetooth SCO link. - -Required properties: - - - compatible : "delta,dfbmcs320" or "linux,bt-sco" - -Example: - -codec: bt_sco { - compatible = "delta,dfbmcs320"; -}; diff --git a/dts/Bindings/sound/cirrus,cs35l41.yaml b/dts/Bindings/sound/cirrus,cs35l41.yaml new file mode 100644 index 0000000000..3235702ce4 --- /dev/null +++ b/dts/Bindings/sound/cirrus,cs35l41.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs35l41.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS35L41 Speaker Amplifier + +maintainers: + - david.rhodes@cirrus.com + +description: | + CS35L41 is a boosted mono Class D amplifier with DSP + speaker protection and equalization + +properties: + compatible: + enum: + - cirrus,cs35l40 + - cirrus,cs35l41 + + reg: + maxItems: 1 + + '#sound-dai-cells': + description: + The first cell indicating the audio interface. + const: 1 + + reset-gpios: + maxItems: 1 + + VA-supply: + description: voltage regulator phandle for the VA supply + + VP-supply: + description: voltage regulator phandle for the VP supply + + cirrus,boost-peak-milliamp: + description: + Boost-converter peak current limit in mA. + Configures the peak current by monitoring the current through the boost FET. + Range starts at 1600 mA and goes to a maximum of 4500 mA with increments + of 50 mA. See section 4.3.6 of the datasheet for details. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1600 + maximum: 4500 + default: 4500 + + cirrus,boost-ind-nanohenry: + description: + Boost inductor value, expressed in nH. Valid + values include 1000, 1200, 1500 and 2200. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1000 + maximum: 2200 + + cirrus,boost-cap-microfarad: + description: + Total equivalent boost capacitance on the VBST + and VAMP pins, derated at 11 volts DC. The value must be rounded to the + nearest integer and expressed in uF. + $ref: "/schemas/types.yaml#/definitions/uint32" + + cirrus,asp-sdout-hiz: + description: + Audio serial port SDOUT Hi-Z control. Sets the Hi-Z + configuration for SDOUT pin of amplifier. + 0 = Logic 0 during unused slots, and while all transmit channels disabled + 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled + 2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled + 3 = Hi-Z during unused slots and while all transmit channels disabled + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3 + default: 2 + + cirrus,gpio1-polarity-invert: + description: + Boolean which specifies whether the GPIO1 + level is inverted. If this property is not present the level is not inverted. + type: boolean + + cirrus,gpio1-output-enable: + description: + Boolean which specifies whether the GPIO1 pin + is configured as an output. If this property is not present the + pin will be configured as an input. + type: boolean + + cirrus,gpio1-src-select: + description: + Configures the function of the GPIO1 pin. + Note that the options are different from the GPIO2 pin + 0 = High Impedance (Default) + 1 = GPIO + 2 = Sync + 3 = MCLK input + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3 + + cirrus,gpio2-polarity-invert: + description: + Boolean which specifies whether the GPIO2 + level is inverted. If this property is not present the level is not inverted. + type: boolean + + cirrus,gpio2-output-enable: + description: + Boolean which specifies whether the GPIO2 pin + is configured as an output. If this property is not present the + pin will be configured as an input. + type: boolean + + cirrus,gpio2-src-select: + description: + Configures the function of the GPIO2 pin. + Note that the options are different from the GPIO1 pin. + 0 = High Impedance (Default) + 1 = GPIO + 2 = Open Drain INTB + 3 = MCLK input + 4 = Push-pull INTB (active low) + 5 = Push-pull INT (active high) + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 5 + +required: + - compatible + - reg + - "#sound-dai-cells" + - cirrus,boost-peak-milliamp + - cirrus,boost-ind-nanohenry + - cirrus,boost-cap-microfarad + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + cs35l41: cs35l41@2 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reg = <2>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&gpio 110 0>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + }; + }; diff --git a/dts/Bindings/sound/cirrus,cs42l51.yaml b/dts/Bindings/sound/cirrus,cs42l51.yaml index 0d87e2c86a..963a871e74 100644 --- a/dts/Bindings/sound/cirrus,cs42l51.yaml +++ b/dts/Bindings/sound/cirrus,cs42l51.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CS42L51 audio codec DT bindings maintainers: - - Olivier Moysan + - Olivier Moysan properties: compatible: diff --git a/dts/Bindings/sound/cs42l42.txt b/dts/Bindings/sound/cs42l42.txt index 5d416fdaf0..3b77056239 100644 --- a/dts/Bindings/sound/cs42l42.txt +++ b/dts/Bindings/sound/cs42l42.txt @@ -19,13 +19,14 @@ Optional properties: (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for further information relating to interrupt properties) - - cirrus,ts-inv : Boolean property. For jacks that invert the tip sense - polarity. Normal jacks will short tip sense pin to HS1 when headphones are - plugged in and leave tip sense floating when not plugged in. Inverting jacks - short tip sense when unplugged and float when plugged in. + - cirrus,ts-inv : Boolean property. Sets the behaviour of the jack plug + detect switch. - 0 = (Default) Non-inverted - 1 = Inverted + 0 = (Default) Shorted to tip when unplugged, open when plugged. + This is "inverted tip sense (ITS)" in the datasheet. + + 1 = Open when unplugged, shorted to tip when plugged. + This is "normal tip sense (TS)" in the datasheet. - cirrus,ts-dbnc-rise : Debounce the rising edge of TIP_SENSE_PLUG. With no debounce, the tip sense pin might be noisy on a plug event. diff --git a/dts/Bindings/sound/ingenic,aic.yaml b/dts/Bindings/sound/ingenic,aic.yaml index cdc0fdaab3..d607325f2f 100644 --- a/dts/Bindings/sound/ingenic,aic.yaml +++ b/dts/Bindings/sound/ingenic,aic.yaml @@ -71,7 +71,7 @@ required: examples: - | - #include + #include aic: audio-controller@10020000 { compatible = "ingenic,jz4740-i2s"; reg = <0x10020000 0x38>; diff --git a/dts/Bindings/sound/ingenic,codec.yaml b/dts/Bindings/sound/ingenic,codec.yaml index 97d5f3819b..48aae54dd6 100644 --- a/dts/Bindings/sound/ingenic,codec.yaml +++ b/dts/Bindings/sound/ingenic,codec.yaml @@ -48,7 +48,7 @@ required: examples: - | - #include + #include codec: audio-codec@10020080 { compatible = "ingenic,jz4740-codec"; reg = <0x10020080 0x8>; diff --git a/dts/Bindings/sound/linux,bt-sco.yaml b/dts/Bindings/sound/linux,bt-sco.yaml new file mode 100644 index 0000000000..e3a1f485f6 --- /dev/null +++ b/dts/Bindings/sound/linux,bt-sco.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/linux,bt-sco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bluetooth SCO Audio Codec Device Tree Bindings + +maintainers: + - Mark Brown + +properties: + '#sound-dai-cells': + enum: + - 0 + + # For Wideband PCM + - 1 + + compatible: + enum: + - delta,dfbmcs320 + - linux,bt-sco + +required: + - '#sound-dai-cells' + - compatible + +additionalProperties: false + +examples: + - | + codec { + #sound-dai-cells = <0>; + compatible = "linux,bt-sco"; + }; + +... diff --git a/dts/Bindings/sound/linux,spdif-dit.yaml b/dts/Bindings/sound/linux,spdif-dit.yaml new file mode 100644 index 0000000000..c6b070e1d0 --- /dev/null +++ b/dts/Bindings/sound/linux,spdif-dit.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/linux,spdif-dit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dummy SPDIF Transmitter Device Tree Bindings + +maintainers: + - Mark Brown + +properties: + compatible: + const: linux,spdif-dit + + "#sound-dai-cells": + const: 0 + +required: + - "#sound-dai-cells" + - compatible + +additionalProperties: false + +examples: + - | + spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + +... diff --git a/dts/Bindings/sound/max9892x.txt b/dts/Bindings/sound/max9892x.txt index f6171591dd..98cb9ba5b3 100644 --- a/dts/Bindings/sound/max9892x.txt +++ b/dts/Bindings/sound/max9892x.txt @@ -30,6 +30,9 @@ Required properties: - reg : the I2C address of the device for I2C +Optional properties: + - reset-gpios : GPIO to reset the device + Example: codec: max98927@3a { diff --git a/dts/Bindings/sound/maxim,max98520.yaml b/dts/Bindings/sound/maxim,max98520.yaml new file mode 100644 index 0000000000..b6509cb2c8 --- /dev/null +++ b/dts/Bindings/sound/maxim,max98520.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/maxim,max98520.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX98520 Speaker Amplifier Driver + +maintainers: + - George Song + +properties: + compatible: + const: maxim,max98520 + + reg: + maxItems: 1 + description: I2C address of the device. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + max98520: amplifier@38 { + compatible = "maxim,max98520"; + reg = <0x38>; + }; + }; + diff --git a/dts/Bindings/sound/mt8192-afe-pcm.yaml b/dts/Bindings/sound/mt8192-afe-pcm.yaml new file mode 100644 index 0000000000..7a25bc9b80 --- /dev/null +++ b/dts/Bindings/sound/mt8192-afe-pcm.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek AFE PCM controller for mt8192 + +maintainers: + - Jiaxin Yu + - Shane Chien + +properties: + compatible: + const: mediatek,mt8192-audio + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + mediatek,apmixedsys: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek apmixedsys controller + + mediatek,infracfg: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek infracfg controller + + mediatek,topckgen: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: AFE clock + - description: ADDA DAC clock + - description: ADDA DAC pre-distortion clock + - description: audio infra sys clock + - description: audio infra 26M clock + + clock-names: + items: + - const: aud_afe_clk + - const: aud_dac_clk + - const: aud_dac_predis_clk + - const: aud_infra_clk + - const: aud_infra_26m_clk + +required: + - compatible + - interrupts + - resets + - reset-names + - mediatek,apmixedsys + - mediatek,infracfg + - mediatek,topckgen + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = ; + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg>; + mediatek,topckgen = <&topckgen>; + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_infra_clk", + "aud_infra_26m_clk"; + }; + +... diff --git a/dts/Bindings/sound/mt8195-mt6359-rt1011-rt5682.yaml b/dts/Bindings/sound/mt8195-mt6359-rt1011-rt5682.yaml new file mode 100644 index 0000000000..d354c30d33 --- /dev/null +++ b/dts/Bindings/sound/mt8195-mt6359-rt1011-rt5682.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8195-mt6359-rt1011-rt5682.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8195 with MT6359, RT1011 and RT5682 ASoC sound card driver + +maintainers: + - Trevor Wu + +description: + This binding describes the MT8195 sound card with RT1011 and RT5682. + +properties: + compatible: + const: mediatek,mt8195_mt6359_rt1011_rt5682 + + mediatek,platform: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of MT8195 ASoC platform. + + mediatek,dptx-codec: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of MT8195 Display Port Tx codec node. + + mediatek,hdmi-codec: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of MT8195 HDMI codec node. + +additionalProperties: false + +required: + - compatible + - mediatek,platform + +examples: + - | + + sound: mt8195-sound { + compatible = "mediatek,mt8195_mt6359_rt1011_rt5682"; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + }; + +... diff --git a/dts/Bindings/sound/name-prefix.txt b/dts/Bindings/sound/name-prefix.txt deleted file mode 100644 index 6457759086..0000000000 --- a/dts/Bindings/sound/name-prefix.txt +++ /dev/null @@ -1,24 +0,0 @@ -Name prefix: - -Card implementing the routing property define the connection between -audio components as list of string pair. Component using the same -sink/source names may use the name prefix property to prepend the -name of their sinks/sources with the provided string. - -Optional name prefix property: -- sound-name-prefix : string using as prefix for the sink/source names of - the component. - -Example: Two instances of the same component. - -amp0: analog-amplifier@0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio GPIOH_3 0>; - sound-name-prefix = "FRONT"; -}; - -amp1: analog-amplifier@1 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio GPIOH_4 0>; - sound-name-prefix = "BACK"; -}; diff --git a/dts/Bindings/sound/name-prefix.yaml b/dts/Bindings/sound/name-prefix.yaml new file mode 100644 index 0000000000..2fe57f87ac --- /dev/null +++ b/dts/Bindings/sound/name-prefix.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/name-prefix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Component sound name prefix + +maintainers: + - Jerome Brunet + +properties: + sound-name-prefix: + $ref: /schemas/types.yaml#/definitions/string + description: | + Card implementing the routing property define the connection between + audio components as list of string pair. Component using the same + sink/source names may use this property to prepend the name of their + sinks/sources with the provided string. + +additionalProperties: true diff --git a/dts/Bindings/sound/nau8821.txt b/dts/Bindings/sound/nau8821.txt new file mode 100644 index 0000000000..6c3baf7a5f --- /dev/null +++ b/dts/Bindings/sound/nau8821.txt @@ -0,0 +1,55 @@ +Nuvoton NAU88L21 audio codec + +This device supports I2C only. + +Required properties: + - compatible : Must be "nuvoton,nau8821" + + - reg : the I2C address of the device. This is either 0x1B (CSB=0) or 0x54 (CSB=1). + +Optional properties: + - nuvoton,jkdet-enable: Enable jack detection via JKDET pin. + - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled, + otherwise pin in high impedance state. + - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down. + - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low. + + - nuvoton,vref-impedance: VREF Impedance selection + 0 - Open + 1 - 25 kOhm + 2 - 125 kOhm + 3 - 2.5 kOhm + + - nuvoton,micbias-voltage: Micbias voltage level. + 0 - VDDA + 1 - VDDA + 2 - VDDA * 1.1 + 3 - VDDA * 1.2 + 4 - VDDA * 1.3 + 5 - VDDA * 1.4 + 6 - VDDA * 1.53 + 7 - VDDA * 1.53 + + - nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms + - nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms + + - nuvoton,dmic-clk-threshold: the ADC threshold of DMIC clock. + + +Example: + + headset: nau8821@1b { + compatible = "nuvoton,nau8821"; + reg = <0x1b>; + interrupt-parent = <&gpio>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + nuvoton,jkdet-enable; + nuvoton,jkdet-pull-enable; + nuvoton,jkdet-pull-up; + nuvoton,jkdet-polarity = ; + nuvoton,vref-impedance = <2>; + nuvoton,micbias-voltage = <6>; + nuvoton,jack-insert-debounce = <7>; + nuvoton,jack-eject-debounce = <7>; + nuvoton,dmic-clk-threshold = 3072000; + }; diff --git a/dts/Bindings/sound/nvidia,tegra186-dspk.yaml b/dts/Bindings/sound/nvidia,tegra186-dspk.yaml index 5f6b37c251..0912d3e3fd 100644 --- a/dts/Bindings/sound/nvidia,tegra186-dspk.yaml +++ b/dts/Bindings/sound/nvidia,tegra186-dspk.yaml @@ -17,6 +17,9 @@ maintainers: - Jon Hunter - Sameer Pujar +allOf: + - $ref: name-prefix.yaml# + properties: $nodename: pattern: "^dspk@[0-9a-f]*$" @@ -48,12 +51,6 @@ properties: sound-name-prefix: pattern: "^DSPK[1-9]$" - $ref: /schemas/types.yaml#/definitions/string - description: - Used as prefix for sink/source names of the component. Must be a - unique string among multiple instances of the same component. - The name can be "DSPK1" or "DSPKx", where x depends on the maximum - available instances on a Tegra SoC. ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/sound/nvidia,tegra210-adx.yaml b/dts/Bindings/sound/nvidia,tegra210-adx.yaml new file mode 100644 index 0000000000..c4ba12ea36 --- /dev/null +++ b/dts/Bindings/sound/nvidia,tegra210-adx.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra210-adx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra210 ADX Device Tree Bindings + +description: | + The Audio Demultiplexer (ADX) block takes an input stream with up to + 16 channels and demultiplexes it into four output streams of up to 16 + channels each. A byte RAM helps to form output frames by any combination + of bytes from the input frame. Its design is identical to that of byte + RAM in the AMX except that the data flow direction is reversed. + +maintainers: + - Jon Hunter + - Mohan Kumar + - Sameer Pujar + +allOf: + - $ref: name-prefix.yaml# + +properties: + $nodename: + pattern: "^adx@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra210-adx + - items: + - enum: + - nvidia,tegra194-adx + - nvidia,tegra186-adx + - const: nvidia,tegra210-adx + + reg: + maxItems: 1 + + sound-name-prefix: + pattern: "^ADX[1-9]$" + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + ADX has one input and four outputs. Accordingly ACIF (Audio Client + Interface) port nodes are defined to represent ADX input (port 0) + and outputs (ports 1 to 4). These are connected to corresponding + ports on AHUB (Audio Hub). + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: ADX ACIF input port + patternProperties: + '^port@[1-4]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: ADX ACIF output ports + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + adx@702d3800 { + compatible = "nvidia,tegra210-adx"; + reg = <0x702d3800 0x100>; + sound-name-prefix = "ADX1"; + }; + +... diff --git a/dts/Bindings/sound/nvidia,tegra210-ahub.yaml b/dts/Bindings/sound/nvidia,tegra210-ahub.yaml index 1118a94883..df81d20818 100644 --- a/dts/Bindings/sound/nvidia,tegra210-ahub.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-ahub.yaml @@ -85,6 +85,26 @@ patternProperties: type: object $ref: nvidia,tegra186-dspk.yaml# + '^mvc@[0-9a-f]+$': + type: object + $ref: nvidia,tegra210-mvc.yaml# + + '^sfc@[0-9a-f]+$': + type: object + $ref: nvidia,tegra210-sfc.yaml# + + '^amx@[0-9a-f]+$': + type: object + $ref: nvidia,tegra210-amx.yaml# + + '^adx@[0-9a-f]+$': + type: object + $ref: nvidia,tegra210-adx.yaml# + + '^amixer@[0-9a-f]+$': + type: object + $ref: nvidia,tegra210-mixer.yaml# + required: - compatible - reg diff --git a/dts/Bindings/sound/nvidia,tegra210-amx.yaml b/dts/Bindings/sound/nvidia,tegra210-amx.yaml new file mode 100644 index 0000000000..bb2111afe5 --- /dev/null +++ b/dts/Bindings/sound/nvidia,tegra210-amx.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra210-amx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra210 AMX Device Tree Bindings + +description: | + The Audio Multiplexer (AMX) block can multiplex up to four input streams + each of which can have maximum 16 channels and generate an output stream + with maximum 16 channels. A byte RAM helps to form an output frame by + any combination of bytes from the input frames. + +maintainers: + - Jon Hunter + - Mohan Kumar + - Sameer Pujar + +allOf: + - $ref: name-prefix.yaml# + +properties: + $nodename: + pattern: "^amx@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra210-amx + - items: + - const: nvidia,tegra186-amx + - const: nvidia,tegra210-amx + - const: nvidia,tegra194-amx + + reg: + maxItems: 1 + + sound-name-prefix: + pattern: "^AMX[1-9]$" + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + AMX has four inputs and one output. Accordingly ACIF (Audio Client + Interfaces) port nodes are defined to represent AMX inputs (port 0 + to 3) and output (port 4). These are connected to corresponding + ports on AHUB (Audio Hub). + + patternProperties: + '^port@[0-3]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: AMX ACIF input ports + + properties: + port@4: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: AMX ACIF output port + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + amx@702d3000 { + compatible = "nvidia,tegra210-amx"; + reg = <0x702d3000 0x100>; + sound-name-prefix = "AMX1"; + }; + +... diff --git a/dts/Bindings/sound/nvidia,tegra210-dmic.yaml b/dts/Bindings/sound/nvidia,tegra210-dmic.yaml index fd275a5750..62db982bb0 100644 --- a/dts/Bindings/sound/nvidia,tegra210-dmic.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-dmic.yaml @@ -16,6 +16,9 @@ maintainers: - Jon Hunter - Sameer Pujar +allOf: + - $ref: name-prefix.yaml# + properties: $nodename: pattern: "^dmic@[0-9a-f]*$" @@ -49,12 +52,6 @@ properties: sound-name-prefix: pattern: "^DMIC[1-9]$" - $ref: /schemas/types.yaml#/definitions/string - description: - used as prefix for sink/source names of the component. Must be a - unique string among multiple instances of the same component. - The name can be "DMIC1" or "DMIC2" ... "DMICx", where x depends - on the maximum available instances on a Tegra SoC. ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/sound/nvidia,tegra210-i2s.yaml b/dts/Bindings/sound/nvidia,tegra210-i2s.yaml index 63370709c7..f954be6366 100644 --- a/dts/Bindings/sound/nvidia,tegra210-i2s.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-i2s.yaml @@ -16,6 +16,9 @@ maintainers: - Jon Hunter - Sameer Pujar +allOf: + - $ref: name-prefix.yaml# + properties: $nodename: pattern: "^i2s@[0-9a-f]*$" @@ -65,12 +68,6 @@ properties: sound-name-prefix: pattern: "^I2S[1-9]$" - $ref: /schemas/types.yaml#/definitions/string - description: - Used as prefix for sink/source names of the component. Must be a - unique string among multiple instances of the same component. - The name can be "I2S1" or "I2S2" ... "I2Sx", where x depends - on the maximum available instances on a Tegra SoC. ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/sound/nvidia,tegra210-mixer.yaml b/dts/Bindings/sound/nvidia,tegra210-mixer.yaml new file mode 100644 index 0000000000..428f3c8519 --- /dev/null +++ b/dts/Bindings/sound/nvidia,tegra210-mixer.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra210-mixer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra210 Mixer Device Tree Bindings + +description: | + The Mixer supports mixing of up to ten 7.1 audio input streams and + generate five outputs (each of which can be any combination of the + ten input streams). + +maintainers: + - Jon Hunter + - Mohan Kumar + - Sameer Pujar + +allOf: + - $ref: name-prefix.yaml# + +properties: + $nodename: + pattern: "^amixer@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra210-amixer + - items: + - enum: + - nvidia,tegra194-amixer + - nvidia,tegra186-amixer + - const: nvidia,tegra210-amixer + + reg: + maxItems: 1 + + sound-name-prefix: + pattern: "^MIXER[1-9]$" + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Mixer has ten inputs and five outputs. Accordingly ACIF (Audio + Client Interfaces) port nodes are defined to represent Mixer + inputs (port 0 to 9) and outputs (port 10 to 14). These are + connected to corresponding ports on AHUB (Audio Hub). + + patternProperties: + '^port@[0-9]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Mixer ACIF input ports + '^port@[10-14]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Mixer ACIF output ports + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + amixer@702dbb00 { + compatible = "nvidia,tegra210-amixer"; + reg = <0x702dbb00 0x800>; + sound-name-prefix = "MIXER1"; + }; + +... diff --git a/dts/Bindings/sound/nvidia,tegra210-mvc.yaml b/dts/Bindings/sound/nvidia,tegra210-mvc.yaml new file mode 100644 index 0000000000..e2f5a8591d --- /dev/null +++ b/dts/Bindings/sound/nvidia,tegra210-mvc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra210-mvc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra210 MVC Device Tree Bindings + +description: | + The Master Volume Control (MVC) provides gain or attenuation to a digital + signal path. It can be used in input or output signal path for per-stream + volume control or it can be used as master volume control. The MVC block + has one input and one output. The input digital stream can be mono or + multi-channel (up to 7.1 channels) stream. An independent mute control is + also included in the MVC block. + +maintainers: + - Jon Hunter + - Mohan Kumar + - Sameer Pujar + +allOf: + - $ref: name-prefix.yaml# + +properties: + $nodename: + pattern: "^mvc@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra210-mvc + - items: + - enum: + - nvidia,tegra194-mvc + - nvidia,tegra186-mvc + - const: nvidia,tegra210-mvc + + reg: + maxItems: 1 + + sound-name-prefix: + pattern: "^MVC[1-9]$" + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: | + MVC ACIF (Audio Client Interface) input port. This is connected + to corresponding ACIF output port on AHUB (Audio Hub). + + port@1: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: | + MVC ACIF output port. This is connected to corresponding ACIF + input port on AHUB. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + mvc@702da000 { + compatible = "nvidia,tegra210-mvc"; + reg = <0x702da000 0x200>; + sound-name-prefix = "MVC1"; + }; + +... diff --git a/dts/Bindings/sound/nvidia,tegra210-sfc.yaml b/dts/Bindings/sound/nvidia,tegra210-sfc.yaml new file mode 100644 index 0000000000..41ad651735 --- /dev/null +++ b/dts/Bindings/sound/nvidia,tegra210-sfc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nvidia,tegra210-sfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra210 SFC Device Tree Bindings + +description: | + The Sampling Frequency Converter (SFC) converts the sampling frequency + of the input signal from one frequency to another. It supports sampling + frequency conversions of streams of up to two channels (stereo). + +maintainers: + - Jon Hunter + - Mohan Kumar + - Sameer Pujar + +allOf: + - $ref: name-prefix.yaml# + +properties: + $nodename: + pattern: "^sfc@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra210-sfc + - items: + - enum: + - nvidia,tegra194-sfc + - nvidia,tegra186-sfc + - const: nvidia,tegra210-sfc + + reg: + maxItems: 1 + + sound-name-prefix: + pattern: "^SFC[1-9]$" + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: | + SFC ACIF (Audio Client Interface) input port. This is connected + to corresponding ACIF output port on AHUB (Audio Hub). + + port@1: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: | + SFC ACIF output port. This is connected to corresponding ACIF + input port on AHUB. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + + sfc@702d2000 { + compatible = "nvidia,tegra210-sfc"; + reg = <0x702d2000 0x200>; + sound-name-prefix = "SFC1"; + }; + +... diff --git a/dts/Bindings/sound/nxp,tfa989x.yaml b/dts/Bindings/sound/nxp,tfa989x.yaml index ffb8fcfeb6..7667471be1 100644 --- a/dts/Bindings/sound/nxp,tfa989x.yaml +++ b/dts/Bindings/sound/nxp,tfa989x.yaml @@ -9,6 +9,9 @@ title: NXP/Goodix TFA989X (TFA1) Audio Amplifiers maintainers: - Stephan Gerhold +allOf: + - $ref: name-prefix.yaml# + properties: compatible: enum: @@ -21,11 +24,7 @@ properties: '#sound-dai-cells': const: 0 - sound-name-prefix: - $ref: /schemas/types.yaml#/definitions/string - description: - Used as prefix for sink/source names of the component. Must be a - unique string among multiple instances of the same component. + sound-name-prefix: true vddd-supply: description: regulator phandle for the VDDD power supply. diff --git a/dts/Bindings/sound/qcom,lpass-rx-macro.yaml b/dts/Bindings/sound/qcom,lpass-rx-macro.yaml index 443d556caa..bc762b39c6 100644 --- a/dts/Bindings/sound/qcom,lpass-rx-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-rx-macro.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sm8250-lpass-rx-macro + enum: + - qcom,sc7280-lpass-rx-macro + - qcom,sm8250-lpass-rx-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-tx-macro.yaml b/dts/Bindings/sound/qcom,lpass-tx-macro.yaml index 6b5ca02ccc..74f53864e7 100644 --- a/dts/Bindings/sound/qcom,lpass-tx-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-tx-macro.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sm8250-lpass-tx-macro + enum: + - qcom,sc7280-lpass-tx-macro + - qcom,sm8250-lpass-tx-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-va-macro.yaml b/dts/Bindings/sound/qcom,lpass-va-macro.yaml index 679b49cbe3..99f2c3687f 100644 --- a/dts/Bindings/sound/qcom,lpass-va-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-va-macro.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sm8250-lpass-va-macro + enum: + - qcom,sc7280-lpass-va-macro + - qcom,sm8250-lpass-va-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml index 435b019a1e..13cdb8a106 100644 --- a/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sm8250-lpass-wsa-macro + enum: + - qcom,sc7280-lpass-wsa-macro + - qcom,sm8250-lpass-wsa-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,q6afe.txt b/dts/Bindings/sound/qcom,q6afe.txt index 2d6fb2ea75..bc6b5f1fe4 100644 --- a/dts/Bindings/sound/qcom,q6afe.txt +++ b/dts/Bindings/sound/qcom,q6afe.txt @@ -12,190 +12,9 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE DAIs (Digial Audio Interface) -"dais" subnode of the AFE node. It represents afe dais, each afe dai is a -subnode of "dais" representing board specific dai setup. -"dais" node should have following properties followed by dai children. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-dais" - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -- #address-cells - Usage: required - Value type: - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: - Definition: Must be 0 - -== AFE DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: - Definition: Must be dai id - -- qcom,sd-lines - Usage: required for mi2s interface - Value type: - Definition: Must be list of serial data lines used by this dai. - should be one or more of the 0-3 sd lines. - - - qcom,tdm-sync-mode: - Usage: required for tdm interface - Value type: - Definition: Synchronization mode. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,tdm-sync-src: - Usage: required for tdm interface - Value type: - Definition: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,tdm-data-out: - Usage: required for tdm interface - Value type: - Definition: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,tdm-invert-sync: - Usage: required for tdm interface - Value type: - Definition: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,tdm-data-delay: - Usage: required for tdm interface - Value type: - Definition: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - - qcom,tdm-data-align: - Usage: required for tdm interface - Value type: - Definition: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - -= AFE CLOCKSS -"clocks" subnode of the AFE node. It represents q6afe clocks -"clocks" node should have following properties. -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-clocks" - -- #clock-cells: - Usage: required - Value type: - Definition: Must be 2. Clock Id followed by - below valid clock coupling attributes. - 1 - for no coupled clock - 2 - for dividend of the coupled clock - 3 - for divisor of the coupled clock - 4 - for inverted and no couple clock - = EXAMPLE apr-service@4 { compatible = "qcom,q6afe"; reg = ; - - dais { - compatible = "qcom,q6afe-dais"; - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dai@1 { - reg = ; - }; - - dai@24 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay = <1>; - qcom,tdm-data-align = <0>; - - }; - - dai@25 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay <1>: - qcom,tdm-data-align = <0>; - }; - - dai@16 { - reg = ; - qcom,sd-lines = <0 2>; - }; - - dai@17 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@18 { - reg = ; - qcom,sd-lines = <0 3>; - }; - - dai@19 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@20 { - reg = ; - qcom,sd-lines = <1 3>; - }; - - dai@21 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@22 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@23 { - reg = ; - qcom,sd-lines = <1>; - }; - }; - - clocks { - compatible = "qcom,q6afe-clocks"; - #clock-cells = <2>; - }; }; diff --git a/dts/Bindings/sound/qcom,q6apm-dai.yaml b/dts/Bindings/sound/qcom,q6apm-dai.yaml new file mode 100644 index 0000000000..5d97278432 --- /dev/null +++ b/dts/Bindings/sound/qcom,q6apm-dai.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6apm-dai.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Audio Process Manager Digital Audio Interfaces binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APM DAIs in DSP + +properties: + compatible: + const: qcom,q6apm-dais + + reg: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - reg + +additionalProperties: false + +examples: + - | + #include + gpr { + compatible = "qcom,gpr"; + #address-cells = <1>; + #size-cells = <0>; + qcom,domain = ; + service@1 { + compatible = "qcom,q6apm"; + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + apm-dai@1 { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + reg = <1>; + }; + }; + }; diff --git a/dts/Bindings/sound/qcom,q6asm.txt b/dts/Bindings/sound/qcom,q6asm.txt index 8c4883beca..0d00751252 100644 --- a/dts/Bindings/sound/qcom,q6asm.txt +++ b/dts/Bindings/sound/qcom,q6asm.txt @@ -14,7 +14,7 @@ used by the apr service device. from DSP. example "qcom,q6asm-v2.0" -= ASM DAIs (Digial Audio Interface) += ASM DAIs (Digital Audio Interface) "dais" subnode of the ASM node represents dai specific configuration - compatible: diff --git a/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml new file mode 100644 index 0000000000..f83f00737a --- /dev/null +++ b/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-clocks.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS Clock Controller binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP Clock Controller + +properties: + compatible: + enum: + - qcom,q6afe-clocks + - qcom,q6prm-lpass-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 2 + description: + Clock Id is followed by clock coupling attributes. + 1 = for no coupled clock + 2 = for dividend of the coupled clock + 3 = for divisor of the coupled clock + 4 = for inverted and no couple clock + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clock-controller@2 { + compatible = "qcom,q6afe-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; + + - | + #include + gpr { + compatible = "qcom,gpr"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + service@2 { + reg = ; + compatible = "qcom,q6prm"; + #address-cells = <1>; + #size-cells = <0>; + clock-controller@2 { + compatible = "qcom,q6prm-lpass-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; diff --git a/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml b/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml new file mode 100644 index 0000000000..dc7fba7b92 --- /dev/null +++ b/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -0,0 +1,205 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP LPASS Audio ports + +properties: + compatible: + enum: + - qcom,q6afe-dais + - qcom,q6apm-lpass-dais + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#Digital Audio Interfaces +patternProperties: + '^dai@[0-9]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + description: + Digital Audio Interface ID + + qcom,sd-lines: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of serial data lines used by this dai.should be one or more of the 0-3 sd lines. + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + minimum: 0 + maximum: 3 + + qcom,tdm-sync-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Synchronization mode + 0 = Short sync bit mode + 1 = Long sync mode + 2 = Short sync slot mode + + qcom,tdm-sync-src: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Synchronization source + 0 = External source + 1 = Internal source + + qcom,tdm-data-out: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Data out signal to drive with other masters + 0 = Disable + 1 = Enable + + qcom,tdm-invert-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Invert the sync + 0 = Normal + 1 = Invert + + qcom,tdm-data-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Number of bit clock to delay data + 0 = 0 bit clock cycle + 1 = 1 bit clock cycle + 2 = 2 bit clock cycle + + qcom,tdm-data-align: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Indicate how data is packed within the slot. For example, 32 slot + width in case of sample bit width is 24TDM Invert the sync. + 0 = MSB + 1 = LSB + + required: + - reg + + allOf: + - if: + properties: + reg: + contains: + # TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7 + items: + minimum: 24 + maximum: 103 + then: + required: + - qcom,tdm-sync-mode + - qcom,tdm-sync-src + - qcom,tdm-data-out + - qcom,tdm-invert-sync + - qcom,tdm-data-delay + - qcom,tdm-data-align + + - if: + properties: + reg: + contains: + # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and + # QUINARY_MI2S_RX - QUINARY_MI2S_TX + items: + oneOf: + - minimum: 16 + maximum: 23 + - minimum: 127 + maximum: 128 + then: + required: + - qcom,sd-lines + + additionalProperties: false + +required: + - compatible + - reg + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afedai@1 { + compatible = "qcom,q6afe-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; + - | + #include + gpr { + compatible = "qcom,gpr"; + #address-cells = <1>; + #size-cells = <0>; + qcom,domain = ; + service@1 { + compatible = "qcom,q6apm"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6apmdai@1 { + compatible = "qcom,q6apm-lpass-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; diff --git a/dts/Bindings/sound/realtek,rt5682s.yaml b/dts/Bindings/sound/realtek,rt5682s.yaml new file mode 100644 index 0000000000..2b8b7b51fe --- /dev/null +++ b/dts/Bindings/sound/realtek,rt5682s.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,rt5682s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek rt5682s codec devicetree bindings + +maintainers: + - Derek Fang + +description: | + Rt5682s(ALC5682I-VS) is a rt5682i variant which supports I2C only. + +properties: + compatible: + const: realtek,rt5682s + + reg: + maxItems: 1 + description: I2C address of the device. + + interrupts: + description: The CODEC's interrupt output. + + realtek,dmic1-data-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # dmic1 data is not used + - 1 # using GPIO2 pin as dmic1 data pin + - 2 # using GPIO5 pin as dmic1 data pin + description: | + Specify which GPIO pin be used as DMIC1 data pin. + + realtek,dmic1-clk-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # dmic1 clk is not used + - 1 # using GPIO1 pin as dmic1 clock pin + - 2 # using GPIO3 pin as dmic1 clock pin + description: | + Specify which GPIO pin be used as DMIC1 clk pin. + + realtek,jd-src: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # No JD is used + - 1 # using JD1 as JD source + description: | + Specify which JD source be used. + + realtek,ldo1-en-gpios: + description: | + The GPIO that controls the CODEC's LDO1_EN pin. + + realtek,dmic-clk-rate-hz: + description: | + Set the clock rate (hz) for the requirement of the particular DMIC. + + realtek,dmic-delay-ms: + description: | + Set the delay time (ms) for the requirement of the particular DMIC. + + realtek,dmic-clk-driving-high: + type: boolean + description: | + Set the high driving of the DMIC clock out. + + clocks: + items: + - description: phandle and clock specifier for codec MCLK. + + clock-names: + items: + - const: mclk + + "#clock-cells": + const: 1 + + clock-output-names: + minItems: 2 + maxItems: 2 + description: Name given for DAI word clock and bit clock outputs. + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <1>; + realtek,jd-src = <1>; + + #clock-cells = <1>; + clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk"; + + clocks = <&osc>; + clock-names = "mclk"; + }; + }; diff --git a/dts/Bindings/sound/richtek,rt9120.yaml b/dts/Bindings/sound/richtek,rt9120.yaml new file mode 100644 index 0000000000..5655ca5682 --- /dev/null +++ b/dts/Bindings/sound/richtek,rt9120.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/richtek,rt9120.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9120 Class-D audio amplifier + +maintainers: + - ChiYuan Huang + +description: | + The RT9120 is a high efficiency, I2S-input, stereo audio power amplifier + delivering 2*20W into 8 Ohm BTL speaker loads. It supports the wide input + voltage range from 4.5V to 26.4V to meet the need on most common + applications like as TV, monitors. home entertainment, electronic music + equipment. + +properties: + compatible: + enum: + - richtek,rt9120 + + reg: + description: I2C device address + maxItems: 1 + + pwdnn-gpios: + description: GPIO used for power down, low active + maxItems: 1 + + dvdd-supply: + description: | + Supply for the default on DVDD power, voltage domain must be 3P3V or 1P8V + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - dvdd-supply + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + rt9120@1a { + compatible = "richtek,rt9120"; + reg = <0x1a>; + pwdnn-gpios = <&gpio26 2 0>; + dvdd-supply = <&vdd_io_reg>; + #sound-dai-cells = <0>; + }; + }; diff --git a/dts/Bindings/sound/rockchip,i2s-tdm.yaml b/dts/Bindings/sound/rockchip,i2s-tdm.yaml new file mode 100644 index 0000000000..6a7c004bef --- /dev/null +++ b/dts/Bindings/sound/rockchip,i2s-tdm.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip I2S/TDM Controller + +description: + The Rockchip I2S/TDM Controller is a Time Division Multiplexed + audio interface found in various Rockchip SoCs, allowing up + to 8 channels of audio over a serial interface. + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - rockchip,px30-i2s-tdm + - rockchip,rk1808-i2s-tdm + - rockchip,rk3308-i2s-tdm + - rockchip,rk3568-i2s-tdm + - rockchip,rv1126-i2s-tdm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + maxItems: 2 + items: + enum: + - rx + - tx + + clocks: + minItems: 3 + items: + - description: clock for TX + - description: clock for RX + - description: AHB clock driving the interface + - description: + Parent clock for mclk_tx (only required when using mclk-calibrate) + - description: + Parent clock for mclk_rx (only required when using mclk-calibrate) + - description: + Clock for sample rates that are an integer multiple of 8000 + (only required when using mclk-calibrate) + - description: + Clock for sample rates that are an integer multiple of 11025 + (only required when using mclk-calibrate) + + clock-names: + minItems: 3 + items: + - const: mclk_tx + - const: mclk_rx + - const: hclk + - const: mclk_tx_src + - const: mclk_rx_src + - const: mclk_root0 + - const: mclk_root1 + + resets: + minItems: 1 + maxItems: 2 + description: resets for the tx and rx directions + + reset-names: + minItems: 1 + maxItems: 2 + items: + enum: + - tx-m + - rx-m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF register. + + rockchip,trcm-sync-tx-only: + type: boolean + description: Use TX BCLK/LRCK for both TX and RX. + + rockchip,trcm-sync-rx-only: + type: boolean + description: Use RX BCLK/LRCK for both TX and RX. + + "#sound-dai-cells": + const: 0 + + rockchip,i2s-rx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of I2S RX sdis to I2S data bus lines. + By default, they are mapped one-to-one. + rockchip,i2s-rx-route = <3> would mean sdi3 is receiving from data0. + maxItems: 4 + items: + enum: [0, 1, 2, 3] + + rockchip,i2s-tx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of I2S TX sdos to I2S data bus lines. + By default, they are mapped one-to-one. + rockchip,i2s-tx-route = <3> would mean sdo3 is sending to data0. + maxItems: 4 + items: + enum: [0, 1, 2, 3] + + rockchip,io-multiplex: + description: + Specify that the GPIO lines on the I2S bus are multiplexed such that + the direction (input/output) needs to be dynamically adjusted. + type: boolean + + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + - resets + - reset-names + - rockchip,grf + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe410000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, + <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 3>, <&dmac1 2>; + dma-names = "rx", "tx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = + <&i2s1m0_sclktx + &i2s1m0_sclkrx + &i2s1m0_lrcktx + &i2s1m0_lrckrx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + }; + }; diff --git a/dts/Bindings/sound/rockchip,pdm.txt b/dts/Bindings/sound/rockchip,pdm.txt deleted file mode 100644 index 98572a2512..0000000000 --- a/dts/Bindings/sound/rockchip,pdm.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Rockchip PDM controller - -Required properties: - -- compatible: "rockchip,pdm" - - "rockchip,px30-pdm" - - "rockchip,rk1808-pdm" - - "rockchip,rk3308-pdm" -- reg: physical base address of the controller and length of memory mapped - region. -- dmas: DMA specifiers for rx dma. See the DMA client binding, - Documentation/devicetree/bindings/dma/dma.txt -- dma-names: should include "rx". -- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. -- clock-names: should contain following: - - "pdm_hclk": clock for PDM BUS - - "pdm_clk" : clock for PDM controller -- resets: a list of phandle + reset-specifer paris, one for each entry in reset-names. -- reset-names: reset names, should include "pdm-m". -- pinctrl-names: Must contain a "default" entry. -- pinctrl-N: One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. - -Example for rk3328 PDM controller: - -pdm: pdm@ff040000 { - compatible = "rockchip,pdm"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&clk_pdm>, <&clk_gates28 0>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&pdma 16>; - #dma-cells = <1>; - dma-names = "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-1 = <&pdmm0_clk_sleep - &pdmm0_sdi0_sleep - &pdmm0_sdi1_sleep - &pdmm0_sdi2_sleep - &pdmm0_sdi3_sleep>; -}; diff --git a/dts/Bindings/sound/rockchip,pdm.yaml b/dts/Bindings/sound/rockchip,pdm.yaml new file mode 100644 index 0000000000..22e1cf6c05 --- /dev/null +++ b/dts/Bindings/sound/rockchip,pdm.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,pdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PDM controller + +description: + The Pulse Density Modulation Interface Controller (PDMC) is + a PDM interface controller and decoder that support PDM format. + It integrates a clock generator driving the PDM microphone + and embeds filters which decimate the incoming bit stream to + obtain most common audio rates. + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,pdm + - rockchip,px30-pdm + - rockchip,rk1808-pdm + - rockchip,rk3308-pdm + - rockchip,rk3568-pdm + - rockchip,rv1126-pdm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: clock for PDM controller + - description: clock for PDM BUS + + clock-names: + items: + - const: pdm_clk + - const: pdm_hclk + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx + + power-domains: + maxItems: 1 + + resets: + items: + - description: reset for PDM controller + + reset-names: + items: + - const: pdm-m + + rockchip,path-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of PDM SDIx to PDM PATHx. + By default, they are mapped one-to-one. + maxItems: 4 + uniqueItems: true + items: + enum: [ 0, 1, 2, 3 ] + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pdm@ff040000 { + compatible = "rockchip,pdm"; + reg = <0x0 0xff040000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 16>; + dma-names = "rx"; + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-1 = <&pdmm0_clk_sleep + &pdmm0_sdi0_sleep + &pdmm0_sdi1_sleep + &pdmm0_sdi2_sleep + &pdmm0_sdi3_sleep>; + }; + }; diff --git a/dts/Bindings/sound/rt5659.txt b/dts/Bindings/sound/rt5659.txt index c473df5c87..013f534fa0 100644 --- a/dts/Bindings/sound/rt5659.txt +++ b/dts/Bindings/sound/rt5659.txt @@ -42,7 +42,7 @@ Optional properties: - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. - realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin. -- sound-name-prefix: Please refer to name-prefix.txt +- sound-name-prefix: Please refer to name-prefix.yaml - ports: A Codec may have a single or multiple I2S interfaces. These interfaces on Codec side can be described under 'ports' or 'port'. diff --git a/dts/Bindings/sound/simple-amplifier.txt b/dts/Bindings/sound/simple-amplifier.txt deleted file mode 100644 index b1b097cc9b..0000000000 --- a/dts/Bindings/sound/simple-amplifier.txt +++ /dev/null @@ -1,17 +0,0 @@ -Simple Amplifier Audio Driver - -Required properties: -- compatible : "dioo,dio2125" or "simple-audio-amplifier" - -Optional properties: -- enable-gpios : the gpio connected to the enable pin of the simple amplifier -- VCC-supply : power supply for the device, as covered - in Documentation/devicetree/bindings/regulator/regulator.txt - -Example: - -amp: analog-amplifier { - compatible = "simple-audio-amplifier"; - VCC-supply = <®ulator>; - enable-gpios = <&gpio GPIOH_3 0>; -}; diff --git a/dts/Bindings/sound/simple-audio-amplifier.yaml b/dts/Bindings/sound/simple-audio-amplifier.yaml new file mode 100644 index 0000000000..26379377a7 --- /dev/null +++ b/dts/Bindings/sound/simple-audio-amplifier.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/simple-audio-amplifier.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple Audio Amplifier Device Tree Bindings + +maintainers: + - Jerome Brunet + +properties: + compatible: + enum: + - dioo,dio2125 + - simple-audio-amplifier + + enable-gpios: + maxItems: 1 + + VCC-supply: + description: > + power supply for the device + + sound-name-prefix: + $ref: /schemas/types.yaml#/definitions/string + description: > + See ./name-prefix.txt + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + analog-amplifier { + compatible = "simple-audio-amplifier"; + VCC-supply = <®ulator>; + enable-gpios = <&gpio GPIOH_3 0>; + }; + +... diff --git a/dts/Bindings/sound/simple-audio-mux.yaml b/dts/Bindings/sound/simple-audio-mux.yaml index 5986d1fcbb..b5fc35ee9b 100644 --- a/dts/Bindings/sound/simple-audio-mux.yaml +++ b/dts/Bindings/sound/simple-audio-mux.yaml @@ -13,6 +13,9 @@ description: | Simple audio multiplexers are driven using gpios, allowing to select which of their input line is connected to the output line. +allOf: + - $ref: name-prefix.yaml# + properties: compatible: const: simple-audio-mux @@ -21,11 +24,7 @@ properties: description: | GPIOs used to select the input line. - sound-name-prefix: - $ref: /schemas/types.yaml#/definitions/string - description: - Used as prefix for sink/source names of the component. Must be a - unique string among multiple instances of the same component. + sound-name-prefix: true required: - compatible diff --git a/dts/Bindings/sound/socionext,uniphier-aio.yaml b/dts/Bindings/sound/socionext,uniphier-aio.yaml index 55ae198220..70f62ecd6e 100644 --- a/dts/Bindings/sound/socionext,uniphier-aio.yaml +++ b/dts/Bindings/sound/socionext,uniphier-aio.yaml @@ -46,7 +46,27 @@ properties: patternProperties: "^port@[0-9]$": - description: FIXME, Need to define what each port is. + description: | + Port number of DT node is specified by the following DAI channels that + depends on SoC. + ld11-aio,ld20-aio: + 0: hdmi + 1: pcmin2 + 2: line + 3: hpcmout1 + 4: pcmout3 + 5: hiecout1 + 6: epcmout2 + 7: epcmout3 + 8: hieccompout1 + pxs2-aio: + 0: hdmi + 1: line + 2: aux + 3: hiecout1 + 4: iecout1 + 5: hieccompout1 + 6: ieccompout1 $ref: audio-graph-port.yaml# unevaluatedProperties: false diff --git a/dts/Bindings/sound/socionext,uniphier-evea.yaml b/dts/Bindings/sound/socionext,uniphier-evea.yaml index 48ddfcbbcb..be6acfda99 100644 --- a/dts/Bindings/sound/socionext,uniphier-evea.yaml +++ b/dts/Bindings/sound/socionext,uniphier-evea.yaml @@ -40,7 +40,11 @@ properties: patternProperties: "^port@[0-9]$": - description: FIXME, Need to define what each port is. + description: | + Port number of DT node is specified by the following DAI channels. + 0: line1 + 1: hp + 2: line2 $ref: audio-graph-port.yaml# unevaluatedProperties: false diff --git a/dts/Bindings/sound/spdif-transmitter.txt b/dts/Bindings/sound/spdif-transmitter.txt deleted file mode 100644 index 55a85841dd..0000000000 --- a/dts/Bindings/sound/spdif-transmitter.txt +++ /dev/null @@ -1,10 +0,0 @@ -Device-Tree bindings for dummy spdif transmitter - -Required properties: - - compatible: should be "linux,spdif-dit". - -Example node: - - codec: spdif-transmitter { - compatible = "linux,spdif-dit"; - }; diff --git a/dts/Bindings/sound/st,stm32-i2s.yaml b/dts/Bindings/sound/st,stm32-i2s.yaml index 6feb5a09c1..d3966ae04a 100644 --- a/dts/Bindings/sound/st,stm32-i2s.yaml +++ b/dts/Bindings/sound/st,stm32-i2s.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 SPI/I2S Controller maintainers: - - Olivier Moysan + - Olivier Moysan description: The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode. diff --git a/dts/Bindings/sound/st,stm32-sai.yaml b/dts/Bindings/sound/st,stm32-sai.yaml index f97132400b..1538d11ce9 100644 --- a/dts/Bindings/sound/st,stm32-sai.yaml +++ b/dts/Bindings/sound/st,stm32-sai.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Serial Audio Interface (SAI) maintainers: - - Olivier Moysan + - Olivier Moysan description: The SAI interface (Serial Audio Interface) offers a wide set of audio diff --git a/dts/Bindings/sound/st,stm32-spdifrx.yaml b/dts/Bindings/sound/st,stm32-spdifrx.yaml index b7f7dc4522..837e830c47 100644 --- a/dts/Bindings/sound/st,stm32-spdifrx.yaml +++ b/dts/Bindings/sound/st,stm32-spdifrx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 S/PDIF receiver (SPDIFRX) maintainers: - - Olivier Moysan + - Olivier Moysan description: | The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with diff --git a/dts/Bindings/sound/test-component.yaml b/dts/Bindings/sound/test-component.yaml new file mode 100644 index 0000000000..17fdb43172 --- /dev/null +++ b/dts/Bindings/sound/test-component.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/test-component.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Test Component Device Tree Bindings + +maintainers: + - Kuninori Morimoto + +properties: + compatible: + enum: + - test-cpu + - test-cpu-verbose + - test-cpu-verbose-dai + - test-cpu-verbose-component + - test-codec + - test-codec-verbose + - test-codec-verbose-dai + - test-codec-verbose-component + +required: + - compatible + +additionalProperties: true + +examples: + - | + test_cpu { + compatible = "test-cpu"; + }; diff --git a/dts/Bindings/sound/wlf,wm8962.yaml b/dts/Bindings/sound/wlf,wm8962.yaml new file mode 100644 index 0000000000..0e6249d7c1 --- /dev/null +++ b/dts/Bindings/sound/wlf,wm8962.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/wlf,wm8962.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wolfson WM8962 Ultra-Low Power Stereo CODEC + +maintainers: + - patches@opensource.cirrus.com + +properties: + compatible: + const: wlf,wm8962 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + AVDD-supply: + description: Analogue supply. + + CPVDD-supply: + description: Charge pump power supply. + + DBVDD-supply: + description: Digital Buffer Supply. + + DCVDD-supply: + description: Digital Core Supply. + + MICVDD-supply: + description: Microphone bias amp supply. + + PLLVDD-supply: + description: PLL Supply + + SPKVDD1-supply: + description: Supply for left speaker drivers. + + SPKVDD2-supply: + description: Supply for right speaker drivers. + + spk-mono: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, the SPK_MONO bit of R51 (Class D Control 2) gets set, + indicating that the speaker is in mono mode. + + mic-cfg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Default register value for R48 (Additional Control 4). + If absent, the default should be the register default. + + gpio-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + description: + A list of GPIO configuration register values. If absent, no + configuration of these registers is performed. Note that only values + within [0x0, 0xffff] are valid. Any other value is regarded as setting + the GPIO register to its reset value 0x0. + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - AVDD-supply + - CPVDD-supply + - DBVDD-supply + - DCVDD-supply + - MICVDD-supply + - PLLVDD-supply + - SPKVDD1-supply + - SPKVDD2-supply + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + }; diff --git a/dts/Bindings/sound/wlf,wm8978.yaml b/dts/Bindings/sound/wlf,wm8978.yaml new file mode 100644 index 0000000000..96cf9fc9c8 --- /dev/null +++ b/dts/Bindings/sound/wlf,wm8978.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/wlf,wm8978.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wolfson WM8978 Codec Device Tree Bindings + +maintainers: + - patches@opensource.cirrus.com + +properties: + '#sound-dai-cells': + const: 0 + + compatible: + const: wlf,wm8978 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 526000 + +required: + - '#sound-dai-cells' + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + codec@0 { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0>; + spi-max-frequency = <500000>; + }; + }; + + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + }; + +... diff --git a/dts/Bindings/sound/wm8962.txt b/dts/Bindings/sound/wm8962.txt deleted file mode 100644 index c36c649ddf..0000000000 --- a/dts/Bindings/sound/wm8962.txt +++ /dev/null @@ -1,43 +0,0 @@ -WM8962 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "wlf,wm8962" - - - reg : the I2C address of the device. - -Optional properties: - - - clocks : The clock source of the mclk - - - spk-mono: This is a boolean property. If present, the SPK_MONO bit - of R51 (Class D Control 2) gets set, indicating that the speaker is - in mono mode. - - - mic-cfg : Default register value for R48 (Additional Control 4). - If absent, the default should be the register default. - - - gpio-cfg : A list of GPIO configuration register values. The list must - be 6 entries long. If absent, no configuration of these registers is - performed. And note that only the value within [0x0, 0xffff] is valid. - Any other value is regarded as setting the GPIO register by its reset - value 0x0. - -Example: - -wm8962: codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6QDL_CLK_CKO>; - - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; -}; diff --git a/dts/Bindings/spi/cdns,qspi-nor.yaml b/dts/Bindings/spi/cdns,qspi-nor.yaml index 0e7087cc8b..ca155abbda 100644 --- a/dts/Bindings/spi/cdns,qspi-nor.yaml +++ b/dts/Bindings/spi/cdns,qspi-nor.yaml @@ -11,6 +11,14 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,versal-ospi-1.0 + then: + required: + - power-domains properties: compatible: @@ -20,6 +28,7 @@ properties: - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi + - xlnx,versal-ospi-1.0 - const: cdns,qspi-nor - const: cdns,qspi-nor @@ -65,6 +74,9 @@ properties: data rather than the QSPI clock. Make sure that QSPI return clock is populated on the board before using this property. + power-domains: + maxItems: 1 + resets: maxItems: 2 diff --git a/dts/Bindings/spi/cdns,xspi.yaml b/dts/Bindings/spi/cdns,xspi.yaml new file mode 100644 index 0000000000..b8bb8a3dbf --- /dev/null +++ b/dts/Bindings/spi/cdns,xspi.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020-21 Cadence +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/cdns,xspi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence XSPI Controller + +maintainers: + - Parshuram Thombare + +description: | + The XSPI controller allows SPI protocol communication in + single, dual, quad or octal wire transmission modes for + read/write access to slaves such as SPI-NOR flash. + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + const: cdns,xspi-nor + + reg: + items: + - description: address and length of the controller register set + - description: address and length of the Slave DMA data port + - description: address and length of the auxiliary registers + + reg-names: + items: + - const: io + - const: sdma + - const: aux + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + + xspi: spi@a0010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdns,xspi-nor"; + reg = <0x0 0xa0010000 0x0 0x1040>, + <0x0 0xb0000000 0x0 0x1000>, + <0x0 0xa0020000 0x0 0x100>; + reg-names = "io", "sdma", "aux"; + interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <75000000>; + reg = <0>; + }; + + flash@1 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <75000000>; + reg = <1>; + }; + }; + }; diff --git a/dts/Bindings/spi/ingenic,spi.yaml b/dts/Bindings/spi/ingenic,spi.yaml new file mode 100644 index 0000000000..5b1c7a2a6a --- /dev/null +++ b/dts/Bindings/spi/ingenic,spi.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ingenic,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs SPI controller devicetree bindings + +maintainers: + - Artur Rojek + - Paul Cercueil + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - ingenic,jz4750-spi + - ingenic,jz4780-spi + - items: + - enum: + - ingenic,jz4760-spi + - ingenic,jz4770-spi + - const: ingenic,jz4750-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 2 + minItems: 2 + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + #include + spi@10043000 { + compatible = "ingenic,jz4770-spi", "ingenic,jz4750-spi"; + reg = <0x10043000 0x1c>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + clocks = <&cgu JZ4770_CLK_SSI0>; + + dmas = <&dmac1 23 0xffffffff>, <&dmac1 22 0xffffffff>; + dma-names = "rx", "tx"; + }; diff --git a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml index ef5698f426..055524fe83 100644 --- a/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/dts/Bindings/spi/qcom,spi-qcom-qspi.yaml @@ -21,7 +21,11 @@ allOf: properties: compatible: items: - - const: qcom,sdm845-qspi + - enum: + - qcom,sc7180-qspi + - qcom,sc7280-qspi + - qcom,sdm845-qspi + - const: qcom,qspi-v1 reg: diff --git a/dts/Bindings/spi/spi-nxp-fspi.txt b/dts/Bindings/spi/spi-nxp-fspi.txt deleted file mode 100644 index 8f34a7c7d8..0000000000 --- a/dts/Bindings/spi/spi-nxp-fspi.txt +++ /dev/null @@ -1,44 +0,0 @@ -* NXP Flex Serial Peripheral Interface (FSPI) - -Required properties: - - compatible : Should be "nxp,lx2160a-fspi" - "nxp,imx8qxp-fspi" - "nxp,imx8mm-fspi" - "nxp,imx8mp-fspi" - "nxp,imx8dxl-fspi" - - - reg : First contains the register location and length, - Second contains the memory mapping address and length - - reg-names : Should contain the resource reg names: - - fspi_base: configuration register address space - - fspi_mmap: memory mapped address space - - interrupts : Should contain the interrupt for the device - -Required SPI slave node properties: - - reg : There are two buses (A and B) with two chip selects each. - This encodes to which bus and CS the flash is connected: - - <0>: Bus A, CS 0 - - <1>: Bus A, CS 1 - - <2>: Bus B, CS 0 - - <3>: Bus B, CS 1 - -Example showing the usage of two SPI NOR slave devices on bus A: - -fspi0: spi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = <0 25 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - - mt35xu512aba0: flash@0 { - reg = <0>; - .... - }; - - mt35xu512aba1: flash@1 { - reg = <1>; - .... - }; -}; diff --git a/dts/Bindings/spi/spi-nxp-fspi.yaml b/dts/Bindings/spi/spi-nxp-fspi.yaml new file mode 100644 index 0000000000..283815d59e --- /dev/null +++ b/dts/Bindings/spi/spi-nxp-fspi.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Flex Serial Peripheral Interface (FSPI) + +maintainers: + - Kuldeep Singh + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + enum: + - nxp,imx8dxl-fspi + - nxp,imx8mm-fspi + - nxp,imx8mp-fspi + - nxp,imx8qxp-fspi + - nxp,lx2160a-fspi + + reg: + items: + - description: registers address space + - description: memory mapped address space + + reg-names: + items: + - const: fspi_base + - const: fspi_mmap + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI bus clock + - description: SPI serial clock + + clock-names: + items: + - const: fspi_en + - const: fspi + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + reg = <0x0 0x20c0000 0x0 0x100000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + clock-names = "fspi_en", "fspi"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; + }; + }; diff --git a/dts/Bindings/spi/spi-xlp.txt b/dts/Bindings/spi/spi-xlp.txt deleted file mode 100644 index f4925ec0ed..0000000000 --- a/dts/Bindings/spi/spi-xlp.txt +++ /dev/null @@ -1,38 +0,0 @@ -SPI Master controller for Netlogic XLP MIPS64 SOCs -================================================== - -Currently this SPI controller driver is supported for the following -Netlogic XLP SoCs: - XLP832, XLP316, XLP208, XLP980, XLP532 - -Required properties: -- compatible : Should be "netlogic,xlp832-spi". -- #address-cells : Number of cells required to define a chip select address - on the SPI bus. -- #size-cells : Should be zero. -- reg : Should contain register location and length. -- clocks : Phandle of the spi clock -- interrupts : Interrupt number used by this controller. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - - spi: xlp_spi@3a100 { - compatible = "netlogic,xlp832-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x3a100 0x100>; - clocks = <&spi_clk>; - interrupts = <34>; - interrupt-parent = <&pic>; - - spi_nor@1 { - compatible = "spansion,s25sl12801"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; /* Chip Select */ - spi-max-frequency = <40000000>; - }; -}; diff --git a/dts/Bindings/spi/st,stm32-qspi.yaml b/dts/Bindings/spi/st,stm32-qspi.yaml index 983c4e54c0..6ec6f55618 100644 --- a/dts/Bindings/spi/st,stm32-qspi.yaml +++ b/dts/Bindings/spi/st,stm32-qspi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings maintainers: - - Christophe Kerello - - Patrice Chotard + - Christophe Kerello + - Patrice Chotard allOf: - $ref: "spi-controller.yaml#" diff --git a/dts/Bindings/spi/st,stm32-spi.yaml b/dts/Bindings/spi/st,stm32-spi.yaml index 2d9af4c506..3d64bed266 100644 --- a/dts/Bindings/spi/st,stm32-spi.yaml +++ b/dts/Bindings/spi/st,stm32-spi.yaml @@ -13,8 +13,8 @@ description: | from 4 to 32-bit data size. maintainers: - - Erwan Leray - - Fabrice Gasnier + - Erwan Leray + - Fabrice Gasnier allOf: - $ref: "spi-controller.yaml#" diff --git a/dts/Bindings/sram/sram.yaml b/dts/Bindings/sram/sram.yaml index 3eda5049d1..d4e418b6a1 100644 --- a/dts/Bindings/sram/sram.yaml +++ b/dts/Bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram reg: @@ -60,7 +61,7 @@ properties: type: boolean patternProperties: - "^([a-z]*-)?sram(-section)?@[a-f0-9]+$": + "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$": type: object description: Each child of the sram node specifies a region of reserved memory. @@ -135,7 +136,9 @@ if: properties: compatible: contains: - const: rockchip,rk3288-pmu-sram + enum: + - qcom,rpm-msg-ram + - rockchip,rk3288-pmu-sram else: required: diff --git a/dts/Bindings/submitting-patches.rst b/dts/Bindings/submitting-patches.rst index 8087780f16..36a17b250c 100644 --- a/dts/Bindings/submitting-patches.rst +++ b/dts/Bindings/submitting-patches.rst @@ -63,6 +63,9 @@ I. For patch submitters string that is matched by the driver (as in the "nvidia,tegra20-pcie" example above). + 9) Bindings are actively used by multiple projects other than the Linux + Kernel, extra care and consideration may need to be taken when making changes + to existing bindings. II. For kernel maintainers ========================== diff --git a/dts/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/dts/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml new file mode 100644 index 0000000000..8273ac55b6 --- /dev/null +++ b/dts/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC HC Thermal Monitoring +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm-hc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: + - 256 + - 512 + - 1024 + default: 1024 + +patternProperties: + "^([-a-z0-9]*)@[0-7]$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM + minimum: 0 + maximum: 7 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time-us: + description: Time between AMUX getting configured and the ADC starting conversion. + enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000] + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the + signal is fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by + which input signal is multiplied. For example, <1 3> indicates the + signal is scaled down to 1/3 of its value before ADC measurement. If + property is not found default value depending on chip will be used. + items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10 ] + + required: + - reg + - io-channels + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + spmi_bus { + #address-cells = <1>; + #size-cells = <0>; + pm8998_adc: adc@3100 { + reg = <0x3100>; + compatible = "qcom,spmi-adc-rev2"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* Other propreties are omitted */ + adc-chan@4c { + reg = ; + }; + }; + + pm8998_adc_tm: adc-tm@3400 { + compatible = "qcom,spmi-adc-tm-hc"; + reg = <0x3400>; + interrupts = <0x2 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + thermistor@1 { + reg = <1>; + io-channels = <&pm8998_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + }; + }; +... diff --git a/dts/Bindings/thermal/rockchip-thermal.yaml b/dts/Bindings/thermal/rockchip-thermal.yaml index b96ea277b5..f6c1be226a 100644 --- a/dts/Bindings/thermal/rockchip-thermal.yaml +++ b/dts/Bindings/thermal/rockchip-thermal.yaml @@ -12,14 +12,14 @@ maintainers: properties: compatible: enum: - - rockchip,px30-tsadc # PX30 SoCs - - rockchip,rv1108-tsadc # RV1108 SoCs - - rockchip,rk3228-tsadc # RK3228 SoCs - - rockchip,rk3288-tsadc # RK3288 SoCs - - rockchip,rk3328-tsadc # RK3328 SoCs - - rockchip,rk3368-tsadc # RK3368 SoCs - - rockchip,rk3399-tsadc # RK3399 SoCs - - rockchip,rk3568-tsadc # RK3568 SoCs + - rockchip,px30-tsadc + - rockchip,rk3228-tsadc + - rockchip,rk3288-tsadc + - rockchip,rk3328-tsadc + - rockchip,rk3368-tsadc + - rockchip,rk3399-tsadc + - rockchip,rk3568-tsadc + - rockchip,rv1108-tsadc reg: maxItems: 1 @@ -37,11 +37,15 @@ properties: - const: apb_pclk resets: - maxItems: 1 + minItems: 1 + maxItems: 3 reset-names: + minItems: 1 items: - const: tsadc-apb + - const: tsadc + - const: tsadc-phy "#thermal-sensor-cells": const: 1 @@ -71,7 +75,6 @@ required: - clocks - clock-names - resets - - reset-names - "#thermal-sensor-cells" additionalProperties: false diff --git a/dts/Bindings/thermal/socionext,uniphier-thermal.yaml b/dts/Bindings/thermal/socionext,uniphier-thermal.yaml index 553c9dcdae..c5b25ce449 100644 --- a/dts/Bindings/thermal/socionext,uniphier-thermal.yaml +++ b/dts/Bindings/thermal/socionext,uniphier-thermal.yaml @@ -20,6 +20,7 @@ properties: - socionext,uniphier-pxs2-thermal - socionext,uniphier-ld20-thermal - socionext,uniphier-pxs3-thermal + - socionext,uniphier-nx1-thermal interrupts: maxItems: 1 diff --git a/dts/Bindings/thermal/st,stm32-thermal.yaml b/dts/Bindings/thermal/st,stm32-thermal.yaml index c0f59c5600..bee41cff51 100644 --- a/dts/Bindings/thermal/st,stm32-thermal.yaml +++ b/dts/Bindings/thermal/st,stm32-thermal.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 digital thermal sensor (DTS) binding maintainers: - - David Hernandez Sanchez + - Pascal Paillet properties: compatible: diff --git a/dts/Bindings/timer/ingenic,sysost.yaml b/dts/Bindings/timer/ingenic,sysost.yaml index df3eb76045..98648bf9e1 100644 --- a/dts/Bindings/timer/ingenic,sysost.yaml +++ b/dts/Bindings/timer/ingenic,sysost.yaml @@ -46,7 +46,7 @@ additionalProperties: false examples: - | - #include + #include ost: timer@12000000 { compatible = "ingenic,x1000-ost"; diff --git a/dts/Bindings/timer/ingenic,tcu.yaml b/dts/Bindings/timer/ingenic,tcu.yaml index 8165df4599..7fb37eae9d 100644 --- a/dts/Bindings/timer/ingenic,tcu.yaml +++ b/dts/Bindings/timer/ingenic,tcu.yaml @@ -237,7 +237,7 @@ additionalProperties: false examples: - | - #include + #include #include tcu: timer@10002000 { compatible = "ingenic,jz4770-tcu", "ingenic,jz4760-tcu", "simple-mfd"; diff --git a/dts/Bindings/timer/st,stm32-timer.yaml b/dts/Bindings/timer/st,stm32-timer.yaml index 176aa3c9ba..937aa8a563 100644 --- a/dts/Bindings/timer/st,stm32-timer.yaml +++ b/dts/Bindings/timer/st,stm32-timer.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings maintainers: - - Benjamin Gaignard + - Fabrice Gasnier + - Patrice Chotard properties: compatible: diff --git a/dts/Bindings/trivial-devices.yaml b/dts/Bindings/trivial-devices.yaml index 1e4b3464d7..791079021f 100644 --- a/dts/Bindings/trivial-devices.yaml +++ b/dts/Bindings/trivial-devices.yaml @@ -41,10 +41,6 @@ properties: - adi,adp5585-02 # Analog Devices ADP5589 Keypad Decoder and I/O Expansion - adi,adp5589 - # +/-1C TDM Extended Temp Range I.C - - adi,adt7461 - # +/-1C TDM Extended Temp Range I.C - - adt7461 # AMS iAQ-Core VOC Sensor - ams,iaq-core # i2c serial eeprom (24cxx) @@ -77,6 +73,8 @@ properties: - dallas,ds4510 # Digital Thermometer and Thermostat - dallas,ds75 + # Delta Electronics DPS-650-AB power supply + - delta,dps650ab # Delta Electronics DPS920AB 920W 54V Power Supply - delta,dps920ab # 1/4 Brick DC/DC Regulated Power Module @@ -113,8 +111,14 @@ properties: - mps,mp2888 # Monolithic Power Systems Inc. multi-phase controller mp2975 - mps,mp2975 - # G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface - - gmt,g751 + # Honeywell Humidicon HIH-6130 humidity/temperature sensor + - honeywell,hi6130 + # IBM Common Form Factor Power Supply Versions (all versions) + - ibm,cffps + # IBM Common Form Factor Power Supply Versions 1 + - ibm,cffps1 + # IBM Common Form Factor Power Supply Versions 2 + - ibm,cffps2 # Infineon IR36021 digital POL buck controller - infineon,ir36021 # Infineon IR38064 Voltage Regulator @@ -307,16 +311,22 @@ properties: - ti,hdc1050 # Temperature and humidity sensor with i2c interface - ti,hdc1080 + # Thermometer with SPI interface + - ti,lm70 + - ti,lm71 # Temperature sensor with 2-wire interface - ti,lm73 + # Thermometer with SPI interface + - ti,lm74 # Temperature sensor with integrated fan control - ti,lm96000 # I2C Touch-Screen Controller - ti,tsc2003 # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface - - ti,tmp102 - # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface - ti,tmp103 + # Thermometer with SPI interface + - ti,tmp121 + - ti,tmp122 # Digital Temperature Sensor - ti,tmp275 # TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus diff --git a/dts/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/Bindings/ufs/samsung,exynos-ufs.yaml index b9ca8ef4f2..95ac1c1833 100644 --- a/dts/Bindings/ufs/samsung,exynos-ufs.yaml +++ b/dts/Bindings/ufs/samsung,exynos-ufs.yaml @@ -20,6 +20,8 @@ properties: compatible: enum: - samsung,exynos7-ufs + - samsung,exynosautov9-ufs + - samsung,exynosautov9-ufs-vh reg: items: @@ -54,6 +56,14 @@ properties: phy-names: const: ufs-phy + samsung,sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: Should be phandle/offset pair. The phandle to the syscon node + which indicates the FSYSx sysreg interface and the offset of + the control register for UFS io coherency setting. + + dma-coherent: true + required: - compatible - reg diff --git a/dts/Bindings/usb/atmel-usb.txt b/dts/Bindings/usb/atmel-usb.txt index a4002624ba..f512f02907 100644 --- a/dts/Bindings/usb/atmel-usb.txt +++ b/dts/Bindings/usb/atmel-usb.txt @@ -39,6 +39,10 @@ Required properties: "ehci_clk" for the peripheral clock "usb_clk" for the UTMI clock +Optional properties: + - phy_type : For multi port host USB controllers, should be one of + "utmi", or "hsic". + usb1: ehci@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; diff --git a/dts/Bindings/usb/dwc2.yaml b/dts/Bindings/usb/dwc2.yaml index 10c7d9b6cc..56a818478c 100644 --- a/dts/Bindings/usb/dwc2.yaml +++ b/dts/Bindings/usb/dwc2.yaml @@ -9,6 +9,9 @@ title: DesignWare HS OTG USB 2.0 controller Bindings maintainers: - Rob Herring +allOf: + - $ref: usb-drd.yaml# + properties: compatible: oneOf: @@ -101,12 +104,15 @@ properties: description: reference to the VBUS and ID sensing comparators supply, in order to perform OTG operation, used on STM32MP15 SoCs. - dr_mode: - enum: [host, peripheral, otg] + dr_mode: true - usb-role-switch: - $ref: /schemas/types.yaml#/definitions/flag - description: Support role switch. + otg-rev: true + + hnp-disable: true + + srp-disable: true + + usb-role-switch: true g-rx-fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/Bindings/usb/ingenic,musb.yaml b/dts/Bindings/usb/ingenic,musb.yaml index f506225a4d..59212358fc 100644 --- a/dts/Bindings/usb/ingenic,musb.yaml +++ b/dts/Bindings/usb/ingenic,musb.yaml @@ -58,7 +58,7 @@ additionalProperties: false examples: - | - #include + #include usb_phy: usb-phy { compatible = "usb-nop-xceiv"; #phy-cells = <0>; diff --git a/dts/Bindings/usb/qcom,dwc3.yaml b/dts/Bindings/usb/qcom,dwc3.yaml index e70afc40ed..2bdaba023c 100644 --- a/dts/Bindings/usb/qcom,dwc3.yaml +++ b/dts/Bindings/usb/qcom,dwc3.yaml @@ -13,6 +13,7 @@ properties: compatible: items: - enum: + - qcom,ipq6018-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - qcom,sc7180-dwc3 diff --git a/dts/Bindings/usb/smsc,usb3503.yaml b/dts/Bindings/usb/smsc,usb3503.yaml new file mode 100644 index 0000000000..39228a506b --- /dev/null +++ b/dts/Bindings/usb/smsc,usb3503.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/smsc,usb3503.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMSC USB3503 High-Speed Hub Controller Device Tree Bindings + +maintainers: + - Dongjin Kim + +properties: + compatible: + enum: + - smsc,usb3503 + - smsc,usb3503a + + reg: + maxItems: 1 + + connect-gpios: + maxItems: 1 + description: > + GPIO for connect + + intn-gpios: + maxItems: 1 + description: > + GPIO for interrupt + + reset-gpios: + maxItems: 1 + description: > + GPIO for reset + + disabled-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 1 + maximum: 3 + description: > + Specifies the ports unused using their port number. Do not describe this + property if all ports have to be enabled. + + initial-mode: + enum: [1, 2] + description: > + Specifies initial mode. 1 for Hub mode, 2 for standby mode. + + clocks: + maxItems: 1 + description: > + Clock used for driving REFCLK signal. If not provided the driver assumes + that clock signal is always available, its rate is specified by REF_SEL + pins and a value from the primary reference clock frequencies table is + used. + + clock-names: + const: refclk + + refclk-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Frequency of the REFCLK signal as defined by REF_SEL pins. If not + provided, driver will not set rate of the REFCLK signal and assume that a + value from the primary reference clock frequencies table is used. + +required: + - compatible + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@8 { + compatible = "smsc,usb3503"; + reg = <0x08>; + connect-gpios = <&gpx3 0 1>; + disabled-ports = <2 3>; + intn-gpios = <&gpx3 4 1>; + reset-gpios = <&gpx3 5 1>; + initial-mode = <1>; + clocks = <&clks 80>; + clock-names = "refclk"; + }; + }; + + - | + #include + + usb-hub { + /* I2C is not connected */ + compatible = "smsc,usb3503"; + initial-mode = <1>; /* initialize in HUB mode */ + disabled-ports = <1>; + intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ + connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + refclk-frequency = <19200000>; + }; + +... diff --git a/dts/Bindings/usb/snps,dwc3.yaml b/dts/Bindings/usb/snps,dwc3.yaml index 078fb78895..25ac2c93dc 100644 --- a/dts/Bindings/usb/snps,dwc3.yaml +++ b/dts/Bindings/usb/snps,dwc3.yaml @@ -73,15 +73,15 @@ properties: phys: minItems: 1 - items: - - description: USB2/HS PHY - - description: USB3/SS PHY + maxItems: 2 phy-names: minItems: 1 + maxItems: 2 items: - - const: usb2-phy - - const: usb3-phy + enum: + - usb2-phy + - usb3-phy resets: minItems: 1 @@ -252,6 +252,14 @@ properties: minimum: 0 maximum: 0x3f + snps,ref-clock-period-ns: + description: + Value for REFCLKPER field of GUCTL register for reference clock period in + nanoseconds, when the hardware set default does not match the actual + clock. + minimum: 1 + maximum: 0x3ff + snps,rx-thr-num-pkt-prd: description: Periodic ESS RX packet threshold count (host mode only). Set this and diff --git a/dts/Bindings/usb/st,stusb160x.yaml b/dts/Bindings/usb/st,stusb160x.yaml index 9a51efa9d1..ead1571e0e 100644 --- a/dts/Bindings/usb/st,stusb160x.yaml +++ b/dts/Bindings/usb/st,stusb160x.yaml @@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: STMicroelectronics STUSB160x Type-C controller bindings maintainers: - - Amelie Delaunay + - Amelie Delaunay properties: compatible: diff --git a/dts/Bindings/usb/ti,tps6598x.yaml b/dts/Bindings/usb/ti,tps6598x.yaml index f6819bf2a3..a4c53b1f1a 100644 --- a/dts/Bindings/usb/ti,tps6598x.yaml +++ b/dts/Bindings/usb/ti,tps6598x.yaml @@ -12,10 +12,14 @@ maintainers: description: | Texas Instruments 6598x Type-C Port Switch and Power Delivery controller + A variant of this controller known as Apple CD321x or Apple ACE is also + present on hardware with Apple SoCs such as the M1. + properties: compatible: enum: - ti,tps6598x + - apple,cd321x reg: maxItems: 1 diff --git a/dts/Bindings/usb/udc-xilinx.txt b/dts/Bindings/usb/udc-xilinx.txt deleted file mode 100644 index 47b4e397a0..0000000000 --- a/dts/Bindings/usb/udc-xilinx.txt +++ /dev/null @@ -1,18 +0,0 @@ -Xilinx USB2 device controller - -Required properties: -- compatible : Should be "xlnx,usb2-device-4.00.a" -- reg : Physical base address and size of the USB2 - device registers map. -- interrupts : Should contain single irq line of USB2 device - controller -- xlnx,has-builtin-dma : if DMA is included - -Example: - axi-usb2-device@42e00000 { - compatible = "xlnx,usb2-device-4.00.a"; - interrupts = <0x0 0x39 0x1>; - reg = <0x42e00000 0x10000>; - xlnx,has-builtin-dma; - }; - diff --git a/dts/Bindings/usb/usb3503.txt b/dts/Bindings/usb/usb3503.txt deleted file mode 100644 index 057dd384d4..0000000000 --- a/dts/Bindings/usb/usb3503.txt +++ /dev/null @@ -1,39 +0,0 @@ -SMSC USB3503 High-Speed Hub Controller - -Required properties: -- compatible: Should be "smsc,usb3503" or "smsc,usb3503a". - -Optional properties: -- reg: Specifies the i2c slave address, it is required and should be 0x08 - if I2C is used. -- connect-gpios: Should specify GPIO for connect. -- disabled-ports: Should specify the ports unused. - '1' or '2' or '3' are available for this property to describe the port - number. 1~3 property values are possible to be described. - Do not describe this property if all ports have to be enabled. -- intn-gpios: Should specify GPIO for interrupt. -- reset-gpios: Should specify GPIO for reset. -- initial-mode: Should specify initial mode. - (1 for HUB mode, 2 for STANDBY mode) -- refclk: Clock used for driving REFCLK signal (optional, if not provided - the driver assumes that clock signal is always available, its - rate is specified by REF_SEL pins and a value from the primary - reference clock frequencies table is used). Use clocks and - clock-names in order to assign it -- refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL - pins (optional, if not provided, driver will not set rate of the - REFCLK signal and assume that a value from the primary reference - clock frequencies table is used) - -Examples: - usb3503@8 { - compatible = "smsc,usb3503"; - reg = <0x08>; - connect-gpios = <&gpx3 0 1>; - disabled-ports = <2 3>; - intn-gpios = <&gpx3 4 1>; - reset-gpios = <&gpx3 5 1>; - initial-mode = <1>; - clocks = <&clks 80>; - clock-names = "refclk"; - }; diff --git a/dts/Bindings/usb/xlnx,usb2.yaml b/dts/Bindings/usb/xlnx,usb2.yaml new file mode 100644 index 0000000000..04c123c725 --- /dev/null +++ b/dts/Bindings/usb/xlnx,usb2.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/xlnx,usb2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx udc controller + +maintainers: + - Manish Narani + +properties: + compatible: + const: xlnx,usb2-device-4.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + xlnx,has-builtin-dma: + description: + If present, hardware has dma capability. + type: boolean + + clocks: + minItems: 1 + + clock-names: + const: s_axi_aclk + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + axi-usb2-device@42e00000 { + compatible = "xlnx,usb2-device-4.00.a"; + interrupts = <0x0 0x39 0x1>; + reg = <0xee000000 0xc00>; + xlnx,has-builtin-dma; + }; diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml index a867f7102c..66d6432fd7 100644 --- a/dts/Bindings/vendor-prefixes.yaml +++ b/dts/Bindings/vendor-prefixes.yaml @@ -131,6 +131,8 @@ patternProperties: description: Asahi Kasei Corp. "^asc,.*": description: All Sensors Corporation + "^asix,.*": + description: ASIX Electronics Corporation "^aspeed,.*": description: ASPEED Technology Inc. "^asus,.*": @@ -191,6 +193,8 @@ patternProperties: description: B&R Industrial Automation GmbH "^bticino,.*": description: Bticino International + "^calamp,.*": + description: CalAmp Corp. "^calaosystems,.*": description: CALAO Systems SAS "^calxeda,.*": @@ -335,6 +339,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^edimax,.*": + description: EDIMAX Technology Co., Ltd "^edt,.*": description: Emerging Display Technologies "^eeti,.*": @@ -353,6 +359,8 @@ patternProperties: description: Shenzhen Elida Technology Co., Ltd. "^elimo,.*": description: Elimo Engineering Ltd. + "^elpida,.*": + description: Elpida Memory, Inc. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. "^emlid,.*": @@ -395,6 +403,8 @@ patternProperties: description: Exar Corporation "^excito,.*": description: Excito + "^exegin,.*": + description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor "^facebook,.*": @@ -509,6 +519,8 @@ patternProperties: description: Hycon Technology Corp. "^hydis,.*": description: Hydis Technologies + "^hynix,.*": + description: SK Hynix Inc. "^hyundai,.*": description: Hyundai Technology "^i2se,.*": @@ -577,6 +589,8 @@ patternProperties: description: JEDEC Solid State Technology Association "^jesurun,.*": description: Shenzhen Jesurun Electronics Business Dept. + "^jethome,.*": + description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. "^kam,.*": @@ -653,6 +667,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^liteon,.*": + description: LITE-ON Technology Corp. "^litex,.*": description: LiteX SoC builder "^lltc,.*": @@ -1018,6 +1034,8 @@ patternProperties: description: Shenzhen SEI Robotics Co., Ltd "^semtech,.*": description: Semtech Corporation + "^senseair,.*": + description: Senseair AB "^sensirion,.*": description: Sensirion AG "^sensortek,.*": @@ -1100,8 +1118,12 @@ patternProperties: description: Spansion Inc. "^sparkfun,.*": description: SparkFun Electronics + "^spinalhdl,.*": + description: SpinalHDL "^sprd,.*": description: Spreadtrum Communications Inc. + "^ssi,.*": + description: SSI Computer Corp "^sst,.*": description: Silicon Storage Technology, Inc. "^sstar,.*": @@ -1264,6 +1286,8 @@ patternProperties: description: Vitesse Semiconductor Corporation "^vivante,.*": description: Vivante Corporation + "^vivax,.*": + description: Vivax brand by M SAN Grupa d.o.o. "^vocore,.*": description: VoCore Studio "^voipac,.*": diff --git a/dts/Bindings/w1/w1-gpio.txt b/dts/Bindings/w1/w1-gpio.txt deleted file mode 100644 index 3d6554eac2..0000000000 --- a/dts/Bindings/w1/w1-gpio.txt +++ /dev/null @@ -1,27 +0,0 @@ -w1-gpio devicetree bindings - -Required properties: - - - compatible: "w1-gpio" - - gpios: one or two GPIO specs: - - the first one is used as data I/O pin - - the second one is optional. If specified, it is used as - enable pin for an external pin pullup. - -Optional properties: - - - linux,open-drain: if specified, the data pin is considered in - open-drain mode. - -Also refer to the generic w1.txt document. - -Examples: - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - - battery { - // ... - }; - }; diff --git a/dts/Bindings/w1/w1-gpio.yaml b/dts/Bindings/w1/w1-gpio.yaml new file mode 100644 index 0000000000..8eef238016 --- /dev/null +++ b/dts/Bindings/w1/w1-gpio.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/w1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitbanged GPIO 1-Wire Bus Device Tree Bindings + +maintainers: + - Daniel Mack + +properties: + compatible: + const: w1-gpio + + gpios: + minItems: 1 + items: + - description: Data I/O pin + - description: Enable pin for an external pull-up resistor + + linux,open-drain: + type: boolean + description: > + If specified, the data pin is considered in open-drain mode. + +required: + - compatible + - gpios + +additionalProperties: + type: object + +examples: + - | + #include + + onewire { + compatible = "w1-gpio"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + +... diff --git a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c4..43afa24513 100644 --- a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -24,16 +24,31 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt - const: allwinner,sun4i-a10-wdt + - const: allwinner,sun20i-d1-wdt + - items: + - const: allwinner,sun20i-d1-wdt-reset + - const: allwinner,sun20i-d1-wdt reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input, only found on some variants + + clock-names: + minItems: 1 + items: + - const: hosc + - const: losc interrupts: maxItems: 1 @@ -44,6 +59,35 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun20i-d1-wdt + - allwinner,sun20i-d1-wdt-reset + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + +then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/dts/Bindings/watchdog/mtk-wdt.txt b/dts/Bindings/watchdog/mtk-wdt.txt index a4e31ce96e..0114871f88 100644 --- a/dts/Bindings/watchdog/mtk-wdt.txt +++ b/dts/Bindings/watchdog/mtk-wdt.txt @@ -22,6 +22,7 @@ Required properties: - reg : Specifies base physical address and size of the registers. Optional properties: +- mediatek,disable-extrst: disable send output reset signal - interrupts: Watchdog pre-timeout (bark) interrupt. - timeout-sec: contains the watchdog timeout in seconds. - #reset-cells: Should be 1. @@ -31,6 +32,7 @@ Example: watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; interrupts = ; timeout-sec = <10>; diff --git a/dts/Bindings/watchdog/st,stm32-iwdg.yaml b/dts/Bindings/watchdog/st,stm32-iwdg.yaml index 481bf91f98..39736449ba 100644 --- a/dts/Bindings/watchdog/st,stm32-iwdg.yaml +++ b/dts/Bindings/watchdog/st,stm32-iwdg.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings maintainers: - - Yannick Fertre - - Christophe Roullier + - Yannick Fertre + - Christophe Roullier allOf: - $ref: "watchdog.yaml#" diff --git a/dts/Bindings/writing-bindings.rst b/dts/Bindings/writing-bindings.rst index f7dfb98c15..18d9e0689d 100644 --- a/dts/Bindings/writing-bindings.rst +++ b/dts/Bindings/writing-bindings.rst @@ -44,7 +44,7 @@ Properties of prior implementations. DO add new compatibles in case there are new features or bugs. -- DO use a vendor prefix on device specific property names. Consider if +- DO use a vendor prefix on device-specific property names. Consider if properties could be common among devices of the same class. Check other existing bindings for similar devices. diff --git a/dts/Bindings/writing-schema.rst b/dts/Bindings/writing-schema.rst index 23d6579aea..ea21c72aeb 100644 --- a/dts/Bindings/writing-schema.rst +++ b/dts/Bindings/writing-schema.rst @@ -4,7 +4,7 @@ Writing Devicetree Bindings in json-schema ========================================== Devicetree bindings are written using json-schema vocabulary. Schema files are -written in a JSON compatible subset of YAML. YAML is used instead of JSON as it +written in a JSON-compatible subset of YAML. YAML is used instead of JSON as it is considered more human readable and has some advantages such as allowing comments (Prefixed with '#'). @@ -22,16 +22,16 @@ $id URI typically containing the binding's filename and path. For DT schema, it must begin with "http://devicetree.org/schemas/". The URL is used in constructing references to other files specified in schema "$ref" properties. A $ref value - with a leading '/' will have the hostname prepended. A $ref value a relative - path or filename only will be prepended with the hostname and path components - of the current schema file's '$id' value. A URL is used even for local files, - but there may not actually be files present at those locations. + with a leading '/' will have the hostname prepended. A $ref value with only a + relative path or filename will be prepended with the hostname and path + components of the current schema file's '$id' value. A URL is used even for + local files, but there may not actually be files present at those locations. $schema Indicates the meta-schema the schema file adheres to. title - A one line description on the contents of the binding schema. + A one-line description on the contents of the binding schema. maintainers A DT specific property. Contains a list of email address(es) @@ -45,8 +45,8 @@ description select Optional. A json-schema used to match nodes for applying the - schema. By default without 'select', nodes are matched against their possible - compatible string values or node name. Most bindings should not need select. + schema. By default, without 'select', nodes are matched against their possible + compatible-string values or node name. Most bindings should not need select. allOf Optional. A list of other schemas to include. This is used to @@ -56,7 +56,8 @@ allOf properties A set of sub-schema defining all the DT properties for the binding. The exact schema syntax depends on whether properties are known, - common properties (e.g. 'interrupts') or are binding/vendor specific properties. + common properties (e.g. 'interrupts') or are binding/vendor-specific + properties. A property can also define a child DT node with child properties defined under it. @@ -81,23 +82,23 @@ Property Schema The 'properties' section of the schema contains all the DT properties for a binding. Each property contains a set of constraints using json-schema -vocabulary for that property. The properties schemas are what is used for +vocabulary for that property. The properties schemas are what are used for validation of DT files. -For common properties, only additional constraints not covered by the common +For common properties, only additional constraints not covered by the common, binding schema need to be defined such as how many values are valid or what possible values are valid. -Vendor specific properties will typically need more detailed schema. With the +Vendor-specific properties will typically need more detailed schema. With the exception of boolean properties, they should have a reference to a type in schemas/types.yaml. A "description" property is always required. -The Devicetree schemas don't exactly match the YAML encoded DT data produced by +The Devicetree schemas don't exactly match the YAML-encoded DT data produced by dtc. They are simplified to make them more compact and avoid a bunch of boilerplate. The tools process the schema files to produce the final schema for validation. There are currently 2 transformations the tools perform. -The default for arrays in json-schema is they are variable sized and allow more +The default for arrays in json-schema is they are variable-sized and allow more entries than explicitly defined. This can be restricted by defining 'minItems', 'maxItems', and 'additionalItems'. However, for DeviceTree Schemas, a fixed size is desired in most cases, so these properties are added based on the -- cgit v1.2.3