From a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 10 Jan 2017 08:26:15 +0100 Subject: dts: update to v4.10-rc1 Signed-off-by: Sascha Hauer --- dts/src/arc/abilis_tb10x.dtsi | 1 + dts/src/arc/axs101.dts | 2 +- dts/src/arc/axs103_idu.dts | 2 +- dts/src/arc/haps_hs.dts | 69 +++++++++++++++++++++++++++++++++++ dts/src/arc/haps_hs_idu.dts | 85 +++++++++++++++++++++++++++++++++++++++++++ dts/src/arc/zebu_hs.dts | 69 ----------------------------------- dts/src/arc/zebu_hs_idu.dts | 85 ------------------------------------------- 7 files changed, 157 insertions(+), 156 deletions(-) create mode 100644 dts/src/arc/haps_hs.dts create mode 100644 dts/src/arc/haps_hs_idu.dts delete mode 100644 dts/src/arc/zebu_hs.dts delete mode 100644 dts/src/arc/zebu_hs_idu.dts (limited to 'dts/src/arc') diff --git a/dts/src/arc/abilis_tb10x.dtsi b/dts/src/arc/abilis_tb10x.dtsi index de53f5c325..3121536b25 100644 --- a/dts/src/arc/abilis_tb10x.dtsi +++ b/dts/src/arc/abilis_tb10x.dtsi @@ -129,6 +129,7 @@ data-width = <4>; clocks = <&ahb_clk>; clock-names = "hclk"; + multi-block = <1 1 1 1 1 1>; }; i2c0: i2c@FF120000 { diff --git a/dts/src/arc/axs101.dts b/dts/src/arc/axs101.dts index d9b9b9dcfc..70aec7d6ca 100644 --- a/dts/src/arc/axs101.dts +++ b/dts/src/arc/axs101.dts @@ -17,6 +17,6 @@ compatible = "snps,axs101", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60"; }; }; diff --git a/dts/src/arc/axs103_idu.dts b/dts/src/arc/axs103_idu.dts index 070c297822..5c843d9b4a 100644 --- a/dts/src/arc/axs103_idu.dts +++ b/dts/src/arc/axs103_idu.dts @@ -20,6 +20,6 @@ compatible = "snps,axs103", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0 video=1280x720@60"; }; }; diff --git a/dts/src/arc/haps_hs.dts b/dts/src/arc/haps_hs.dts new file mode 100644 index 0000000000..1c1324e849 --- /dev/null +++ b/dts/src/arc/haps_hs.dts @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs.dtsi" + +/ { + model = "snps,zebu_hs"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@f0000000 { + compatible = "ns8250"; + reg = <0xf0000000 0x2000>; + interrupts = <24>; + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/haps_hs_idu.dts b/dts/src/arc/haps_hs_idu.dts new file mode 100644 index 0000000000..65204b4c0f --- /dev/null +++ b/dts/src/arc/haps_hs_idu.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs_idu.dtsi" + +/ { + model = "snps,zebu_hs-smp"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; /* 50 MHZ */ + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; +/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + /* + distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ + #interrupt-cells = <2>; + interrupts = <24 25 26 27 28 29 30 31>; + + }; + + uart0: serial@f0000000 { + /* compatible = "ns8250"; Doesn't use FIFOs */ + compatible = "ns16550a"; + reg = <0xf0000000 0x2000>; + interrupt-parent = <&idu_intc>; + /* interrupts = <0 1>; DEST=1*/ + /* interrupts = <0 2>; DEST=2*/ + interrupts = <0 0>; /* RR*/ + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/zebu_hs.dts b/dts/src/arc/zebu_hs.dts deleted file mode 100644 index 1c1324e849..0000000000 --- a/dts/src/arc/zebu_hs.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton_hs.dtsi" - -/ { - model = "snps,zebu_hs"; - compatible = "snps,zebu_hs"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&core_intc>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 */ - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; - }; - - aliases { - serial0 = &uart0; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - core_clk: core_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - core_intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - uart0: serial@f0000000 { - compatible = "ns8250"; - reg = <0xf0000000 0x2000>; - interrupts = <24>; - clock-frequency = <50000000>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - }; - - arcpct0: pct { - compatible = "snps,archs-pct"; - #interrupt-cells = <1>; - interrupts = <20>; - }; - }; -}; diff --git a/dts/src/arc/zebu_hs_idu.dts b/dts/src/arc/zebu_hs_idu.dts deleted file mode 100644 index 65204b4c0f..0000000000 --- a/dts/src/arc/zebu_hs_idu.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton_hs_idu.dtsi" - -/ { - model = "snps,zebu_hs-smp"; - compatible = "snps,zebu_hs"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&core_intc>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 */ - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; - }; - - aliases { - serial0 = &uart0; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - core_clk: core_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; /* 50 MHZ */ - }; - - core_intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; -/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - /* - distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ - #interrupt-cells = <2>; - interrupts = <24 25 26 27 28 29 30 31>; - - }; - - uart0: serial@f0000000 { - /* compatible = "ns8250"; Doesn't use FIFOs */ - compatible = "ns16550a"; - reg = <0xf0000000 0x2000>; - interrupt-parent = <&idu_intc>; - /* interrupts = <0 1>; DEST=1*/ - /* interrupts = <0 2>; DEST=2*/ - interrupts = <0 0>; /* RR*/ - clock-frequency = <50000000>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - }; - - arcpct0: pct { - compatible = "snps,archs-pct"; - #interrupt-cells = <1>; - interrupts = <20>; - }; - }; -}; -- cgit v1.2.3