From ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 6 Oct 2017 06:12:41 +0200 Subject: dts: update to v4.14-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm/r8a7745-sk-rzg1e.dts | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'dts/src/arm/r8a7745-sk-rzg1e.dts') diff --git a/dts/src/arm/r8a7745-sk-rzg1e.dts b/dts/src/arm/r8a7745-sk-rzg1e.dts index 97840b3401..b4d679b04a 100644 --- a/dts/src/arm/r8a7745-sk-rzg1e.dts +++ b/dts/src/arm/r8a7745-sk-rzg1e.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for the SK-RZG1E board * - * Copyright (C) 2016 Cogent Embedded, Inc. + * Copyright (C) 2016-2017 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -34,11 +34,34 @@ clock-frequency = <20000000>; }; +&pfc { + scif2_pins: scif2 { + groups = "scif2_data"; + function = "scif2"; + }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; +}; + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; }; ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; renesas,ether-link-active-low; status = "okay"; -- cgit v1.2.3