From f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 9 Mar 2021 14:49:17 +0100 Subject: dts: update to v5.12-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm/sun8i-r40.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'dts/src/arm/sun8i-r40.dtsi') diff --git a/dts/src/arm/sun8i-r40.dtsi b/dts/src/arm/sun8i-r40.dtsi index 7907569e7b..d5ad3b9efd 100644 --- a/dts/src/arm/sun8i-r40.dtsi +++ b/dts/src/arm/sun8i-r40.dtsi @@ -190,6 +190,25 @@ }; }; + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-r40-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + /* + * NOTE: Contrary to what datasheet claims, + * DRAM deinterlace gate doesn't exist and + * it's shared with CSI1. + */ + <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + syscon: system-control@1c00000 { compatible = "allwinner,sun8i-r40-system-control", "allwinner,sun4i-a10-system-control"; -- cgit v1.2.3