From 0ff58575c9d66f660886387c2e68d8c5c724e87b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 3 Feb 2016 10:25:36 +0100 Subject: dts: update to v4.5-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm64/broadcom/ns2.dtsi | 200 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 195 insertions(+), 5 deletions(-) (limited to 'dts/src/arm64/broadcom/ns2.dtsi') diff --git a/dts/src/arm64/broadcom/ns2.dtsi b/dts/src/arm64/broadcom/ns2.dtsi index 3c92d92278..a510d3a8e6 100644 --- a/dts/src/arm64/broadcom/ns2.dtsi +++ b/dts/src/arm64/broadcom/ns2.dtsi @@ -31,6 +31,7 @@ */ #include +#include /memreserve/ 0x84b00000 0x00000008; @@ -44,36 +45,44 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + A57_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 0>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; - cpu@1 { + A57_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 1>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; - cpu@2 { + A57_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 2>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; - cpu@3 { + A57_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 3>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; + }; + + CLUSTER0_L2: l2-cache@000 { + compatible = "cache"; }; }; @@ -89,12 +98,154 @@ IRQ_TYPE_EDGE_RISING)>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&A57_0>, + <&A57_1>, + <&A57_2>, + <&A57_3>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + smmu: mmu@64000000 { + compatible = "arm,mmu-500"; + reg = <0x64000000 0x40000>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + mmu-masters; + }; + + lcpll_ddr: lcpll_ddr@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: lcpll_ports@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: genpll_scr@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: genpll_sw@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; + + crmu: crmu@65024000 { + compatible = "syscon"; + reg = <0x65024000 0x100>; + }; + + reboot@65024000 { + compatible ="syscon-reboot"; + regmap = <&crmu>; + offset = <0x90>; + mask = <0xfffffffd>; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -105,14 +256,53 @@ <0x65260000 0x1000>; }; + i2c0: i2c@66080000 { + compatible = "brcm,iproc-i2c"; + reg = <0x66080000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@660b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x660b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + uart3: serial@66130000 { compatible = "snps,dw-apb-uart"; reg = <0x66130000 0x100>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <23961600>; + clocks = <&osc>; status = "disabled"; }; + + hwrng: hwrng@66220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x66220000 0x28>; + }; + + nand: nand@66460000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x66460000 0x600>, + <0x67015408 0x600>, + <0x66460f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; }; -- cgit v1.2.3