From a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 17 May 2021 13:27:45 +0200 Subject: dts: update to v5.13-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm64/freescale/imx8qm-ss-dma.dtsi | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 dts/src/arm64/freescale/imx8qm-ss-dma.dtsi (limited to 'dts/src/arm64/freescale/imx8qm-ss-dma.dtsi') diff --git a/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi b/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 0000000000..bbe5f5ecfb --- /dev/null +++ b/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +&dma_subsys { + uart4_lpcg: clock-controller@5a4a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_4>; + }; +}; + +&lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart1 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart2 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&lpuart3 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; +}; + +&i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; -- cgit v1.2.3