From ebde8820a04dd73a09f50ba84b8cf8ec3773d6ba Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 6 Oct 2017 06:12:41 +0200 Subject: dts: update to v4.14-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm64/mediatek/mt2712-evb.dts | 32 ++++++ dts/src/arm64/mediatek/mt2712e.dtsi | 171 +++++++++++++++++++++++++++++++++ dts/src/arm64/mediatek/mt6797.dtsi | 12 +-- dts/src/arm64/mediatek/mt7622-rfb1.dts | 27 ++++++ dts/src/arm64/mediatek/mt7622.dtsi | 110 +++++++++++++++++++++ 5 files changed, 345 insertions(+), 7 deletions(-) create mode 100644 dts/src/arm64/mediatek/mt2712-evb.dts create mode 100644 dts/src/arm64/mediatek/mt2712e.dtsi create mode 100644 dts/src/arm64/mediatek/mt7622-rfb1.dts create mode 100644 dts/src/arm64/mediatek/mt7622.dtsi (limited to 'dts/src/arm64/mediatek') diff --git a/dts/src/arm64/mediatek/mt2712-evb.dts b/dts/src/arm64/mediatek/mt2712-evb.dts new file mode 100644 index 0000000000..8c804df3da --- /dev/null +++ b/dts/src/arm64/mediatek/mt2712-evb.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt2712e.dtsi" + +/ { + model = "MediaTek MT2712 evaluation board"; + compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + diff --git a/dts/src/arm64/mediatek/mt2712e.dtsi b/dts/src/arm64/mediatek/mt2712e.dtsi new file mode 100644 index 0000000000..57d0396b7f --- /dev/null +++ b/dts/src/arm64/mediatek/mt2712e.dtsi @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include +#include + +/ { + compatible = "mediatek,mt2712"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x001>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + baud_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + sys_clk: dummyclk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + uart5: serial@1000f000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x1000f000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + sysirq: interrupt-controller@10220a80 { + compatible = "mediatek,mt2712-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10220a80 0 0x40>; + }; + + gic: interrupt-controller@10510000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10510000 0 0x10000>, + <0 0x10520000 0 0x20000>, + <0 0x10540000 0 0x20000>, + <0 0x10560000 0 0x20000>; + interrupts = ; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11019000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11019000 0 0x400>; + interrupts = ; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; +}; + diff --git a/dts/src/arm64/mediatek/mt6797.dtsi b/dts/src/arm64/mediatek/mt6797.dtsi index 31088a9f71..4beaa71107 100644 --- a/dts/src/arm64/mediatek/mt6797.dtsi +++ b/dts/src/arm64/mediatek/mt6797.dtsi @@ -108,13 +108,6 @@ clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "clk32k"; - }; - timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -147,6 +140,11 @@ infracfg = <&infrasys>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + apmixedsys: apmixed@1000c000 { compatible = "mediatek,mt6797-apmixedsys"; reg = <0 0x1000c000 0 0x1000>; diff --git a/dts/src/arm64/mediatek/mt7622-rfb1.dts b/dts/src/arm64/mediatek/mt7622-rfb1.dts new file mode 100644 index 0000000000..c08309df2c --- /dev/null +++ b/dts/src/arm64/mediatek/mt7622-rfb1.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang + * Sean Wang + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7622.dtsi" + +/ { + model = "MediaTek MT7622 RFB1 board"; + compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; + + chosen { + bootargs = "console=ttyS0,115200n1"; + }; + + memory { + reg = <0 0x40000000 0 0x3F000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm64/mediatek/mt7622.dtsi b/dts/src/arm64/mediatek/mt7622.dtsi new file mode 100644 index 0000000000..b111fec2ed --- /dev/null +++ b/dts/src/arm64/mediatek/mt7622.dtsi @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang + * Sean Wang + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include +#include + +/ { + compatible = "mediatek,mt7622"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; + }; + + uart_clk: dummy25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + bus_clk: dummy280m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <280000000>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, + <0 0x10320000 0 0x1000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>, <&bus_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; +}; -- cgit v1.2.3