From 6187b17da4b277417f34fe0b0b90bbaddcbc599e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 9 Aug 2021 21:17:51 +0200 Subject: dts: update to v5.14-rc1 Signed-off-by: Sascha Hauer --- dts/src/arm64/qcom/sm8350.dtsi | 64 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 6 deletions(-) (limited to 'dts/src/arm64/qcom/sm8350.dtsi') diff --git a/dts/src/arm64/qcom/sm8350.dtsi b/dts/src/arm64/qcom/sm8350.dtsi index ed0b51bc03..0d16392bb9 100644 --- a/dts/src/arm64/qcom/sm8350.dtsi +++ b/dts/src/arm64/qcom/sm8350.dtsi @@ -6,11 +6,13 @@ #include #include #include +#include #include #include #include #include #include +#include / { interrupt-parent = <&intc>; @@ -391,6 +393,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; smp2p-slpi { @@ -629,6 +642,45 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sm8350-ipa"; + + iommus = <&apps_smmu 0x5c0 0x0>, + <&apps_smmu 0x5c2 0x0>; + reg = <0 0x1e40000 0 0x8000>, + <0 0x1e50000 0 0x4b20>, + <0 0x1e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_llcc", + "llcc_to_ebi1", + "appss_to_ipa"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -656,7 +708,7 @@ <&rpmhpd 12>; power-domain-names = "load_state", "cx", "mss"; - interconnects = <&mc_virt 0 &mc_virt 1>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; memory-region = <&pil_modem_mem>; @@ -689,7 +741,7 @@ interrupt-controller; }; - tsens0: thermal-sensor@c222000 { + tsens0: thermal-sensor@c263000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ @@ -700,7 +752,7 @@ #thermal-sensor-cells = <1>; }; - tsens1: thermal-sensor@c223000 { + tsens1: thermal-sensor@c265000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ @@ -1063,7 +1115,7 @@ <&rpmhpd 10>; power-domain-names = "load_state", "cx", "mxc"; - interconnects = <&compute_noc 1 &mc_virt 1>; + interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; memory-region = <&pil_cdsp_mem>; @@ -1176,7 +1228,7 @@ }; }; - dc_noc: interconnect@90e0000 { + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8350-dc-noc"; reg = <0 0x090c0000 0 0x4200>; #interconnect-cells = <1>; @@ -1317,7 +1369,7 @@ }; }; - thermal-zones { + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; -- cgit v1.2.3