From 2ab5d62d038d22f343e472a406d113706915f5c1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 11 Jan 2018 16:20:46 +0100 Subject: dts: update to v4.15-rc7 Signed-off-by: Sascha Hauer --- dts/src/arc/axc003.dtsi | 8 ++++++++ dts/src/arc/axc003_idu.dtsi | 8 ++++++++ dts/src/arc/hsdk.dts | 8 ++++++++ dts/src/arm/aspeed-g4.dtsi | 2 +- dts/src/arm/at91-tse850-3.dts | 1 + dts/src/arm/da850-lego-ev3.dts | 4 ++-- dts/src/arm/exynos5800-peach-pi.dts | 4 ++++ dts/src/arm/ls1021a-qds.dts | 2 +- dts/src/arm/ls1021a-twr.dts | 2 +- dts/src/arm/rk3066a-marsboard.dts | 4 ++++ dts/src/arm/rk3288.dtsi | 2 +- dts/src/arm/sun4i-a10.dtsi | 4 ++-- dts/src/arm/sun5i-a10s.dtsi | 4 ++-- dts/src/arm/sun6i-a31.dtsi | 4 ++-- dts/src/arm/sun7i-a20.dtsi | 4 ++-- dts/src/arm/sun8i-a83t-tbs-a711.dts | 1 + dts/src/arm/tango4-common.dtsi | 1 - dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts | 1 + dts/src/arm64/allwinner/sun50i-a64-pine64.dts | 1 + dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts | 3 ++- dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi | 11 +---------- dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 2 +- dts/src/arm64/renesas/salvator-common.dtsi | 1 - dts/src/arm64/renesas/ulcb.dtsi | 1 - dts/src/arm64/rockchip/rk3328-rock64.dts | 2 ++ dts/src/arm64/rockchip/rk3328.dtsi | 2 +- dts/src/arm64/rockchip/rk3399-puma.dtsi | 11 ----------- dts/src/arm64/socionext/uniphier-pxs3.dtsi | 4 ++-- 28 files changed, 59 insertions(+), 43 deletions(-) (limited to 'dts/src') diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi index 4e6e9f57e7..dc91c663bc 100644 --- a/dts/src/arc/axc003.dtsi +++ b/dts/src/arc/axc003.dtsi @@ -35,6 +35,14 @@ reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 90MHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <90000000>; }; core_intc: archs-intc@cpu { diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi index 63954a8b01..69ff4895f2 100644 --- a/dts/src/arc/axc003_idu.dtsi +++ b/dts/src/arc/axc003_idu.dtsi @@ -35,6 +35,14 @@ reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 100MHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <100000000>; }; core_intc: archs-intc@cpu { diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts index 8f627c200d..006aa3de53 100644 --- a/dts/src/arc/hsdk.dts +++ b/dts/src/arc/hsdk.dts @@ -114,6 +114,14 @@ reg = <0x00 0x10>, <0x14B8 0x4>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 1GHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <1000000000>; }; serial: serial@5000 { diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi index 45d815a86d..de08d9045c 100644 --- a/dts/src/arm/aspeed-g4.dtsi +++ b/dts/src/arm/aspeed-g4.dtsi @@ -219,7 +219,7 @@ compatible = "aspeed,ast2400-vuart"; reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <10>; + interrupts = <8>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; diff --git a/dts/src/arm/at91-tse850-3.dts b/dts/src/arm/at91-tse850-3.dts index 5f29010cdb..9b82cc8843 100644 --- a/dts/src/arm/at91-tse850-3.dts +++ b/dts/src/arm/at91-tse850-3.dts @@ -221,6 +221,7 @@ jc42@18 { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x18>; + smbus-timeout-disable; }; dpot: mcp4651-104@28 { diff --git a/dts/src/arm/da850-lego-ev3.dts b/dts/src/arm/da850-lego-ev3.dts index 413dbd5d9f..81942ae83e 100644 --- a/dts/src/arm/da850-lego-ev3.dts +++ b/dts/src/arm/da850-lego-ev3.dts @@ -178,7 +178,7 @@ */ battery { pinctrl-names = "default"; - pintctrl-0 = <&battery_pins>; + pinctrl-0 = <&battery_pins>; compatible = "lego,ev3-battery"; io-channels = <&adc 4>, <&adc 3>; io-channel-names = "voltage", "current"; @@ -392,7 +392,7 @@ batt_volt_en { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; + output-high; }; }; diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts index b2b95ff205..0029ec2781 100644 --- a/dts/src/arm/exynos5800-peach-pi.dts +++ b/dts/src/arm/exynos5800-peach-pi.dts @@ -664,6 +664,10 @@ status = "okay"; }; +&mixer { + status = "okay"; +}; + /* eMMC flash */ &mmc_0 { status = "okay"; diff --git a/dts/src/arm/ls1021a-qds.dts b/dts/src/arm/ls1021a-qds.dts index 940875316d..67b4de0e34 100644 --- a/dts/src/arm/ls1021a-qds.dts +++ b/dts/src/arm/ls1021a-qds.dts @@ -215,7 +215,7 @@ reg = <0x2a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; + clocks = <&sys_mclk>; }; }; }; diff --git a/dts/src/arm/ls1021a-twr.dts b/dts/src/arm/ls1021a-twr.dts index a8b148ad1d..44715c8ef7 100644 --- a/dts/src/arm/ls1021a-twr.dts +++ b/dts/src/arm/ls1021a-twr.dts @@ -187,7 +187,7 @@ reg = <0x0a>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk 1>; + clocks = <&sys_mclk>; }; }; diff --git a/dts/src/arm/rk3066a-marsboard.dts b/dts/src/arm/rk3066a-marsboard.dts index c6d92c25df..d23ee6d911 100644 --- a/dts/src/arm/rk3066a-marsboard.dts +++ b/dts/src/arm/rk3066a-marsboard.dts @@ -83,6 +83,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index cd24894ee5..6102e4e7f3 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -956,7 +956,7 @@ iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "iep_mmu"; #iommu-cells = <0>; status = "disabled"; diff --git a/dts/src/arm/sun4i-a10.dtsi b/dts/src/arm/sun4i-a10.dtsi index b91300d49a..5840f5c75c 100644 --- a/dts/src/arm/sun4i-a10.dtsi +++ b/dts/src/arm/sun4i-a10.dtsi @@ -502,8 +502,8 @@ reg = <0x01c16000 0x1000>; interrupts = <58>; clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 18>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, diff --git a/dts/src/arm/sun5i-a10s.dtsi b/dts/src/arm/sun5i-a10s.dtsi index 6ae4d95e23..316cb8b294 100644 --- a/dts/src/arm/sun5i-a10s.dtsi +++ b/dts/src/arm/sun5i-a10s.dtsi @@ -82,8 +82,8 @@ reg = <0x01c16000 0x1000>; interrupts = <58>; clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 16>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi index 8bfa12b548..72d3fe44ec 100644 --- a/dts/src/arm/sun6i-a31.dtsi +++ b/dts/src/arm/sun6i-a31.dtsi @@ -429,8 +429,8 @@ interrupts = ; clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu 7>, - <&ccu 13>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; resets = <&ccu RST_AHB1_HDMI>; reset-names = "ahb"; diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi index 68dfa82544..59655e42e4 100644 --- a/dts/src/arm/sun7i-a20.dtsi +++ b/dts/src/arm/sun7i-a20.dtsi @@ -581,8 +581,8 @@ reg = <0x01c16000 0x1000>; interrupts = ; clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu 9>, - <&ccu 18>; + <&ccu CLK_PLL_VIDEO0_2X>, + <&ccu CLK_PLL_VIDEO1_2X>; clock-names = "ahb", "mod", "pll-0", "pll-1"; dmas = <&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>, diff --git a/dts/src/arm/sun8i-a83t-tbs-a711.dts b/dts/src/arm/sun8i-a83t-tbs-a711.dts index 9871553893..a021ee6da3 100644 --- a/dts/src/arm/sun8i-a83t-tbs-a711.dts +++ b/dts/src/arm/sun8i-a83t-tbs-a711.dts @@ -146,6 +146,7 @@ status = "okay"; axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; diff --git a/dts/src/arm/tango4-common.dtsi b/dts/src/arm/tango4-common.dtsi index 0ec1b0a317..ff72a8efb7 100644 --- a/dts/src/arm/tango4-common.dtsi +++ b/dts/src/arm/tango4-common.dtsi @@ -156,7 +156,6 @@ reg = <0x6e000 0x400>; ranges = <0 0x6e000 0x400>; interrupt-parent = <&gic>; - interrupt-controller; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts index 45bdbfb961..4a8d3f83a3 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-bananapi-m64.dts @@ -75,6 +75,7 @@ pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; diff --git a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts index 806442d3e8..604cdaedac 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-pine64.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-pine64.dts @@ -77,6 +77,7 @@ pinctrl-0 = <&rmii_pins>; phy-mode = "rmii"; phy-handle = <&ext_rmii_phy1>; + phy-supply = <®_dc1sw>; status = "okay"; }; diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts index 0eb2acedf8..abe179de35 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/dts/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts @@ -82,6 +82,7 @@ pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dc1sw>; status = "okay"; }; @@ -95,7 +96,7 @@ &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; vqmmc-supply = <®_vcc1v8>; bus-width = <8>; non-removable; diff --git a/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi index a5da18a6f2..43418bd881 100644 --- a/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi +++ b/dts/src/arm64/allwinner/sun50i-a64-sopine.dtsi @@ -45,19 +45,10 @@ #include "sun50i-a64.dtsi" -/ { - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; non-removable; disable-wp; bus-width = <4>; diff --git a/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts index b6b7a561df..a42fd79a62 100644 --- a/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/dts/src/arm64/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -71,7 +71,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi index a298df74ca..dbe2648649 100644 --- a/dts/src/arm64/renesas/salvator-common.dtsi +++ b/dts/src/arm64/renesas/salvator-common.dtsi @@ -255,7 +255,6 @@ &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; - renesas,no-ether-link; phy-handle = <&phy0>; status = "okay"; diff --git a/dts/src/arm64/renesas/ulcb.dtsi b/dts/src/arm64/renesas/ulcb.dtsi index 0d85b315ce..73439cf486 100644 --- a/dts/src/arm64/renesas/ulcb.dtsi +++ b/dts/src/arm64/renesas/ulcb.dtsi @@ -145,7 +145,6 @@ &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; - renesas,no-ether-link; phy-handle = <&phy0>; status = "okay"; diff --git a/dts/src/arm64/rockchip/rk3328-rock64.dts b/dts/src/arm64/rockchip/rk3328-rock64.dts index d4f80786e7..3890468678 100644 --- a/dts/src/arm64/rockchip/rk3328-rock64.dts +++ b/dts/src/arm64/rockchip/rk3328-rock64.dts @@ -132,6 +132,8 @@ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; clock_in_out = "input"; + /* shows instability at 1GBit right now */ + max-speed = <100>; phy-supply = <&vcc_io>; phy-mode = "rgmii"; pinctrl-names = "default"; diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi index 41d61840fb..2426da6319 100644 --- a/dts/src/arm64/rockchip/rk3328.dtsi +++ b/dts/src/arm64/rockchip/rk3328.dtsi @@ -514,7 +514,7 @@ tsadc: tsadc@ff250000 { compatible = "rockchip,rk3328-tsadc"; reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; + interrupts = ; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <50000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; diff --git a/dts/src/arm64/rockchip/rk3399-puma.dtsi b/dts/src/arm64/rockchip/rk3399-puma.dtsi index 910628d18a..1fc5060d70 100644 --- a/dts/src/arm64/rockchip/rk3399-puma.dtsi +++ b/dts/src/arm64/rockchip/rk3399-puma.dtsi @@ -155,17 +155,6 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 0>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; }; &cpu_b0 { diff --git a/dts/src/arm64/socionext/uniphier-pxs3.dtsi b/dts/src/arm64/socionext/uniphier-pxs3.dtsi index 48e733136d..0ac2ace824 100644 --- a/dts/src/arm64/socionext/uniphier-pxs3.dtsi +++ b/dts/src/arm64/socionext/uniphier-pxs3.dtsi @@ -198,8 +198,8 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 96 0 0>, - <&pinctrl 160 0 0>; + <&pinctrl 104 0 0>, + <&pinctrl 168 0 0>; gpio-ranges-group-names = "gpio_range0", "gpio_range1", "gpio_range2"; -- cgit v1.2.3