From 87360e3dd42bb627a9f2611f961728c0789e1c21 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 8 Jul 2015 14:44:21 +0200 Subject: dts: update to v4.2-rc1 Signed-off-by: Sascha Hauer --- dts/Bindings/arc/archs-idu-intc.txt | 46 + dts/Bindings/arc/archs-intc.txt | 22 + dts/Bindings/arc/axs101.txt | 7 + dts/Bindings/arc/axs103.txt | 8 + .../arm/altera/socfpga-sdram-controller.txt | 12 + dts/Bindings/arm/altera/socfpga-sdram-edac.txt | 2 +- dts/Bindings/arm/arm-boards | 66 + dts/Bindings/arm/armv7m_systick.txt | 26 + dts/Bindings/arm/atmel-at91.txt | 2 +- dts/Bindings/arm/bcm/brcm,bcm2835.txt | 31 +- dts/Bindings/arm/bcm/brcm,bcm63138.txt | 76 ++ dts/Bindings/arm/cci.txt | 4 +- dts/Bindings/arm/coresight.txt | 12 +- dts/Bindings/arm/cpus.txt | 1 + dts/Bindings/arm/exynos/power_domain.txt | 7 +- dts/Bindings/arm/fsl.txt | 3 + dts/Bindings/arm/hisilicon/hisilicon.txt | 87 ++ dts/Bindings/arm/l2cc.txt | 5 + dts/Bindings/arm/marvell,berlin.txt | 100 +- dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt | 23 + dts/Bindings/arm/mediatek/mediatek,infracfg.txt | 30 + dts/Bindings/arm/mediatek/mediatek,pericfg.txt | 30 + dts/Bindings/arm/mediatek/mediatek,topckgen.txt | 23 + dts/Bindings/arm/scu.txt | 25 + dts/Bindings/arm/ux500/boards.txt | 83 ++ dts/Bindings/arm/zte.txt | 15 + dts/Bindings/ata/ahci-ceva.txt | 20 + dts/Bindings/ata/ahci-platform.txt | 2 + dts/Bindings/ata/brcm,sata-brcmstb.txt | 34 + dts/Bindings/clock/amlogic,meson8b-clkc.txt | 40 + dts/Bindings/clock/bcm-cygnus-clock.txt | 34 - dts/Bindings/clock/brcm,iproc-clocks.txt | 132 ++ dts/Bindings/clock/clock-bindings.txt | 7 +- dts/Bindings/clock/csr,atlas7-car.txt | 55 + dts/Bindings/clock/emev2-clock.txt | 2 +- dts/Bindings/clock/hi6220-clock.txt | 34 + dts/Bindings/clock/imx7d-clock.txt | 13 + dts/Bindings/clock/ingenic,cgu.txt | 53 + dts/Bindings/clock/keystone-pll.txt | 8 +- dts/Bindings/clock/lpc1850-ccu.txt | 77 ++ dts/Bindings/clock/lpc1850-cgu.txt | 131 ++ dts/Bindings/clock/marvell,berlin.txt | 31 + dts/Bindings/clock/marvell,pxa1928.txt | 21 + dts/Bindings/clock/mvebu-gated-clock.txt | 1 + dts/Bindings/clock/nvidia,tegra124-car.txt | 44 +- dts/Bindings/clock/qca,ath79-pll.txt | 33 + dts/Bindings/clock/renesas,cpg-div6-clocks.txt | 6 +- dts/Bindings/clock/renesas,cpg-mstp-clocks.txt | 6 +- dts/Bindings/clock/renesas,h8300-div-clock.txt | 24 + dts/Bindings/clock/renesas,h8s2678-pll-clock.txt | 23 + .../clock/renesas,rcar-gen2-cpg-clocks.txt | 2 +- dts/Bindings/clock/renesas,rz-cpg-clocks.txt | 2 +- dts/Bindings/clock/st,stm32-rcc.txt | 65 + dts/Bindings/clock/sunxi.txt | 1 + dts/Bindings/clock/ti,cdce925.txt | 42 + dts/Bindings/clock/zx296702-clk.txt | 35 + dts/Bindings/crypto/fsl-sec2.txt | 6 +- dts/Bindings/crypto/marvell-cesa.txt | 45 + dts/Bindings/crypto/mv_cesa.txt | 31 +- dts/Bindings/dma/dma.txt | 28 + dts/Bindings/dma/mv-xor.txt | 2 +- dts/Bindings/dma/sirfsoc-dma.txt | 3 +- dts/Bindings/dma/sun6i-dma.txt | 5 +- dts/Bindings/dma/ti-dma-crossbar.txt | 52 + dts/Bindings/drm/msm/dsi.txt | 120 ++ dts/Bindings/drm/msm/edp.txt | 60 + dts/Bindings/drm/msm/hdmi.txt | 6 + dts/Bindings/drm/tilcdc/slave.txt | 18 - dts/Bindings/drm/tilcdc/tilcdc.txt | 27 + dts/Bindings/edac/apm-xgene-edac.txt | 79 ++ dts/Bindings/fuse/nvidia,tegra20-fuse.txt | 2 +- dts/Bindings/gpio/brcm,brcmstb-gpio.txt | 65 + dts/Bindings/gpio/gpio-ath79.txt | 38 + dts/Bindings/gpio/gpio-atlas7.txt | 50 + dts/Bindings/gpio/gpio-etraxfs.txt | 21 + dts/Bindings/gpio/gpio-xlp.txt | 47 + dts/Bindings/gpio/gpio-zynq.txt | 2 +- dts/Bindings/gpio/nxp,lpc1850-gpio.txt | 39 + dts/Bindings/h8300/cpu.txt | 13 + dts/Bindings/hwlock/hwlock.txt | 59 + dts/Bindings/hwlock/omap-hwspinlock.txt | 26 + dts/Bindings/hwlock/qcom-hwspinlock.txt | 39 + dts/Bindings/hwlock/sirf,hwspinlock.txt | 28 + dts/Bindings/hwmon/ntc_thermistor.txt | 1 + dts/Bindings/i2c/i2c-at91.txt | 30 +- dts/Bindings/i2c/i2c-brcmstb.txt | 28 + dts/Bindings/i2c/i2c-mt6577.txt | 41 + dts/Bindings/i2c/i2c-xgene-slimpro.txt | 15 + dts/Bindings/i2c/trivial-devices.txt | 3 +- dts/Bindings/iio/adc/berlin2_adc.txt | 19 + dts/Bindings/iio/adc/ti-adc128s052.txt | 4 +- dts/Bindings/iio/adc/vf610-adc.txt | 9 + dts/Bindings/iio/imu/inv_mpu6050.txt | 17 + dts/Bindings/iio/magnetometer/bmc150_magn.txt | 22 + dts/Bindings/iio/st-sensors.txt | 2 + dts/Bindings/iio/temperature/mlx90614.txt | 24 + dts/Bindings/input/ti,drv2665.txt | 17 + dts/Bindings/input/touchscreen/ti-tsc-adc.txt | 24 + dts/Bindings/interrupt-controller/atmel,aic.txt | 2 +- dts/Bindings/interrupt-controller/ingenic,intc.txt | 28 + .../interrupt-controller/qca,ath79-cpu-intc.txt | 44 + .../interrupt-controller/qca,ath79-misc-intc.txt | 30 + .../interrupt-controller/renesas,h8300h-intc.txt | 22 + .../interrupt-controller/renesas,h8s-intc.txt | 22 + .../interrupt-controller/renesas,intc-irqpin.txt | 39 +- dts/Bindings/iommu/arm,smmu-v3.txt | 37 + dts/Bindings/leds/leds-aat1290.txt | 73 ++ dts/Bindings/leds/leds-bcm6328.txt | 309 +++++ dts/Bindings/leds/leds-bcm6358.txt | 145 +++ dts/Bindings/leds/leds-ktd2692.txt | 50 + dts/Bindings/leds/leds-tlc591xx.txt | 40 + dts/Bindings/mailbox/brcm,bcm2835-mbox.txt | 26 + dts/Bindings/mailbox/mailbox.txt | 10 +- dts/Bindings/media/i2c/adp1653.txt | 37 + dts/Bindings/media/st,stih4xx.txt | 32 + .../memory-controllers/ath79-ddr-controller.txt | 35 + .../memory-controllers/nvidia,tegra-mc.txt | 84 +- .../memory-controllers/renesas,h8300-bsc.txt | 12 + dts/Bindings/memory-controllers/tegra-emc.txt | 374 ++++++ dts/Bindings/mfd/arizona.txt | 19 +- dts/Bindings/mfd/axp20x.txt | 32 +- dts/Bindings/mfd/cros-ec.txt | 4 + dts/Bindings/mfd/da9063.txt | 18 + dts/Bindings/mfd/max77686.txt | 2 +- dts/Bindings/mfd/max77693.txt | 67 + dts/Bindings/mfd/mfd.txt | 41 + dts/Bindings/mfd/tps6507x.txt | 0 dts/Bindings/mips/ath79-soc.txt | 21 + dts/Bindings/misc/nvidia,tegra20-apbmisc.txt | 2 + dts/Bindings/mmc/arasan,sdhci.txt | 3 +- dts/Bindings/mmc/fsl-imx-esdhc.txt | 9 +- dts/Bindings/mmc/k3-dw-mshc.txt | 28 + dts/Bindings/mmc/mmc-pwrseq-simple.txt | 4 +- dts/Bindings/mmc/mmc.txt | 5 + dts/Bindings/mmc/mtk-sd.txt | 32 + dts/Bindings/mmc/renesas,mmcif.txt | 3 + dts/Bindings/mtd/brcm,brcmnand.txt | 150 +++ dts/Bindings/net/amd-xgbe-phy.txt | 48 - dts/Bindings/net/amd-xgbe.txt | 40 +- dts/Bindings/net/ezchip_enet.txt | 15 + dts/Bindings/net/ipq806x-dwmac.txt | 35 + dts/Bindings/net/macb.txt | 6 +- dts/Bindings/net/marvell-armada-370-neta.txt | 2 +- dts/Bindings/net/nfc/nfcmrvl.txt | 29 + dts/Bindings/net/nfc/st-nci.txt | 33 + dts/Bindings/net/nfc/st21nfcb.txt | 33 - dts/Bindings/net/nfc/trf7970a.txt | 4 + dts/Bindings/net/nxp,lpc1850-dwmac.txt | 20 + dts/Bindings/net/phy.txt | 3 + dts/Bindings/net/renesas,ravb.txt | 48 + dts/Bindings/net/rockchip-dwmac.txt | 2 +- dts/Bindings/net/ti,dp83867.txt | 25 + dts/Bindings/panel/hannstar,hsd100pxn1.txt | 7 + dts/Bindings/panel/lg,lb070wv8.txt | 7 + dts/Bindings/pci/xgene-pci-msi.txt | 68 + dts/Bindings/pci/xilinx-pcie.txt | 2 +- dts/Bindings/phy/brcm,brcmstb-sata-phy.txt | 40 + dts/Bindings/phy/pistachio-usb-phy.txt | 29 + dts/Bindings/phy/pxa1928-usb-phy.txt | 18 + dts/Bindings/phy/rcar-gen2-phy.txt | 1 + dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 + dts/Bindings/pinctrl/berlin,pinctrl.txt | 43 + dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt | 27 + dts/Bindings/pinctrl/img,pistachio-pinctrl.txt | 217 ++++ dts/Bindings/pinctrl/lantiq,falcon-pinumx.txt | 83 -- dts/Bindings/pinctrl/lantiq,pinctrl-falcon.txt | 83 ++ dts/Bindings/pinctrl/lantiq,pinctrl-xway.txt | 97 ++ dts/Bindings/pinctrl/lantiq,xway-pinumx.txt | 97 -- .../pinctrl/marvell,armada-370-pinctrl.txt | 18 +- .../pinctrl/marvell,armada-375-pinctrl.txt | 34 +- .../pinctrl/marvell,armada-38x-pinctrl.txt | 66 +- .../pinctrl/marvell,armada-39x-pinctrl.txt | 84 +- dts/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 80 +- dts/Bindings/pinctrl/nxp,lpc1850-scu.txt | 57 + dts/Bindings/pinctrl/pinctrl-atlas7.txt | 109 ++ dts/Bindings/pinctrl/pinctrl-mt65xx.txt | 9 +- dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt | 90 ++ dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt | 4 +- dts/Bindings/pinctrl/rockchip,pinctrl.txt | 5 +- dts/Bindings/pinctrl/xlnx,zynq-pinctrl.txt | 7 +- dts/Bindings/power/bq24257.txt | 21 + dts/Bindings/power/bq25890.txt | 46 + dts/Bindings/power/opp.txt | 448 ++++++- dts/Bindings/power/rt9455_charger.txt | 48 + dts/Bindings/power/twl-charger.txt | 10 + dts/Bindings/power_supply/max17042_battery.txt | 13 + dts/Bindings/powerpc/fsl/fman.txt | 13 + dts/Bindings/powerpc/fsl/guts.txt | 5 + dts/Bindings/regulator/max8973-regulator.txt | 20 +- dts/Bindings/regulator/qcom,spmi-regulator.txt | 121 ++ dts/Bindings/regulator/regulator.txt | 7 +- dts/Bindings/remoteproc/wkup_m3_rproc.txt | 52 + dts/Bindings/reset/berlin,reset.txt | 23 + dts/Bindings/reset/brcm,bcm63138-pmb.txt | 19 + dts/Bindings/rtc/haoyu,hym8563.txt | 2 +- dts/Bindings/rtc/rtc-st-lpc.txt | 25 + dts/Bindings/rtc/s3c-rtc.txt | 3 +- dts/Bindings/serial/arm_sbsa_uart.txt | 10 + dts/Bindings/serial/ingenic,uart.txt | 22 + dts/Bindings/serial/mtk-uart.txt | 12 +- dts/Bindings/serial/nxp,lpc1850-uart.txt | 28 + dts/Bindings/serial/nxp,sc16is7xx.txt | 37 + dts/Bindings/serial/pl011.txt | 2 +- dts/Bindings/serial/renesas,sci-serial.txt | 8 + dts/Bindings/serial/sirf-uart.txt | 15 +- dts/Bindings/serial/uniphier-uart.txt | 23 + dts/Bindings/soc/fsl/qman-portals.txt | 4 +- dts/Bindings/soc/sunxi/sram.txt | 72 ++ dts/Bindings/sound/adi,adau1701.txt | 4 + dts/Bindings/sound/bt-sco.txt | 13 + dts/Bindings/sound/gtm601.txt | 13 + dts/Bindings/sound/max98090.txt | 6 + dts/Bindings/sound/mt8173-max98090.txt | 13 + dts/Bindings/sound/mt8173-rt5650-rt5676.txt | 13 + dts/Bindings/sound/mtk-afe-pcm.txt | 45 + dts/Bindings/sound/qcom,apq8016-sbc.txt | 60 + dts/Bindings/sound/qcom,lpass-cpu.txt | 13 +- dts/Bindings/sound/renesas,rsnd.txt | 3 +- dts/Bindings/sound/rt5645.txt | 72 ++ dts/Bindings/sound/rt5677.txt | 2 + dts/Bindings/sound/simple-card.txt | 6 +- dts/Bindings/sound/tas2552.txt | 6 + dts/Bindings/sound/tas571x.txt | 41 + dts/Bindings/sound/wm8741.txt | 11 + dts/Bindings/sound/zte,zx-i2s.txt | 44 + dts/Bindings/sound/zte,zx-spdif.txt | 28 + dts/Bindings/spi/sh-msiof.txt | 2 +- dts/Bindings/spi/spi-ath79.txt | 24 + dts/Bindings/spi/spi-fsl-dspi.txt | 2 +- dts/Bindings/spi/spi-orion.txt | 8 +- dts/Bindings/spi/spi-sirf.txt | 3 +- dts/Bindings/spi/spi-zynqmp-qspi.txt | 26 + dts/Bindings/spi/spi_atmel.txt | 8 +- dts/Bindings/spi/spi_pl022.txt | 2 +- dts/Bindings/thermal/hisilicon-thermal.txt | 23 + dts/Bindings/thermal/qcom-spmi-temp-alarm.txt | 57 + dts/Bindings/thermal/thermal.txt | 9 + dts/Bindings/timer/cadence,ttc-timer.txt | 4 + dts/Bindings/timer/nxp,lpc3220-timer.txt | 26 + dts/Bindings/timer/renesas,16bit-timer.txt | 25 + dts/Bindings/timer/renesas,8bit-timer.txt | 25 + dts/Bindings/timer/renesas,tpu.txt | 21 + dts/Bindings/timer/st,stm32-timer.txt | 22 + dts/Bindings/usb/atmel-usb.txt | 31 +- dts/Bindings/usb/ci-hdrc-imx.txt | 35 - dts/Bindings/usb/ci-hdrc-qcom.txt | 17 - dts/Bindings/usb/ci-hdrc-usb2.txt | 22 +- dts/Bindings/usb/ci-hdrc-zevio.txt | 17 - dts/Bindings/usb/dwc3-st.txt | 7 +- dts/Bindings/usb/dwc3.txt | 2 + dts/Bindings/usb/msm-hsusb.txt | 11 + dts/Bindings/usb/renesas_usbhs.txt | 1 + dts/Bindings/usb/twlxxxx-usb.txt | 3 + dts/Bindings/usb/usb-ehci.txt | 2 + dts/Bindings/vendor-prefixes.txt | 18 + dts/Bindings/video/exynos-mic.txt | 51 + dts/Bindings/video/exynos5433-decon.txt | 65 + dts/Bindings/video/exynos_dsim.txt | 31 +- dts/Bindings/video/ssd1307fb.txt | 23 +- dts/Bindings/watchdog/digicolor-wdt.txt | 25 + dts/Bindings/watchdog/omap-wdt.txt | 9 +- dts/Bindings/watchdog/st_lpc_wdt.txt | 38 + dts/include/dt-bindings/clock/bcm-cygnus.h | 68 + dts/include/dt-bindings/clock/hi6220-clock.h | 173 +++ dts/include/dt-bindings/clock/imx7d-clock.h | 450 +++++++ dts/include/dt-bindings/clock/jz4740-cgu.h | 37 + dts/include/dt-bindings/clock/jz4780-cgu.h | 88 ++ dts/include/dt-bindings/clock/lpc18xx-ccu.h | 74 ++ dts/include/dt-bindings/clock/lpc18xx-cgu.h | 41 + dts/include/dt-bindings/clock/marvell,mmp2.h | 1 + dts/include/dt-bindings/clock/marvell,pxa168.h | 3 + dts/include/dt-bindings/clock/marvell,pxa1928.h | 57 + dts/include/dt-bindings/clock/marvell,pxa910.h | 4 + dts/include/dt-bindings/clock/meson8b-clkc.h | 25 + dts/include/dt-bindings/clock/mt8135-clk.h | 194 +++ dts/include/dt-bindings/clock/mt8173-clk.h | 235 ++++ dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h | 2 + dts/include/dt-bindings/clock/r8a73a4-clock.h | 1 + dts/include/dt-bindings/clock/r8a7790-clock.h | 3 + dts/include/dt-bindings/clock/r8a7791-clock.h | 3 + dts/include/dt-bindings/clock/r8a7794-clock.h | 3 + dts/include/dt-bindings/clock/samsung,s2mps11.h | 23 + dts/include/dt-bindings/clock/vf610-clock.h | 3 +- dts/include/dt-bindings/clock/zx296702-clock.h | 170 +++ dts/include/dt-bindings/mfd/arizona.h | 18 + dts/include/dt-bindings/mfd/st-lpc.h | 15 + dts/include/dt-bindings/net/ti-dp83867.h | 45 + dts/include/dt-bindings/phy/phy-pistachio-usb.h | 16 + dts/include/dt-bindings/pinctrl/am43xx.h | 1 + dts/include/dt-bindings/pinctrl/bcm2835.h | 27 + dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h | 256 ++++ .../dt-bindings/reset-controller/mt8135-resets.h | 64 + .../dt-bindings/reset-controller/mt8173-resets.h | 63 + dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43 + dts/include/dt-bindings/sound/apq8016-lpass.h | 9 + dts/include/dt-bindings/sound/audio-jack-events.h | 9 + dts/include/dt-bindings/sound/tas2552.h | 18 + dts/src/arc/angel4.dts | 70 - dts/src/arc/axc001.dtsi | 100 ++ dts/src/arc/axc003.dtsi | 102 ++ dts/src/arc/axc003_idu.dtsi | 126 ++ dts/src/arc/axs101.dts | 21 + dts/src/arc/axs103.dts | 24 + dts/src/arc/axs103_idu.dts | 24 + dts/src/arc/axs10x_mb.dtsi | 224 ++++ dts/src/arc/nsim_700.dts | 70 + dts/src/arc/nsim_hs.dts | 53 + dts/src/arc/nsim_hs_idu.dts | 72 ++ dts/src/arc/nsimosci_hs.dts | 80 ++ dts/src/arc/nsimosci_hs_idu.dts | 101 ++ dts/src/arc/vdk_axc003.dtsi | 61 + dts/src/arc/vdk_axc003_idu.dtsi | 76 ++ dts/src/arc/vdk_axs10x_mb.dtsi | 93 ++ dts/src/arc/vdk_hs38.dts | 21 + dts/src/arc/vdk_hs38_smp.dts | 21 + dts/src/arm/am335x-baltos-ir5221.dts | 532 ++++++++ dts/src/arm/am335x-bone-common.dtsi | 66 + dts/src/arm/am335x-evm.dts | 81 ++ dts/src/arm/am335x-sl50.dts | 482 +++++++ dts/src/arm/am3517.dtsi | 11 + dts/src/arm/am437x-gp-evm.dts | 144 ++- dts/src/arm/am57xx-beagle-x15.dts | 81 ++ dts/src/arm/arm-realview-pb1176.dts | 2 +- dts/src/arm/armada-370-db.dts | 2 +- dts/src/arm/armada-370-dlink-dns327l.dts | 357 ++++++ dts/src/arm/armada-370-synology-ds213j.dts | 2 +- dts/src/arm/armada-370-xp.dtsi | 4 - dts/src/arm/armada-370.dtsi | 12 + dts/src/arm/armada-375-db.dts | 2 +- dts/src/arm/armada-375.dtsi | 6 +- dts/src/arm/armada-385-db-ap.dts | 2 +- dts/src/arm/armada-385-linksys-caiman.dts | 114 ++ dts/src/arm/armada-385-linksys-cobra.dts | 114 ++ dts/src/arm/armada-385-linksys.dtsi | 332 +++++ dts/src/arm/armada-388-db.dts | 2 +- dts/src/arm/armada-388-gp.dts | 2 +- dts/src/arm/armada-388-rd.dts | 2 +- dts/src/arm/armada-38x.dtsi | 8 +- dts/src/arm/armada-398-db.dts | 2 +- dts/src/arm/armada-39x.dtsi | 6 +- dts/src/arm/armada-xp-axpwifiap.dts | 2 +- dts/src/arm/armada-xp-db.dts | 2 +- dts/src/arm/armada-xp-gp.dts | 2 +- dts/src/arm/armada-xp-mv78260.dtsi | 2 +- dts/src/arm/armada-xp-mv78460.dtsi | 2 +- dts/src/arm/armada-xp-synology-ds414.dts | 2 +- dts/src/arm/armada-xp.dtsi | 20 +- dts/src/arm/armv7-m.dtsi | 6 + dts/src/arm/at91-ariettag25.dts | 79 ++ dts/src/arm/at91-kizbox.dts | 159 +++ dts/src/arm/at91-kizbox2.dts | 216 ++++ dts/src/arm/at91-kizboxmini.dts | 129 ++ dts/src/arm/at91-sama5d3_xplained.dts | 35 +- dts/src/arm/at91-sama5d4_xplained.dts | 28 +- dts/src/arm/at91-sama5d4ek.dts | 7 +- dts/src/arm/at91rm9200.dtsi | 6 +- dts/src/arm/at91rm9200ek.dts | 4 + dts/src/arm/at91sam9260.dtsi | 4 +- dts/src/arm/at91sam9261.dtsi | 4 +- dts/src/arm/at91sam9261ek.dts | 3 +- dts/src/arm/at91sam9263.dtsi | 4 +- dts/src/arm/at91sam9263ek.dts | 3 +- dts/src/arm/at91sam9g20ek_common.dtsi | 3 +- dts/src/arm/at91sam9g45.dtsi | 10 +- dts/src/arm/at91sam9m10g45ek.dts | 3 +- dts/src/arm/at91sam9n12.dtsi | 5 +- dts/src/arm/at91sam9n12ek.dts | 3 +- dts/src/arm/at91sam9rl.dtsi | 15 +- dts/src/arm/at91sam9rlek.dts | 11 +- dts/src/arm/at91sam9x5.dtsi | 58 +- dts/src/arm/at91sam9x5ek.dtsi | 3 +- dts/src/arm/atlas7.dtsi | 15 + dts/src/arm/axp209.dtsi | 5 - dts/src/arm/bcm-cygnus.dtsi | 12 + dts/src/arm/bcm2835-rpi-b-plus.dts | 4 +- dts/src/arm/bcm2835-rpi-b.dts | 4 +- dts/src/arm/bcm2835-rpi.dtsi | 8 +- dts/src/arm/bcm2835.dtsi | 13 +- dts/src/arm/bcm4708-asus-rt-ac56u.dts | 97 ++ dts/src/arm/bcm4708-asus-rt-ac68u.dts | 84 ++ dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts | 7 + dts/src/arm/bcm4708-luxul-xwc-1000.dts | 9 +- dts/src/arm/bcm4708-netgear-r6250.dts | 1 + dts/src/arm/bcm4708-netgear-r6300-v2.dts | 1 + dts/src/arm/bcm4708-smartrg-sr400ac.dts | 120 ++ dts/src/arm/bcm47081-asus-rt-n18u.dts | 1 + dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts | 1 + dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts | 1 + dts/src/arm/bcm4709-asus-rt-ac87u.dts | 65 + dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts | 128 ++ dts/src/arm/bcm4709-netgear-r8000.dts | 1 + dts/src/arm/bcm5301x-nand-cs0-bch8.dtsi | 24 + dts/src/arm/bcm5301x.dtsi | 36 + dts/src/arm/bcm63138.dtsi | 43 + dts/src/arm/bcm7445-bcm97445svmb.dts | 23 + dts/src/arm/bcm7445.dtsi | 59 + dts/src/arm/bcm958300k.dts | 16 + dts/src/arm/bcm963138dvt.dts | 12 + dts/src/arm/berlin2-sony-nsz-gs7.dts | 34 +- dts/src/arm/berlin2.dtsi | 124 +- dts/src/arm/berlin2cd-google-chromecast.dts | 34 +- dts/src/arm/berlin2cd.dtsi | 100 +- dts/src/arm/berlin2q-marvell-dmp.dts | 34 +- dts/src/arm/berlin2q.dtsi | 154 ++- dts/src/arm/cx92755.dtsi | 17 + dts/src/arm/cx92755_equinox.dts | 4 + dts/src/arm/dove-cm-a510.dts | 38 - dts/src/arm/dove-cm-a510.dtsi | 195 +++ dts/src/arm/dove-sbc-a510.dts | 182 +++ dts/src/arm/dove.dtsi | 40 +- dts/src/arm/dra7.dtsi | 43 + dts/src/arm/dra72-evm.dts | 110 ++ dts/src/arm/dra72x.dtsi | 11 + dts/src/arm/dra74x.dtsi | 15 + dts/src/arm/dra7xx-clocks.dtsi | 11 + dts/src/arm/emev2-kzm9d.dts | 4 +- dts/src/arm/exynos3250-monk.dts | 3 +- dts/src/arm/exynos3250-rinato.dts | 7 +- dts/src/arm/exynos3250.dtsi | 48 +- dts/src/arm/exynos4.dtsi | 152 ++- dts/src/arm/exynos4210-origen.dts | 418 +++--- dts/src/arm/exynos4210-smdkv310.dts | 280 ++-- dts/src/arm/exynos4210-trats.dts | 592 ++++----- dts/src/arm/exynos4210.dtsi | 72 +- dts/src/arm/exynos4212.dtsi | 12 +- dts/src/arm/exynos4412-odroid-common.dtsi | 732 +++++------ dts/src/arm/exynos4412-odroidx.dts | 16 +- dts/src/arm/exynos4412-origen.dts | 892 ++++++------- dts/src/arm/exynos4412-smdk4412.dts | 210 +-- dts/src/arm/exynos4412-tiny4412.dts | 54 +- dts/src/arm/exynos4412-trats2.dts | 1339 ++++++++++---------- dts/src/arm/exynos4412.dtsi | 20 +- dts/src/arm/exynos4415.dtsi | 15 +- dts/src/arm/exynos4x12-pinctrl.dtsi | 8 +- dts/src/arm/exynos4x12.dtsi | 290 +++-- dts/src/arm/exynos5.dtsi | 6 +- dts/src/arm/exynos5250-smdk5250.dts | 12 + dts/src/arm/exynos5250-snow.dts | 46 +- dts/src/arm/exynos5250.dtsi | 332 ++++- dts/src/arm/exynos5260-xyref5260.dts | 2 +- dts/src/arm/exynos5420-arndale-octa.dts | 652 +++++----- dts/src/arm/exynos5420-peach-pit.dts | 2 +- dts/src/arm/exynos5420-smdk5420.dts | 645 +++++----- dts/src/arm/exynos5420.dtsi | 305 ++++- dts/src/arm/exynos5422-odroidxu3-common.dtsi | 479 +++++++ dts/src/arm/exynos5422-odroidxu3-lite.dts | 20 + dts/src/arm/exynos5422-odroidxu3.dts | 339 +---- dts/src/arm/exynos5440-sd5v1.dts | 10 +- dts/src/arm/exynos5440-ssdk5440.dts | 85 +- dts/src/arm/exynos5440.dtsi | 4 +- dts/src/arm/exynos5800-peach-pi.dts | 2 +- dts/src/arm/imx23-olinuxino.dts | 6 + dts/src/arm/imx23.dtsi | 40 +- dts/src/arm/imx28-cfa10036.dts | 3 + dts/src/arm/imx6dl-apf6dev.dts | 60 + dts/src/arm/imx6dl-aristainetos2_4.dts | 159 +++ dts/src/arm/imx6dl-aristainetos2_7.dts | 97 ++ dts/src/arm/imx6dl-cubox-i.dts | 5 +- dts/src/arm/imx6dl-gw551x.dts | 55 + dts/src/arm/imx6dl-hummingboard.dts | 5 +- dts/src/arm/imx6dl.dtsi | 4 + dts/src/arm/imx6q-apf6dev.dts | 64 + dts/src/arm/imx6q-cubox-i.dts | 5 +- dts/src/arm/imx6q-gw551x.dts | 55 + dts/src/arm/imx6q-hummingboard.dts | 5 +- dts/src/arm/imx6qdl-apf6.dtsi | 158 +++ dts/src/arm/imx6qdl-apf6dev.dtsi | 479 +++++++ dts/src/arm/imx6qdl-aristainetos2.dtsi | 633 +++++++++ dts/src/arm/imx6qdl-cubox-i.dtsi | 5 +- dts/src/arm/imx6qdl-gw551x.dtsi | 314 +++++ dts/src/arm/imx6qdl-hummingboard.dtsi | 19 +- dts/src/arm/imx6qdl-microsom-ar8035.dtsi | 5 +- dts/src/arm/imx6qdl-microsom.dtsi | 108 +- dts/src/arm/imx6qdl-nitrogen6x.dtsi | 30 +- dts/src/arm/imx6qdl-sabrelite.dtsi | 30 +- dts/src/arm/imx6qdl.dtsi | 57 +- dts/src/arm/imx6sl-warp.dts | 39 +- dts/src/arm/imx7d-pinfunc.h | 1038 +++++++++++++++ dts/src/arm/imx7d-sdb.dts | 408 ++++++ dts/src/arm/imx7d.dtsi | 486 +++++++ dts/src/arm/integrator.dtsi | 4 +- dts/src/arm/k2e-evm.dts | 1 + dts/src/arm/k2e-netcp.dtsi | 206 +++ dts/src/arm/k2e.dtsi | 1 + dts/src/arm/k2hk-evm.dts | 1 + dts/src/arm/k2hk-netcp.dtsi | 208 +++ dts/src/arm/k2hk.dtsi | 1 + dts/src/arm/k2l-evm.dts | 1 + dts/src/arm/k2l-netcp.dtsi | 189 +++ dts/src/arm/k2l.dtsi | 1 + dts/src/arm/kirkwood-b3.dts | 2 +- dts/src/arm/kirkwood-cloudbox.dts | 2 +- dts/src/arm/kirkwood-dir665.dts | 2 +- dts/src/arm/kirkwood-dreamplug.dts | 2 +- dts/src/arm/kirkwood-lsxl.dtsi | 2 +- dts/src/arm/kirkwood-mv88f6281gtw-ge.dts | 2 +- dts/src/arm/kirkwood-netxbig.dtsi | 2 +- dts/src/arm/kirkwood-ns2-common.dtsi | 2 +- dts/src/arm/kirkwood-rd88f6192.dts | 2 +- dts/src/arm/kirkwood-synology.dtsi | 2 +- dts/src/arm/kirkwood-t5325.dts | 2 +- dts/src/arm/kirkwood-ts219.dtsi | 2 +- dts/src/arm/kizbox.dts | 150 --- dts/src/arm/logicpd-torpedo-37xx-devkit.dts | 157 +++ dts/src/arm/logicpd-torpedo-som.dtsi | 162 +++ dts/src/arm/lpc18xx.dtsi | 114 ++ dts/src/arm/lpc4350-hitex-eval.dts | 45 + dts/src/arm/lpc4350.dtsi | 39 + dts/src/arm/lpc4357-ea4357-devkit.dts | 41 + dts/src/arm/lpc4357.dtsi | 39 + dts/src/arm/mt8127.dtsi | 8 +- dts/src/arm/mt8135-pinfunc.h | 1302 +++++++++++++++++++ dts/src/arm/mt8135.dtsi | 29 + dts/src/arm/omap3-cm-t3517.dts | 2 +- dts/src/arm/omap3-devkit8000.dts | 41 + dts/src/arm/omap3-evm-common.dtsi | 1 + dts/src/arm/omap3-gta04.dtsi | 37 + dts/src/arm/omap3-ldp.dts | 18 +- dts/src/arm/omap5-uevm.dts | 14 +- dts/src/arm/pxa27x.dtsi | 46 +- dts/src/arm/pxa2xx.dtsi | 7 +- dts/src/arm/pxa3xx.dtsi | 29 +- dts/src/arm/qcom-apq8064-cm-qs600.dts | 100 ++ dts/src/arm/qcom-apq8064-ifc6410.dts | 136 +- dts/src/arm/qcom-apq8064.dtsi | 175 ++- dts/src/arm/qcom-msm8660.dtsi | 5 + dts/src/arm/qcom-pm8841.dtsi | 18 + dts/src/arm/qcom-pm8941.dtsi | 133 +- dts/src/arm/qcom-pma8084.dtsi | 92 ++ dts/src/arm/r8a73a4-ape6evm.dts | 2 +- dts/src/arm/r8a73a4.dtsi | 11 +- dts/src/arm/r8a7740-armadillo800eva.dts | 2 +- dts/src/arm/r8a7740.dtsi | 10 +- dts/src/arm/r8a7778-bockw-reference.dts | 2 +- dts/src/arm/r8a7778-bockw.dts | 4 +- dts/src/arm/r8a7778.dtsi | 2 +- dts/src/arm/r8a7779-marzen.dts | 6 +- dts/src/arm/r8a7779.dtsi | 2 +- dts/src/arm/r8a7790-lager.dts | 4 +- dts/src/arm/r8a7790.dtsi | 66 +- dts/src/arm/r8a7791-henninger.dts | 2 +- dts/src/arm/r8a7791-koelsch.dts | 4 +- dts/src/arm/r8a7791.dtsi | 79 +- dts/src/arm/r8a7794.dtsi | 45 + dts/src/arm/rk3066a-bqcurie2.dts | 44 +- dts/src/arm/rk3066a.dtsi | 44 +- dts/src/arm/rk3188-radxarock.dts | 45 +- dts/src/arm/rk3188.dtsi | 44 +- dts/src/arm/rk3288-evb-act8846.dts | 44 +- dts/src/arm/rk3288-evb-rk808.dts | 44 +- dts/src/arm/rk3288-evb.dtsi | 67 +- dts/src/arm/rk3288-firefly.dtsi | 14 + dts/src/arm/rk3288-popmetal.dts | 6 + dts/src/arm/rk3288-thermal.dtsi | 40 +- dts/src/arm/rk3288.dtsi | 58 +- dts/src/arm/rk3xxx.dtsi | 44 +- dts/src/arm/s3c2416-smdk2416.dts | 86 +- dts/src/arm/s3c2416.dtsi | 18 +- dts/src/arm/sama5d3.dtsi | 13 +- dts/src/arm/sama5d3xcm.dtsi | 9 +- dts/src/arm/sama5d4.dtsi | 220 +++- dts/src/arm/sh73a0-kzm9g.dts | 1 + dts/src/arm/sh73a0.dtsi | 10 +- dts/src/arm/socfpga.dtsi | 20 +- dts/src/arm/socfpga_arria10.dtsi | 363 +++++- dts/src/arm/socfpga_arria10_socdk.dts | 48 - dts/src/arm/socfpga_arria10_socdk.dtsi | 74 ++ dts/src/arm/socfpga_arria10_socdk_sdmmc.dts | 26 + dts/src/arm/socfpga_cyclone5_sockit.dts | 16 + dts/src/arm/socfpga_cyclone5_socrates.dts | 31 + dts/src/arm/ste-dbx5x0.dtsi | 175 +++ dts/src/arm/ste-href-stuib.dtsi | 50 + dts/src/arm/ste-href-tvk1281618.dtsi | 7 +- dts/src/arm/ste-nomadik-stn8815.dtsi | 5 +- dts/src/arm/ste-snowball.dts | 23 +- dts/src/arm/stih407-b2120.dts | 2 +- dts/src/arm/stih407-family.dtsi | 231 +++- dts/src/arm/stih407-pinctrl.dtsi | 2 + dts/src/arm/stih407.dtsi | 28 + dts/src/arm/stih410-b2120.dts | 10 + dts/src/arm/stih416-b2020e.dts | 10 + dts/src/arm/stih416-pinctrl.dtsi | 50 + dts/src/arm/stih416.dtsi | 66 +- dts/src/arm/stih418-b2199.dts | 27 + dts/src/arm/stihxxx-b2120.dtsi | 13 + dts/src/arm/stm32f429-disco.dts | 71 ++ dts/src/arm/stm32f429.dtsi | 214 ++++ dts/src/arm/sun4i-a10-a1000.dts | 211 +-- dts/src/arm/sun4i-a10-ba10-tvbox.dts | 185 +-- dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts | 40 +- dts/src/arm/sun4i-a10-cubieboard.dts | 226 ++-- dts/src/arm/sun4i-a10-gemei-g9.dts | 171 +++ dts/src/arm/sun4i-a10-hackberry.dts | 200 ++- dts/src/arm/sun4i-a10-hyundai-a7hd.dts | 13 +- dts/src/arm/sun4i-a10-inet97fv2.dts | 123 +- dts/src/arm/sun4i-a10-jesurun-q5.dts | 193 +++ dts/src/arm/sun4i-a10-marsboard.dts | 20 +- dts/src/arm/sun4i-a10-mini-xplus.dts | 149 ++- dts/src/arm/sun4i-a10-mk802.dts | 13 +- dts/src/arm/sun4i-a10-mk802ii.dts | 13 +- dts/src/arm/sun4i-a10-olinuxino-lime.dts | 228 ++-- dts/src/arm/sun4i-a10-pcduino.dts | 189 +-- dts/src/arm/sun4i-a10.dtsi | 166 ++- dts/src/arm/sun5i-a10s-auxtek-t004.dts | 154 +++ dts/src/arm/sun5i-a10s-mk802.dts | 13 +- dts/src/arm/sun5i-a10s-olinuxino-micro.dts | 328 ++--- dts/src/arm/sun5i-a10s-r7-tv-dongle.dts | 139 +- dts/src/arm/sun5i-a10s.dtsi | 651 ++-------- dts/src/arm/sun5i-a13-hsg-h702.dts | 143 +-- dts/src/arm/sun5i-a13-olinuxino-micro.dts | 155 ++- dts/src/arm/sun5i-a13-olinuxino.dts | 245 ++-- dts/src/arm/sun5i-a13-utoo-p66.dts | 226 ++++ dts/src/arm/sun5i-a13.dtsi | 608 ++------- dts/src/arm/sun5i.dtsi | 609 +++++++++ dts/src/arm/sun6i-a31-app4-evb1.dts | 63 +- dts/src/arm/sun6i-a31-colombus.dts | 145 ++- dts/src/arm/sun6i-a31-hummingbird.dts | 108 +- dts/src/arm/sun6i-a31-i7.dts | 149 +++ dts/src/arm/sun6i-a31-m9.dts | 161 ++- dts/src/arm/sun6i-a31-mele-a1000g-quad.dts | 149 +++ dts/src/arm/sun6i-a31.dtsi | 133 +- dts/src/arm/sun6i-a31s-cs908.dts | 48 +- dts/src/arm/sun6i-a31s.dtsi | 5 - dts/src/arm/sun7i-a20-bananapi.dts | 271 ++-- dts/src/arm/sun7i-a20-bananapro.dts | 25 +- dts/src/arm/sun7i-a20-cubieboard2.dts | 205 +-- dts/src/arm/sun7i-a20-cubietruck.dts | 331 ++--- dts/src/arm/sun7i-a20-hummingbird.dts | 426 ++++--- dts/src/arm/sun7i-a20-i12-tvbox.dts | 267 ++-- dts/src/arm/sun7i-a20-m3.dts | 191 +-- dts/src/arm/sun7i-a20-mk808c.dts | 148 +++ dts/src/arm/sun7i-a20-olinuxino-lime.dts | 197 +-- dts/src/arm/sun7i-a20-olinuxino-lime2.dts | 301 ++--- dts/src/arm/sun7i-a20-olinuxino-micro.dts | 411 +++--- dts/src/arm/sun7i-a20-orangepi-mini.dts | 250 ++++ dts/src/arm/sun7i-a20-orangepi.dts | 228 ++++ dts/src/arm/sun7i-a20-pcduino3-nano.dts | 194 +++ dts/src/arm/sun7i-a20-pcduino3.dts | 217 ++-- dts/src/arm/sun7i-a20-wexler-tab7200.dts | 183 +++ dts/src/arm/sun7i-a20.dtsi | 196 ++- dts/src/arm/sun8i-a23-a33.dtsi | 636 ++++++++++ dts/src/arm/sun8i-a23-evb.dts | 134 ++ dts/src/arm/sun8i-a23-ippo-q8h-v1.2.dts | 5 - dts/src/arm/sun8i-a23-ippo-q8h-v5.dts | 117 +- dts/src/arm/sun8i-a23.dtsi | 557 +------- dts/src/arm/sun8i-a33-et-q8-v1.6.dts | 88 ++ dts/src/arm/sun8i-a33-ga10h-v1.1.dts | 125 ++ dts/src/arm/sun8i-a33-sinlinx-sina33.dts | 129 ++ dts/src/arm/sun8i-a33.dtsi | 97 ++ dts/src/arm/sun9i-a80-cubieboard4.dts | 99 ++ dts/src/arm/sun9i-a80-optimus.dts | 72 +- dts/src/arm/sun9i-a80.dtsi | 145 ++- dts/src/arm/sunxi-common-regulators.dtsi | 5 - dts/src/arm/tegra124-jetson-tk1.dts | 4 + dts/src/arm/tegra124-venice2.dts | 3 + dts/src/arm/tegra124.dtsi | 6 +- dts/src/arm/tegra20-seaboard.dts | 12 + dts/src/arm/tegra20.dtsi | 2 +- dts/src/arm/tegra30-cardhu.dtsi | 30 +- dts/src/arm/tegra30.dtsi | 15 + dts/src/arm/uniphier-ph1-ld4-ref.dts | 79 ++ dts/src/arm/uniphier-ph1-ld4.dtsi | 110 ++ dts/src/arm/uniphier-ph1-pro4-ref.dts | 79 ++ dts/src/arm/uniphier-ph1-pro4.dtsi | 117 ++ dts/src/arm/uniphier-ph1-sld3-ref.dts | 80 ++ dts/src/arm/uniphier-ph1-sld3.dtsi | 117 ++ dts/src/arm/uniphier-ph1-sld8-ref.dts | 79 ++ dts/src/arm/uniphier-ph1-sld8.dtsi | 110 ++ dts/src/arm/uniphier-support-card.dtsi | 65 + dts/src/arm/vf-colibri.dtsi | 2 +- dts/src/arm/vf610-cosmic.dts | 2 +- dts/src/arm/vf610-pinfunc.h | 2 +- dts/src/arm/vf610-twr.dts | 2 +- dts/src/arm/vf610m4-colibri.dts | 99 ++ dts/src/arm/vf610m4.dtsi | 50 + dts/src/arm/zx296702-ad1.dts | 48 + dts/src/arm/zx296702.dtsi | 139 ++ dts/src/arm/zynq-7000.dtsi | 4 +- dts/src/arm/zynq-parallella.dts | 9 +- dts/src/arm/zynq-zc702.dts | 3 +- dts/src/arm/zynq-zc706.dts | 3 +- dts/src/arm/zynq-zed.dts | 3 +- dts/src/arm/zynq-zybo.dts | 8 +- dts/src/arm64/apm/apm-storm.dtsi | 123 ++ dts/src/arm64/arm/juno-base.dtsi | 154 +++ dts/src/arm64/arm/juno-clocks.dtsi | 4 +- dts/src/arm64/arm/juno-motherboard.dtsi | 129 ++ dts/src/arm64/arm/juno-r1.dts | 116 ++ dts/src/arm64/arm/juno.dts | 129 +- dts/src/arm64/hisilicon/hi6220-hikey.dts | 31 + dts/src/arm64/hisilicon/hi6220.dtsi | 171 +++ dts/src/arm64/mediatek/mt8173.dtsi | 41 +- dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi | 30 + dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi | 21 + dts/src/arm64/qcom/apq8016-sbc.dtsi | 3 + dts/src/arm64/qcom/msm8916-mtp.dtsi | 1 + dts/src/arm64/qcom/msm8916.dtsi | 25 +- dts/src/arm64/qcom/pm8916.dtsi | 99 ++ dts/src/arm64/skeleton.dtsi | 13 - dts/src/h8300/edosk2674.dts | 107 ++ dts/src/h8300/h8300h_sim.dts | 96 ++ dts/src/h8300/h8s_sim.dts | 99 ++ dts/src/mips/brcm/bcm7346.dtsi | 26 + dts/src/mips/brcm/bcm7358.dtsi | 26 + dts/src/mips/brcm/bcm7360.dtsi | 26 + dts/src/mips/brcm/bcm7362.dtsi | 26 + dts/src/mips/brcm/bcm7435.dtsi | 239 ++++ dts/src/mips/brcm/bcm97346dbsmb.dts | 8 + dts/src/mips/brcm/bcm97358svmb.dts | 8 + dts/src/mips/brcm/bcm97360svmb.dts | 8 + dts/src/mips/brcm/bcm97362svmb.dts | 8 + dts/src/mips/brcm/bcm97435svmb.dts | 60 + dts/src/mips/ingenic/ci20.dts | 44 + dts/src/mips/ingenic/jz4740.dtsi | 68 + dts/src/mips/ingenic/jz4780.dtsi | 111 ++ dts/src/mips/ingenic/qi_lb60.dts | 15 + dts/src/mips/mti/malta.dts | 7 + dts/src/mips/qca/ar9132.dtsi | 133 ++ dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts | 112 ++ dts/src/powerpc/b4qds.dtsi | 12 + dts/src/powerpc/fsl/b4420si-post.dtsi | 15 +- dts/src/powerpc/fsl/b4860si-post.dtsi | 84 +- dts/src/powerpc/fsl/b4si-post.dtsi | 118 ++ dts/src/powerpc/fsl/p1023si-post.dtsi | 43 + dts/src/powerpc/fsl/p2041si-post.dtsi | 14 + dts/src/powerpc/fsl/p3041si-post.dtsi | 14 + dts/src/powerpc/fsl/p4080si-post.dtsi | 14 + dts/src/powerpc/fsl/p5020si-post.dtsi | 14 + dts/src/powerpc/fsl/p5040si-post.dtsi | 14 + dts/src/powerpc/fsl/qoriq-qman1-portals.dtsi | 20 +- dts/src/powerpc/fsl/t1023si-post.dtsi | 330 +++++ dts/src/powerpc/fsl/t1024si-post.dtsi | 100 ++ dts/src/powerpc/fsl/t102xsi-pre.dtsi | 87 ++ dts/src/powerpc/fsl/t1040si-post.dtsi | 78 ++ dts/src/powerpc/fsl/t2081si-post.dtsi | 130 +- dts/src/powerpc/fsl/t4240si-post.dtsi | 318 +++++ dts/src/powerpc/kmcoge4.dts | 12 + dts/src/powerpc/oca4080.dts | 12 + dts/src/powerpc/p1023rdb.dts | 12 + dts/src/powerpc/p2041rdb.dts | 12 + dts/src/powerpc/p3041ds.dts | 12 + dts/src/powerpc/p4080ds.dts | 12 + dts/src/powerpc/p5020ds.dts | 12 + dts/src/powerpc/p5040ds.dts | 12 + dts/src/powerpc/t1023rdb.dts | 151 +++ dts/src/powerpc/t1024qds.dts | 251 ++++ dts/src/powerpc/t1024rdb.dts | 185 +++ dts/src/powerpc/t104xqds.dtsi | 12 + dts/src/powerpc/t104xrdb.dtsi | 12 + dts/src/powerpc/t208xqds.dtsi | 12 + dts/src/powerpc/t208xrdb.dtsi | 12 + dts/src/powerpc/t4240qds.dts | 12 + dts/src/powerpc/t4240rdb.dts | 12 + 753 files changed, 44349 insertions(+), 10161 deletions(-) create mode 100644 dts/Bindings/arc/archs-idu-intc.txt create mode 100644 dts/Bindings/arc/archs-intc.txt create mode 100644 dts/Bindings/arc/axs101.txt create mode 100644 dts/Bindings/arc/axs103.txt create mode 100644 dts/Bindings/arm/altera/socfpga-sdram-controller.txt create mode 100644 dts/Bindings/arm/armv7m_systick.txt create mode 100644 dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt create mode 100644 dts/Bindings/arm/mediatek/mediatek,infracfg.txt create mode 100644 dts/Bindings/arm/mediatek/mediatek,pericfg.txt create mode 100644 dts/Bindings/arm/mediatek/mediatek,topckgen.txt create mode 100644 dts/Bindings/arm/scu.txt create mode 100644 dts/Bindings/arm/ux500/boards.txt create mode 100644 dts/Bindings/arm/zte.txt create mode 100644 dts/Bindings/ata/ahci-ceva.txt create mode 100644 dts/Bindings/ata/brcm,sata-brcmstb.txt create mode 100644 dts/Bindings/clock/amlogic,meson8b-clkc.txt delete mode 100644 dts/Bindings/clock/bcm-cygnus-clock.txt create mode 100644 dts/Bindings/clock/brcm,iproc-clocks.txt create mode 100644 dts/Bindings/clock/csr,atlas7-car.txt create mode 100644 dts/Bindings/clock/hi6220-clock.txt create mode 100644 dts/Bindings/clock/imx7d-clock.txt create mode 100644 dts/Bindings/clock/ingenic,cgu.txt create mode 100644 dts/Bindings/clock/lpc1850-ccu.txt create mode 100644 dts/Bindings/clock/lpc1850-cgu.txt create mode 100644 dts/Bindings/clock/marvell,berlin.txt create mode 100644 dts/Bindings/clock/marvell,pxa1928.txt create mode 100644 dts/Bindings/clock/qca,ath79-pll.txt create mode 100644 dts/Bindings/clock/renesas,h8300-div-clock.txt create mode 100644 dts/Bindings/clock/renesas,h8s2678-pll-clock.txt create mode 100644 dts/Bindings/clock/st,stm32-rcc.txt create mode 100644 dts/Bindings/clock/ti,cdce925.txt create mode 100644 dts/Bindings/clock/zx296702-clk.txt create mode 100644 dts/Bindings/crypto/marvell-cesa.txt create mode 100644 dts/Bindings/dma/ti-dma-crossbar.txt create mode 100644 dts/Bindings/drm/msm/dsi.txt create mode 100644 dts/Bindings/drm/msm/edp.txt delete mode 100644 dts/Bindings/drm/tilcdc/slave.txt create mode 100644 dts/Bindings/edac/apm-xgene-edac.txt create mode 100644 dts/Bindings/gpio/brcm,brcmstb-gpio.txt create mode 100644 dts/Bindings/gpio/gpio-ath79.txt create mode 100644 dts/Bindings/gpio/gpio-atlas7.txt create mode 100644 dts/Bindings/gpio/gpio-etraxfs.txt create mode 100644 dts/Bindings/gpio/gpio-xlp.txt create mode 100644 dts/Bindings/gpio/nxp,lpc1850-gpio.txt create mode 100644 dts/Bindings/h8300/cpu.txt create mode 100644 dts/Bindings/hwlock/hwlock.txt create mode 100644 dts/Bindings/hwlock/omap-hwspinlock.txt create mode 100644 dts/Bindings/hwlock/qcom-hwspinlock.txt create mode 100644 dts/Bindings/hwlock/sirf,hwspinlock.txt create mode 100644 dts/Bindings/i2c/i2c-brcmstb.txt create mode 100644 dts/Bindings/i2c/i2c-mt6577.txt create mode 100644 dts/Bindings/i2c/i2c-xgene-slimpro.txt create mode 100644 dts/Bindings/iio/adc/berlin2_adc.txt create mode 100644 dts/Bindings/iio/imu/inv_mpu6050.txt create mode 100644 dts/Bindings/iio/magnetometer/bmc150_magn.txt create mode 100644 dts/Bindings/iio/temperature/mlx90614.txt create mode 100644 dts/Bindings/input/ti,drv2665.txt create mode 100644 dts/Bindings/interrupt-controller/ingenic,intc.txt create mode 100644 dts/Bindings/interrupt-controller/qca,ath79-cpu-intc.txt create mode 100644 dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt create mode 100644 dts/Bindings/interrupt-controller/renesas,h8300h-intc.txt create mode 100644 dts/Bindings/interrupt-controller/renesas,h8s-intc.txt create mode 100644 dts/Bindings/iommu/arm,smmu-v3.txt create mode 100644 dts/Bindings/leds/leds-aat1290.txt create mode 100644 dts/Bindings/leds/leds-bcm6328.txt create mode 100644 dts/Bindings/leds/leds-bcm6358.txt create mode 100644 dts/Bindings/leds/leds-ktd2692.txt create mode 100644 dts/Bindings/leds/leds-tlc591xx.txt create mode 100644 dts/Bindings/mailbox/brcm,bcm2835-mbox.txt create mode 100644 dts/Bindings/media/i2c/adp1653.txt create mode 100644 dts/Bindings/media/st,stih4xx.txt create mode 100644 dts/Bindings/memory-controllers/ath79-ddr-controller.txt create mode 100644 dts/Bindings/memory-controllers/renesas,h8300-bsc.txt create mode 100644 dts/Bindings/memory-controllers/tegra-emc.txt create mode 100644 dts/Bindings/mfd/mfd.txt mode change 100755 => 100644 dts/Bindings/mfd/tps6507x.txt create mode 100644 dts/Bindings/mips/ath79-soc.txt create mode 100644 dts/Bindings/mmc/mtk-sd.txt create mode 100644 dts/Bindings/mtd/brcm,brcmnand.txt delete mode 100644 dts/Bindings/net/amd-xgbe-phy.txt create mode 100644 dts/Bindings/net/ezchip_enet.txt create mode 100644 dts/Bindings/net/ipq806x-dwmac.txt create mode 100644 dts/Bindings/net/nfc/nfcmrvl.txt create mode 100644 dts/Bindings/net/nfc/st-nci.txt delete mode 100644 dts/Bindings/net/nfc/st21nfcb.txt create mode 100644 dts/Bindings/net/nxp,lpc1850-dwmac.txt create mode 100644 dts/Bindings/net/renesas,ravb.txt create mode 100644 dts/Bindings/net/ti,dp83867.txt create mode 100644 dts/Bindings/panel/hannstar,hsd100pxn1.txt create mode 100644 dts/Bindings/panel/lg,lb070wv8.txt create mode 100644 dts/Bindings/pci/xgene-pci-msi.txt create mode 100644 dts/Bindings/phy/brcm,brcmstb-sata-phy.txt create mode 100644 dts/Bindings/phy/pistachio-usb-phy.txt create mode 100644 dts/Bindings/phy/pxa1928-usb-phy.txt create mode 100644 dts/Bindings/pinctrl/berlin,pinctrl.txt create mode 100644 dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt create mode 100644 dts/Bindings/pinctrl/img,pistachio-pinctrl.txt delete mode 100644 dts/Bindings/pinctrl/lantiq,falcon-pinumx.txt create mode 100644 dts/Bindings/pinctrl/lantiq,pinctrl-falcon.txt create mode 100644 dts/Bindings/pinctrl/lantiq,pinctrl-xway.txt delete mode 100644 dts/Bindings/pinctrl/lantiq,xway-pinumx.txt create mode 100644 dts/Bindings/pinctrl/nxp,lpc1850-scu.txt create mode 100644 dts/Bindings/pinctrl/pinctrl-atlas7.txt create mode 100644 dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt create mode 100644 dts/Bindings/power/bq24257.txt create mode 100644 dts/Bindings/power/bq25890.txt create mode 100644 dts/Bindings/power/rt9455_charger.txt create mode 100644 dts/Bindings/regulator/qcom,spmi-regulator.txt create mode 100644 dts/Bindings/remoteproc/wkup_m3_rproc.txt create mode 100644 dts/Bindings/reset/berlin,reset.txt create mode 100644 dts/Bindings/reset/brcm,bcm63138-pmb.txt create mode 100644 dts/Bindings/rtc/rtc-st-lpc.txt create mode 100644 dts/Bindings/serial/arm_sbsa_uart.txt create mode 100644 dts/Bindings/serial/ingenic,uart.txt create mode 100644 dts/Bindings/serial/nxp,lpc1850-uart.txt create mode 100644 dts/Bindings/serial/uniphier-uart.txt create mode 100644 dts/Bindings/soc/sunxi/sram.txt create mode 100644 dts/Bindings/sound/bt-sco.txt create mode 100644 dts/Bindings/sound/gtm601.txt create mode 100644 dts/Bindings/sound/mt8173-max98090.txt create mode 100644 dts/Bindings/sound/mt8173-rt5650-rt5676.txt create mode 100644 dts/Bindings/sound/mtk-afe-pcm.txt create mode 100644 dts/Bindings/sound/qcom,apq8016-sbc.txt create mode 100644 dts/Bindings/sound/rt5645.txt create mode 100644 dts/Bindings/sound/tas571x.txt create mode 100644 dts/Bindings/sound/zte,zx-i2s.txt create mode 100644 dts/Bindings/sound/zte,zx-spdif.txt create mode 100644 dts/Bindings/spi/spi-ath79.txt create mode 100644 dts/Bindings/spi/spi-zynqmp-qspi.txt create mode 100644 dts/Bindings/thermal/hisilicon-thermal.txt create mode 100644 dts/Bindings/thermal/qcom-spmi-temp-alarm.txt create mode 100644 dts/Bindings/timer/nxp,lpc3220-timer.txt create mode 100644 dts/Bindings/timer/renesas,16bit-timer.txt create mode 100644 dts/Bindings/timer/renesas,8bit-timer.txt create mode 100644 dts/Bindings/timer/renesas,tpu.txt create mode 100644 dts/Bindings/timer/st,stm32-timer.txt delete mode 100644 dts/Bindings/usb/ci-hdrc-imx.txt delete mode 100644 dts/Bindings/usb/ci-hdrc-qcom.txt delete mode 100644 dts/Bindings/usb/ci-hdrc-zevio.txt create mode 100644 dts/Bindings/video/exynos-mic.txt create mode 100644 dts/Bindings/video/exynos5433-decon.txt create mode 100644 dts/Bindings/watchdog/digicolor-wdt.txt create mode 100644 dts/Bindings/watchdog/st_lpc_wdt.txt create mode 100644 dts/include/dt-bindings/clock/bcm-cygnus.h create mode 100644 dts/include/dt-bindings/clock/hi6220-clock.h create mode 100644 dts/include/dt-bindings/clock/imx7d-clock.h create mode 100644 dts/include/dt-bindings/clock/jz4740-cgu.h create mode 100644 dts/include/dt-bindings/clock/jz4780-cgu.h create mode 100644 dts/include/dt-bindings/clock/lpc18xx-ccu.h create mode 100644 dts/include/dt-bindings/clock/lpc18xx-cgu.h create mode 100644 dts/include/dt-bindings/clock/marvell,pxa1928.h create mode 100644 dts/include/dt-bindings/clock/meson8b-clkc.h create mode 100644 dts/include/dt-bindings/clock/mt8135-clk.h create mode 100644 dts/include/dt-bindings/clock/mt8173-clk.h create mode 100644 dts/include/dt-bindings/clock/samsung,s2mps11.h create mode 100644 dts/include/dt-bindings/clock/zx296702-clock.h create mode 100644 dts/include/dt-bindings/mfd/st-lpc.h create mode 100644 dts/include/dt-bindings/net/ti-dp83867.h create mode 100644 dts/include/dt-bindings/phy/phy-pistachio-usb.h create mode 100644 dts/include/dt-bindings/pinctrl/bcm2835.h create mode 100644 dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h create mode 100644 dts/include/dt-bindings/reset-controller/mt8135-resets.h create mode 100644 dts/include/dt-bindings/reset-controller/mt8173-resets.h create mode 100644 dts/include/dt-bindings/sound/apq8016-lpass.h create mode 100644 dts/include/dt-bindings/sound/audio-jack-events.h create mode 100644 dts/include/dt-bindings/sound/tas2552.h delete mode 100644 dts/src/arc/angel4.dts create mode 100644 dts/src/arc/axc001.dtsi create mode 100644 dts/src/arc/axc003.dtsi create mode 100644 dts/src/arc/axc003_idu.dtsi create mode 100644 dts/src/arc/axs101.dts create mode 100644 dts/src/arc/axs103.dts create mode 100644 dts/src/arc/axs103_idu.dts create mode 100644 dts/src/arc/axs10x_mb.dtsi create mode 100644 dts/src/arc/nsim_700.dts create mode 100644 dts/src/arc/nsim_hs.dts create mode 100644 dts/src/arc/nsim_hs_idu.dts create mode 100644 dts/src/arc/nsimosci_hs.dts create mode 100644 dts/src/arc/nsimosci_hs_idu.dts create mode 100644 dts/src/arc/vdk_axc003.dtsi create mode 100644 dts/src/arc/vdk_axc003_idu.dtsi create mode 100644 dts/src/arc/vdk_axs10x_mb.dtsi create mode 100644 dts/src/arc/vdk_hs38.dts create mode 100644 dts/src/arc/vdk_hs38_smp.dts create mode 100644 dts/src/arm/am335x-baltos-ir5221.dts create mode 100644 dts/src/arm/am335x-sl50.dts create mode 100644 dts/src/arm/armada-370-dlink-dns327l.dts create mode 100644 dts/src/arm/armada-385-linksys-caiman.dts create mode 100644 dts/src/arm/armada-385-linksys-cobra.dts create mode 100644 dts/src/arm/armada-385-linksys.dtsi create mode 100644 dts/src/arm/at91-ariettag25.dts create mode 100644 dts/src/arm/at91-kizbox.dts create mode 100644 dts/src/arm/at91-kizbox2.dts create mode 100644 dts/src/arm/at91-kizboxmini.dts create mode 100644 dts/src/arm/bcm4708-asus-rt-ac56u.dts create mode 100644 dts/src/arm/bcm4708-asus-rt-ac68u.dts create mode 100644 dts/src/arm/bcm4708-smartrg-sr400ac.dts create mode 100644 dts/src/arm/bcm4709-asus-rt-ac87u.dts create mode 100644 dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts create mode 100644 dts/src/arm/bcm5301x-nand-cs0-bch8.dtsi delete mode 100644 dts/src/arm/dove-cm-a510.dts create mode 100644 dts/src/arm/dove-cm-a510.dtsi create mode 100644 dts/src/arm/dove-sbc-a510.dts create mode 100644 dts/src/arm/exynos5422-odroidxu3-common.dtsi create mode 100644 dts/src/arm/exynos5422-odroidxu3-lite.dts create mode 100644 dts/src/arm/imx6dl-apf6dev.dts create mode 100644 dts/src/arm/imx6dl-aristainetos2_4.dts create mode 100644 dts/src/arm/imx6dl-aristainetos2_7.dts create mode 100644 dts/src/arm/imx6dl-gw551x.dts create mode 100644 dts/src/arm/imx6q-apf6dev.dts create mode 100644 dts/src/arm/imx6q-gw551x.dts create mode 100644 dts/src/arm/imx6qdl-apf6.dtsi create mode 100644 dts/src/arm/imx6qdl-apf6dev.dtsi create mode 100644 dts/src/arm/imx6qdl-aristainetos2.dtsi create mode 100644 dts/src/arm/imx6qdl-gw551x.dtsi create mode 100644 dts/src/arm/imx7d-pinfunc.h create mode 100644 dts/src/arm/imx7d-sdb.dts create mode 100644 dts/src/arm/imx7d.dtsi create mode 100644 dts/src/arm/k2e-netcp.dtsi create mode 100644 dts/src/arm/k2hk-netcp.dtsi create mode 100644 dts/src/arm/k2l-netcp.dtsi delete mode 100644 dts/src/arm/kizbox.dts create mode 100644 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Interrupt Distribution Unit + + This optional 2nd level interrupt controller can be used in SMP configurations for + dynamic IRQ routing, load balancing of common/external IRQs towards core intc. + +Properties: + +- compatible: "snps,archs-idu-intc" +- interrupt-controller: This is an interrupt controller. +- interrupt-parent: +- #interrupt-cells: Must be <2>. +- interrupts: <...> specifies the upstream core irqs + + First cell specifies the "common" IRQ from peripheral to IDU + Second cell specifies the irq distribution mode to cores + 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +Example: + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */ + interrupts = <24 25 26 27 28 29 30 31>; + }; + + some_device: serial@c0fc1000 { + interrupt-parent = <&idu_intc>; + interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */ + }; diff --git a/dts/Bindings/arc/archs-intc.txt b/dts/Bindings/arc/archs-intc.txt new file mode 100644 index 0000000000..69f326d6a5 --- /dev/null +++ b/dts/Bindings/arc/archs-intc.txt @@ -0,0 +1,22 @@ +* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) + +Properties: + +- compatible: "snps,archs-intc" +- interrupt-controller: This is an interrupt controller. +- #interrupt-cells: Must be <1>. + + Single Cell "interrupts" property of a device specifies the IRQ number + between 16 to 256 + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +Example: + + intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <16 17 18 19 20 21 22 23 24 25>; + }; diff --git a/dts/Bindings/arc/axs101.txt b/dts/Bindings/arc/axs101.txt new file mode 100644 index 0000000000..48290d5178 --- /dev/null +++ b/dts/Bindings/arc/axs101.txt @@ -0,0 +1,7 @@ +Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon + +Required root node properties: + - compatible = "snps,axs101", "snps,arc-sdp"; diff --git a/dts/Bindings/arc/axs103.txt b/dts/Bindings/arc/axs103.txt new file mode 100644 index 0000000000..6eea862e72 --- /dev/null +++ b/dts/Bindings/arc/axs103.txt @@ -0,0 +1,8 @@ +Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +SDP Main Board with an AXC003 FPGA Card which can contain various flavours of +HS38x cores. + +Required root node properties: + - compatible = "snps,axs103", "snps,arc-sdp"; diff --git a/dts/Bindings/arm/altera/socfpga-sdram-controller.txt b/dts/Bindings/arm/altera/socfpga-sdram-controller.txt new file mode 100644 index 0000000000..77ca635765 --- /dev/null +++ b/dts/Bindings/arm/altera/socfpga-sdram-controller.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Controller + +Required properties: +- compatible : Should contain "altr,sdr-ctl" and "syscon". + syscon is required by the Altera SOCFPGA SDRAM EDAC. +- reg : Should contain 1 register range (address and length) + +Example: + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; diff --git a/dts/Bindings/arm/altera/socfpga-sdram-edac.txt b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt index d0ce01da5c..f5ad0ff69f 100644 --- a/dts/Bindings/arm/altera/socfpga-sdram-edac.txt +++ b/dts/Bindings/arm/altera/socfpga-sdram-edac.txt @@ -2,7 +2,7 @@ Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] The EDAC accesses a range of registers in the SDRAM controller. Required properties: -- compatible : should contain "altr,sdram-edac"; +- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" - altr,sdr-syscon : phandle of the sdr module - interrupts : Should contain the SDRAM ECC IRQ in the appropriate format for the IRQ controller. diff --git a/dts/Bindings/arm/arm-boards b/dts/Bindings/arm/arm-boards index b78564b2b2..1a709970e7 100644 --- a/dts/Bindings/arm/arm-boards +++ b/dts/Bindings/arm/arm-boards @@ -157,3 +157,69 @@ Example: }; }; + +ARM Versatile Express Boards +----------------------------- +For details on the device tree bindings for ARM Versatile Express boards +please consult the vexpress.txt file in the same directory as this file. + +ARM Juno Boards +---------------- +The Juno boards are targeting development for AArch64 systems. The first +iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64, +with the second iteration, Juno r1, mainly aimed at development of PCIe +based systems. Juno r1 also has support for AXI masters placed on the TLX +connectors to join the coherency domain. + +Juno boards are described in a similar way to ARM Versatile Express boards, +with the motherboard part of the hardware being described in a separate file +to highlight the fact that is part of the support infrastructure for the SoC. +Juno device tree bindings also share the Versatile Express bindings as +described under the RS1 memory mapping. + +Required properties (in root node): + compatible = "arm,juno"; /* For Juno r0 board */ + compatible = "arm,juno-r1"; /* For Juno r1 board */ + +Required nodes: +The description for the board must include: + - a "psci" node describing the boot method used for the secondary CPUs. + A detailed description of the bindings used for "psci" nodes is present + in the psci.txt file. + - a "cpus" node describing the available cores and their associated + "enable-method"s. For more details see cpus.txt file. + +Example: + +/dts-v1/; +/ { + model = "ARM Juno development board (r0)"; + compatible = "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A57_0: cpu@0 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + ..... + + A53_0: cpu@100 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + + ..... + }; + +}; diff --git a/dts/Bindings/arm/armv7m_systick.txt b/dts/Bindings/arm/armv7m_systick.txt new file mode 100644 index 0000000000..7cf4a24601 --- /dev/null +++ b/dts/Bindings/arm/armv7m_systick.txt @@ -0,0 +1,26 @@ +* ARMv7M System Timer + +ARMv7-M includes a system timer, known as SysTick. Current driver only +implements the clocksource feature. + +Required properties: +- compatible : Should be "arm,armv7m-systick" +- reg : The address range of the timer + +Required clocking property, have to be one of: +- clocks : The input clock of the timer +- clock-frequency : The rate in HZ in input of the ARM SysTick + +Examples: + +systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + clocks = <&clk_systick>; +}; + +systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + clock-frequency = <90000000>; +}; diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt index 2e99b5b573..424ac8cbfa 100644 --- a/dts/Bindings/arm/atmel-at91.txt +++ b/dts/Bindings/arm/atmel-at91.txt @@ -98,7 +98,7 @@ Example: }; RAMC SDRAM/DDR Controller required properties: -- compatible: Should be "atmel,at91rm9200-sdramc", +- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", diff --git a/dts/Bindings/arm/bcm/brcm,bcm2835.txt b/dts/Bindings/arm/bcm/brcm,bcm2835.txt index ac683480c4..c78576bb77 100644 --- a/dts/Bindings/arm/bcm/brcm,bcm2835.txt +++ b/dts/Bindings/arm/bcm/brcm,bcm2835.txt @@ -1,8 +1,35 @@ Broadcom BCM2835 device tree bindings ------------------------------------------- -Boards with the BCM2835 SoC shall have the following properties: +Raspberry Pi Model A +Required root node properties: +compatible = "raspberrypi,model-a", "brcm,bcm2835"; -Required root node property: +Raspberry Pi Model A+ +Required root node properties: +compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; +Raspberry Pi Model B +Required root node properties: +compatible = "raspberrypi,model-b", "brcm,bcm2835"; + +Raspberry Pi Model B (no P5) +early model B with I2C0 rather than I2C1 routed to the expansion header +Required root node properties: +compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835"; + +Raspberry Pi Model B rev2 +Required root node properties: +compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; + +Raspberry Pi Model B+ +Required root node properties: +compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + +Raspberry Pi Compute Module +Required root node properties: +compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + +Generic BCM2835 board +Required root node properties: compatible = "brcm,bcm2835"; diff --git a/dts/Bindings/arm/bcm/brcm,bcm63138.txt b/dts/Bindings/arm/bcm/brcm,bcm63138.txt index bd49987a88..b82b6a0ae6 100644 --- a/dts/Bindings/arm/bcm/brcm,bcm63138.txt +++ b/dts/Bindings/arm/bcm/brcm,bcm63138.txt @@ -7,3 +7,79 @@ following properties: Required root node property: compatible: should be "brcm,bcm63138" + +An optional Boot lookup table Device Tree node is required for secondary CPU +initialization as well as a 'resets' phandle to the correct PMB controller as +defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an +'enable-method' property. + +Required properties for the Boot lookup table node: +- compatible: should be "brcm,bcm63138-bootlut" +- reg: register base address and length for the Boot Lookup table + +Optional properties for the primary CPU node: +- enable-method: should be "brcm,bcm63138" + +Optional properties for the secondary CPU node: +- enable-method: should be "brcm,bcm63138" +- resets: phandle to the relevant PMB controller, one integer indicating the internal + bus number, and a second integer indicating the address of the CPU in the PMB + internal bus number. + +Example: + + cpus { + cpu@0 { + compatible = "arm,cotex-a9"; + reg = <0>; + ... + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + ... + enable-method = "brcm,bcm63138"; + resets = <&pmb0 4 1>; + }; + }; + + bootlut: bootlut@8000 { + compatible = "brcm,bcm63138-bootlut"; + reg = <0x8000 0x50>; + }; + +======= +reboot +------ +Two nodes are required for software reboot: a timer node and a syscon-reboot node. + +Timer node: + +- compatible: Must be "brcm,bcm6328-timer", "syscon" +- reg: Register base address and length + +Syscon reboot node: + +See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the +detailed list of properties, the two values defined below are specific to the +BCM6328-style timer: + +- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register + from the beginning of the TIMER block +- mask: Should be 1 for the SoftRst bit. + +Example: + + timer: timer@80 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x80 0x3c>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <0x1>; + }; diff --git a/dts/Bindings/arm/cci.txt b/dts/Bindings/arm/cci.txt index 3c5c631328..aef1d200a9 100644 --- a/dts/Bindings/arm/cci.txt +++ b/dts/Bindings/arm/cci.txt @@ -31,8 +31,9 @@ specific to ARM. - compatible Usage: required Value type: - Definition: must be set to + Definition: must contain one of the following: "arm,cci-400" + "arm,cci-500" - reg Usage: required @@ -99,6 +100,7 @@ specific to ARM. "arm,cci-400-pmu,r1" "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has secure acces to CCI registers + "arm,cci-500-pmu,r0" - reg: Usage: required Value type: Integer cells. A register entry, expressed diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt index 88602b7541..65a6db2271 100644 --- a/dts/Bindings/arm/coresight.txt +++ b/dts/Bindings/arm/coresight.txt @@ -17,15 +17,19 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; + - "qcom,coresight-replicator1x", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. - * clocks: the clock associated to this component. + * clocks: the clocks associated to this component. - * clock-names: the name of the clock as referenced by the code. - Since we are using the AMBA framework, the name should be - "apb_pclk". + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. * port or ports: The representation of the component's port layout using the generic DT graph presentation found in diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt index 6aa331d11c..d6b794cef0 100644 --- a/dts/Bindings/arm/cpus.txt +++ b/dts/Bindings/arm/cpus.txt @@ -188,6 +188,7 @@ nodes to be present and contain the properties described below. # On ARM 32-bit systems this property is optional and can be one of: "allwinner,sun6i-a31" + "allwinner,sun8i-a23" "arm,psci" "brcm,brahma-b15" "marvell,armada-375-smp" diff --git a/dts/Bindings/arm/exynos/power_domain.txt b/dts/Bindings/arm/exynos/power_domain.txt index 5da38c5ed4..e151057d92 100644 --- a/dts/Bindings/arm/exynos/power_domain.txt +++ b/dts/Bindings/arm/exynos/power_domain.txt @@ -19,9 +19,10 @@ Optional Properties: domains. - clock-names: The following clocks can be specified: - oscclk: Oscillator clock. - - pclkN, clkN: Pairs of parent of input clock and input clock to the - devices in this power domain. Maximum of 4 pairs (N = 0 to 3) - are supported currently. + - clkN: Input clocks to the devices in this power domain. These clocks + will be reparented to oscclk before swithing power domain off. + Their original parent will be brought back after turning on + the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - asbN: Clocks required by asynchronous bridges (ASB) present in the power domain. These clock should be enabled during power domain on/off operations. diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt index a5462b6b3c..2a3ba73f0c 100644 --- a/dts/Bindings/arm/fsl.txt +++ b/dts/Bindings/arm/fsl.txt @@ -81,12 +81,15 @@ Freescale Vybrid Platform Device Tree Bindings For the Vybrid SoC familiy all variants with DDR controller are supported, which is the VF5xx and VF6xx series. Out of historical reasons, in most places the kernel uses vf610 to refer to the whole familiy. +The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 +core support. Required root node compatible property (one of them): - compatible = "fsl,vf500"; - compatible = "fsl,vf510"; - compatible = "fsl,vf600"; - compatible = "fsl,vf610"; + - compatible = "fsl,vf610m4"; Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------ diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt index 35b1bd49cf..c431c67524 100644 --- a/dts/Bindings/arm/hisilicon/hisilicon.txt +++ b/dts/Bindings/arm/hisilicon/hisilicon.txt @@ -1,5 +1,8 @@ Hisilicon Platforms Device Tree Bindings ---------------------------------------------------- +Hi6220 SoC +Required root node properties: + - compatible = "hisilicon,hi6220"; Hi4511 Board Required root node properties: @@ -13,6 +16,9 @@ HiP01 ca9x2 Board Required root node properties: - compatible = "hisilicon,hip01-ca9x2"; +HiKey Board +Required root node properties: + - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; Hisilicon system controller @@ -40,6 +46,87 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; + + +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; + ----------------------------------------------------------------------- Hisilicon HiP01 system controller diff --git a/dts/Bindings/arm/l2cc.txt b/dts/Bindings/arm/l2cc.txt index 0dbabe9a6b..2251dccb14 100644 --- a/dts/Bindings/arm/l2cc.txt +++ b/dts/Bindings/arm/l2cc.txt @@ -67,6 +67,11 @@ Optional properties: disable if zero. - arm,prefetch-offset : Override prefetch offset value. Valid values are 0-7, 15, 23, and 31. +- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) +- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) Example: diff --git a/dts/Bindings/arm/marvell,berlin.txt b/dts/Bindings/arm/marvell,berlin.txt index a99eb9eb14..3bab18409b 100644 --- a/dts/Bindings/arm/marvell,berlin.txt +++ b/dts/Bindings/arm/marvell,berlin.txt @@ -1,6 +1,18 @@ Marvell Berlin SoC Family Device Tree Bindings --------------------------------------------------------------- +Work in progress statement: + +Device tree files and bindings applying to Marvell Berlin SoCs and boards are +considered "unstable". Any Marvell Berlin device tree binding may change at any +time. Be sure to use a device tree binary and a kernel image generated from the +same source tree. + +Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a +stable binding/ABI. + +--------------------------------------------------------------- + Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: @@ -49,10 +61,9 @@ chip control registers, so there should be a single DT node only providing the different functions which are described below. Required properties: -- compatible: shall be one of - "marvell,berlin2-chip-ctrl" for BG2 - "marvell,berlin2cd-chip-ctrl" for BG2CD - "marvell,berlin2q-chip-ctrl" for BG2Q +- compatible: + * the first and second values must be: + "simple-mfd", "syscon" - reg: address and length of following register sets for BG2/BG2CD: chip control register set BG2Q: chip control register set and cpu pll registers @@ -63,90 +74,23 @@ Marvell Berlin SoCs have a system control register set providing several individual registers dealing with pinmux, padmux, and reset. Required properties: -- compatible: should be one of - "marvell,berlin2-system-ctrl" for BG2 - "marvell,berlin2cd-system-ctrl" for BG2CD - "marvell,berlin2q-system-ctrl" for BG2Q +- compatible: + * the first and second values must be: + "simple-mfd", "syscon" - reg: address and length of the system control register set -* Clock provider binding - -As clock related registers are spread among the chip control registers, the -chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q) -SoCs share the same IP for PLLs and clocks, with some minor differences in -features and register layout. - -Required properties: -- #clock-cells: shall be set to 1 -- clocks: clock specifiers referencing the core clock input clocks -- clock-names: array of strings describing the input clock specifiers above. - Allowed clock-names for the reference clocks are - "refclk" for the SoCs osciallator input on all SoCs, - and SoC-specific input clocks for - BG2/BG2CD: "video_ext0" for the external video clock input - -Clocks provided by core clocks shall be referenced by a clock specifier -indexing one of the provided clocks. Refer to dt-bindings/clock/berlin.h -for the corresponding index mapping. - -* Pin controller binding - -Pin control registers are part of both register sets, chip control and system -control. The pins controlled are organized in groups, so no actual pin -information is needed. - -A pin-controller node should contain subnodes representing the pin group -configurations, one per function. Each subnode has the group name and the muxing -function used. - -Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called -a 'function' in the pin-controller subsystem. - -Required subnode-properties: -- groups: a list of strings describing the group names. -- function: a string describing the function used to mux the groups. - -* Reset controller binding - -A reset controller is part of the chip control registers set. The chip control -node also provides the reset. The register set is not at the same offset between -Berlin SoCs. - -Required property: -- #reset-cells: must be set to 2 - Example: chip: chip-control@ea0000 { - compatible = "marvell,berlin2-chip-ctrl"; - #clock-cells = <1>; - #reset-cells = <2>; + compatible = "simple-mfd", "syscon"; reg = <0xea0000 0x400>; - clocks = <&refclk>, <&externaldev 0>; - clock-names = "refclk", "video_ext0"; - spi1_pmux: spi1-pmux { - groups = "G0"; - function = "spi1"; - }; + /* sub-device nodes */ }; sysctrl: system-controller@d000 { - compatible = "marvell,berlin2-system-ctrl"; + compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; - }; + /* sub-device nodes */ }; diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt new file mode 100644 index 0000000000..936166fbee --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -0,0 +1,23 @@ +Mediatek apmixedsys controller +============================== + +The Mediatek apmixedsys controller provides the PLLs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8173-apmixedsys" +- #clock-cells: Must be 1 + +The apmixedsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt new file mode 100644 index 0000000000..f6cd3e4192 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt @@ -0,0 +1,30 @@ +Mediatek infracfg controller +============================ + +The Mediatek infracfg controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The infracfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Also it uses the common reset controller binding from +Documentation/devicetree/bindings/reset/reset.txt. +The available reset outputs are defined in +dt-bindings/reset-controller/mt*-resets.h + +Example: + +infracfg: power-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.txt b/dts/Bindings/arm/mediatek/mediatek,pericfg.txt new file mode 100644 index 0000000000..f25b85499a --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.txt @@ -0,0 +1,30 @@ +Mediatek pericfg controller +=========================== + +The Mediatek pericfg controller provides various clocks and reset +outputs to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-pericfg", "syscon" + - "mediatek,mt8173-pericfg", "syscon" +- #clock-cells: Must be 1 +- #reset-cells: Must be 1 + +The pericfg controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Also it uses the common reset controller binding from +Documentation/devicetree/bindings/reset/reset.txt. +The available reset outputs are defined in +dt-bindings/reset-controller/mt*-resets.h + +Example: + +pericfg: power-controller@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt new file mode 100644 index 0000000000..f9e917994c --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt @@ -0,0 +1,23 @@ +Mediatek topckgen controller +============================ + +The Mediatek topckgen controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be: + - "mediatek,mt8135-topckgen" + - "mediatek,mt8173-topckgen" +- #clock-cells: Must be 1 + +The topckgen controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +Example: + +topckgen: power-controller@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/dts/Bindings/arm/scu.txt b/dts/Bindings/arm/scu.txt new file mode 100644 index 0000000000..c447680519 --- /dev/null +++ b/dts/Bindings/arm/scu.txt @@ -0,0 +1,25 @@ +* ARM Snoop Control Unit (SCU) + +As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided +with a Snoop Control Unit. The register range is usually 256 (0x100) +bytes. + +References: + +- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual + Revision r2p0 +- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual + Revision r0p1 + +- compatible : Should be: + "arm,cortex-a9-scu" + "arm,cortex-a5-scu" + +- reg : Specify the base address and the size of the SCU register window. + +Example: + +scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; +}; diff --git a/dts/Bindings/arm/ux500/boards.txt b/dts/Bindings/arm/ux500/boards.txt new file mode 100644 index 0000000000..b8737a8de7 --- /dev/null +++ b/dts/Bindings/arm/ux500/boards.txt @@ -0,0 +1,83 @@ +ST-Ericsson Ux500 boards +------------------------ + +Required properties (in root node) one of these: + compatible = "st-ericsson,mop500" (legacy) + compatible = "st-ericsson,u8500" + +Required node (under root node): + +soc: represents the system-on-chip and contains the chip +peripherals + +Required property of soc node, one of these: + compatible = "stericsson,db8500" + +Required subnodes under soc node: + +backupram: (used for CPU spin tables and for storing data +during retention, system won't boot without this): + compatible = "ste,dbx500-backupram" + +scu: + see binding for arm/scu.txt + +interrupt-controller: + see binding for arm/gic.txt + +timer: + see binding for arm/twd.txt + +clocks: + see binding for clocks/ux500.txt + +Example: + +/dts-v1/; + +/ { + model = "ST-Ericsson HREF (pre-v60) and ST UIB"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ + clocks = <&smp_twd_clk>; + }; + + clocks { + compatible = "stericsson,u8500-clks"; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + }; + }; +}; diff --git a/dts/Bindings/arm/zte.txt b/dts/Bindings/arm/zte.txt new file mode 100644 index 0000000000..3ff5c9e85c --- /dev/null +++ b/dts/Bindings/arm/zte.txt @@ -0,0 +1,15 @@ +ZTE platforms device tree bindings +--------------------------------------- + +- ZX296702 board: + Required root node properties: + - compatible = "zte,zx296702-ad1", "zte,zx296702" + +System management required properties: + - compatible = "zte,sysctrl" + +Low power management required properties: + - compatible = "zte,zx296702-pcu" + +Bus matrix required properties: + - compatible = "zte,zx-bus-matrix" diff --git a/dts/Bindings/ata/ahci-ceva.txt b/dts/Bindings/ata/ahci-ceva.txt new file mode 100644 index 0000000000..7ca8b976c1 --- /dev/null +++ b/dts/Bindings/ata/ahci-ceva.txt @@ -0,0 +1,20 @@ +Binding for CEVA AHCI SATA Controller + +Required properties: + - reg: Physical base address and size of the controller's register area. + - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. + - clocks: Input clock specifier. Refer to common clock bindings. + - interrupts: Interrupt specifier. Refer to interrupt binding. + +Optional properties: + - ceva,broken-gen2: limit to gen1 speed instead of gen2. + +Examples: + ahci@fd0c0000 { + compatible = "ceva,ahci-1v84"; + reg = <0xfd0c0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <0 133 4>; + clocks = <&clkc SATA_CLK_ID>; + ceva,broken-gen2; + }; diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt index c2340eeeb9..a2321819e7 100644 --- a/dts/Bindings/ata/ahci-platform.txt +++ b/dts/Bindings/ata/ahci-platform.txt @@ -16,6 +16,8 @@ Required properties: - "snps,dwc-ahci" - "snps,exynos5440-ahci" - "snps,spear-ahci" + - "fsl,qoriq-ahci" : for qoriq series socs which include ls1021, ls2085, etc. + - "fsl,-ahci" : chip could be ls1021, ls2085 etc. - "generic-ahci" - interrupts : - reg : diff --git a/dts/Bindings/ata/brcm,sata-brcmstb.txt b/dts/Bindings/ata/brcm,sata-brcmstb.txt new file mode 100644 index 0000000000..20ac9bbfa1 --- /dev/null +++ b/dts/Bindings/ata/brcm,sata-brcmstb.txt @@ -0,0 +1,34 @@ +* Broadcom SATA3 AHCI Controller for STB + +SATA nodes are defined to describe on-chip Serial ATA controllers. +Each SATA controller should have its own node. + +Required properties: +- compatible : compatible list, may contain "brcm,bcm7445-ahci" and/or + "brcm,sata3-ahci" +- reg : register mappings for AHCI and SATA_TOP_CTRL +- reg-names : "ahci" and "top-ctrl" +- interrupts : interrupt mapping for SATA IRQ + +Also see ahci-platform.txt. + +Example: + + sata@f045a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>; + reg-names = "ahci", "top-ctrl"; + interrupts = <0 30 0>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + }; + }; diff --git a/dts/Bindings/clock/amlogic,meson8b-clkc.txt b/dts/Bindings/clock/amlogic,meson8b-clkc.txt new file mode 100644 index 0000000000..2b7b3fa588 --- /dev/null +++ b/dts/Bindings/clock/amlogic,meson8b-clkc.txt @@ -0,0 +1,40 @@ +* Amlogic Meson8b Clock and Reset Unit + +The Amlogic Meson8b clock controller generates and supplies clock to various +controllers within the SoC. + +Required Properties: + +- compatible: should be "amlogic,meson8b-clkc" +- reg: it must be composed by two tuples: + 0) physical base address of the xtal register and length of memory + mapped region. + 1) physical base address of the clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be +used in device tree sources. + +Example: Clock controller node: + + clkc: clock-controller@c1104000 { + #clock-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0xc1108000 0x4>, <0xc1104000 0x460>; + }; + + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clkc CLKID_CLK81>; + status = "disabled"; + }; diff --git a/dts/Bindings/clock/bcm-cygnus-clock.txt b/dts/Bindings/clock/bcm-cygnus-clock.txt deleted file mode 100644 index 00d26edec8..0000000000 --- a/dts/Bindings/clock/bcm-cygnus-clock.txt +++ /dev/null @@ -1,34 +0,0 @@ -Broadcom Cygnus Clocks - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -Currently various "fixed" clocks are declared for peripheral drivers that use -the common clock framework to reference their core clocks. Proper support of -these clocks will be added later - -Device tree example: - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <25000000>; - }; - - apb_clk: apb_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - }; - - periph_clk: periph_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - }; - }; diff --git a/dts/Bindings/clock/brcm,iproc-clocks.txt b/dts/Bindings/clock/brcm,iproc-clocks.txt new file mode 100644 index 0000000000..da8d9bb575 --- /dev/null +++ b/dts/Bindings/clock/brcm,iproc-clocks.txt @@ -0,0 +1,132 @@ +Broadcom iProc Family Clocks + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +The iProc clock controller manages clocks that are common to the iProc family. +An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, +LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL +comprises of several leaf clocks + +Required properties for a PLL and its leaf clocks: + +- compatible: + Should have a value of the form "brcm,-". For example, GENPLL on +Cygnus has a compatible string of "brcm,cygnus-genpll" + +- #clock-cells: + Have a value of <1> since there are more than 1 leaf clock of a given PLL + +- reg: + Define the base and range of the I/O address space that contain the iProc +clock control registers required for the PLL + +- clocks: + The input parent clock phandle for the PLL. For most iProc PLLs, this is an +onboard crystal with a fixed rate + +- clock-output-names: + An ordered list of strings defining the names of the clocks + +Example: + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + genpll: genpll { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; + clocks = <&osc>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + +Required properties for ASIU clocks: + +ASIU clocks are a special case. These clocks are derived directly from the +reference clock of the onboard crystal + +- compatible: + Should have a value of the form "brcm,-asiu-clk". For example, ASIU +clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" + +- #clock-cells: + Have a value of <1> since there are more than 1 ASIU clocks + +- reg: + Define the base and range of the I/O address space that contain the iProc +clock control registers required for ASIU clocks + +- clocks: + The input parent clock phandle for the ASIU clock, i.e., the onboard +crystal + +- clock-output-names: + An ordered list of strings defining the names of the ASIU clocks + +Example: + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + asiu_clks: asiu_clks { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x0301d048 0xc>, <0x180aa024 0x4>; + clocks = <&osc>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; + +Cygnus +------ +PLL and leaf clock compatible strings for Cygnus are: + "brcm,cygnus-armpll" + "brcm,cygnus-genpll" + "brcm,cygnus-lcpll0" + "brcm,cygnus-mipipll" + "brcm,cygnus-asiu-clk" + +The following table defines the set of PLL/clock index and ID for Cygnus. +These clock IDs are defined in: + "include/dt-bindings/clock/bcm-cygnus.h" + + Clock Source (Parent) Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK + adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK + pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK + + genpll crystal 0 BCM_CYGNUS_GENPLL + axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK + 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK + ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK + enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK + audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK + can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK + + lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 + pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK + ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK + sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK + usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK + smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK + ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED + + mipipll crystal 0 BCM_CYGNUS_MIPIPLL + ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED + ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD + ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D + ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED + ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED + ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED diff --git a/dts/Bindings/clock/clock-bindings.txt b/dts/Bindings/clock/clock-bindings.txt index 06fc6d541c..2ec489eebe 100644 --- a/dts/Bindings/clock/clock-bindings.txt +++ b/dts/Bindings/clock/clock-bindings.txt @@ -138,9 +138,10 @@ Some platforms may require initial configuration of default parent clocks and clock frequencies. Such a configuration can be specified in a device tree node through assigned-clocks, assigned-clock-parents and assigned-clock-rates properties. The assigned-clock-parents property should contain a list of parent -clocks in form of phandle and clock specifier pairs, the assigned-clock-parents -property the list of assigned clock frequency values - corresponding to clocks -listed in the assigned-clocks property. +clocks in the form of a phandle and clock specifier pair and the +assigned-clock-rates property should contain a list of frequencies in Hz. Both +these properties should correspond to the clocks listed in the assigned-clocks +property. To skip setting parent or rate of a clock its corresponding entry should be set to 0, or can be omitted if it is not followed by any non-zero entry. diff --git a/dts/Bindings/clock/csr,atlas7-car.txt b/dts/Bindings/clock/csr,atlas7-car.txt new file mode 100644 index 0000000000..54d6d13583 --- /dev/null +++ b/dts/Bindings/clock/csr,atlas7-car.txt @@ -0,0 +1,55 @@ +* Clock and reset bindings for CSR atlas7 + +Required properties: +- compatible: Should be "sirf,atlas7-car" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- #reset-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c + +The reset consumer should specify the desired reset by having the reset +ID in its "reset" phandle cell. +The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c + +Examples: Clock and reset controller node: + +car: clock-controller@18620000 { + compatible = "sirf,atlas7-car"; + reg = <0x18620000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +Examples: Consumers using clock or reset: + +timer@10dc0000 { + compatible = "sirf,macro-tick"; + reg = <0x10dc0000 0x1000>; + clocks = <&car 54>; + interrupts = <0 0 0>, + <0 1 0>, + <0 2 0>, + <0 49 0>, + <0 50 0>, + <0 51 0>; +}; + +uart1: uart@18020000 { + cell-index = <1>; + compatible = "sirf,macro-uart"; + reg = <0x18020000 0x1000>; + clocks = <&clks 95>; + interrupts = <0 18 0>; + fifosize = <32>; +}; + +vpp@13110000 { + compatible = "sirf,prima2-vpp"; + reg = <0x13110000 0x10000>; + interrupts = <0 31 0>; + clocks = <&car 85>; + resets = <&car 29>; +}; diff --git a/dts/Bindings/clock/emev2-clock.txt b/dts/Bindings/clock/emev2-clock.txt index 60bbb1a8c6..268ca61545 100644 --- a/dts/Bindings/clock/emev2-clock.txt +++ b/dts/Bindings/clock/emev2-clock.txt @@ -52,7 +52,7 @@ usia_u0_sclk: usia_u0_sclk { Example of consumer: -uart@e1020000 { +serial@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; interrupts = <0 8 0>; diff --git a/dts/Bindings/clock/hi6220-clock.txt b/dts/Bindings/clock/hi6220-clock.txt new file mode 100644 index 0000000000..259e30af95 --- /dev/null +++ b/dts/Bindings/clock/hi6220-clock.txt @@ -0,0 +1,34 @@ +* Hisilicon Hi6220 Clock Controller + +Clock control registers reside in different Hi6220 system controllers, +please refer the following document to know more about the binding rules +for these system controllers: + +Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt + +Required Properties: + +- compatible: the compatible should be one of the following strings to + indicate the clock controller functionality. + + - "hisilicon,hi6220-aoctrl" + - "hisilicon,hi6220-sysctrl" + - "hisilicon,hi6220-mediactrl" + - "hisilicon,hi6220-pmctrl" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +For example: + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; + +Each clock is assigned an identifier and client nodes use this identifier +to specify the clock which they consume. + +All these identifier could be found in . diff --git a/dts/Bindings/clock/imx7d-clock.txt b/dts/Bindings/clock/imx7d-clock.txt new file mode 100644 index 0000000000..9d3026d81a --- /dev/null +++ b/dts/Bindings/clock/imx7d-clock.txt @@ -0,0 +1,13 @@ +* Clock bindings for Freescale i.MX7 Dual + +Required properties: +- compatible: Should be "fsl,imx7d-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h +for the full list of i.MX7 Dual clock IDs. diff --git a/dts/Bindings/clock/ingenic,cgu.txt b/dts/Bindings/clock/ingenic,cgu.txt new file mode 100644 index 0000000000..f8d4134ae4 --- /dev/null +++ b/dts/Bindings/clock/ingenic,cgu.txt @@ -0,0 +1,53 @@ +Ingenic SoC CGU binding + +The CGU in an Ingenic SoC provides all the clocks generated on-chip. It +typically includes a variety of PLLs, multiplexers, dividers & gates in order +to provide many different clock signals derived from only 2 external source +clocks. + +Required properties: +- compatible : Should be "ingenic,-cgu". + For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". +- reg : The address & length of the CGU registers. +- clocks : List of phandle & clock specifiers for clocks external to the CGU. + Two such external clocks should be specified - first the external crystal + "ext" and second the RTC clock source "rtc". +- clock-names : List of name strings for the external clocks. +- #clock-cells: Should be 1. + Clock consumers specify this argument to identify a clock. The valid values + may be found in -cgu.h>. + +Example SoC include file: + +/ { + cgu: jz4740-cgu { + compatible = "ingenic,jz4740-cgu"; + reg = <0x10000000 0x100>; + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + clocks = <&cgu JZ4740_CLK_UART0>; + }; +}; + +Example board file: + +/ { + ext: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + rtc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + &cgu { + clocks = <&ext> <&rtc>; + clock-names: "ext", "rtc"; + }; +}; diff --git a/dts/Bindings/clock/keystone-pll.txt b/dts/Bindings/clock/keystone-pll.txt index 225990f79b..47570d2072 100644 --- a/dts/Bindings/clock/keystone-pll.txt +++ b/dts/Bindings/clock/keystone-pll.txt @@ -15,8 +15,8 @@ Required properties: - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" - clocks : parent clock phandle - reg - pll control0 and pll multipler registers -- reg-names : control and multiplier. The multiplier is applicable only for - main pll clock +- reg-names : control, multiplier and post-divider. The multiplier and + post-divider registers are applicable only for main pll clock - fixed-postdiv : fixed post divider value. If absent, use clkod register bits for postdiv @@ -25,8 +25,8 @@ Example: #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; fixed-postdiv = <2>; }; diff --git a/dts/Bindings/clock/lpc1850-ccu.txt b/dts/Bindings/clock/lpc1850-ccu.txt new file mode 100644 index 0000000000..fa97c12014 --- /dev/null +++ b/dts/Bindings/clock/lpc1850-ccu.txt @@ -0,0 +1,77 @@ +* NXP LPC1850 Clock Control Unit (CCU) + +Each CGU base clock has several clock branches which can be turned on +or off independently by the Clock Control Units CCU1 or CCU2. The +branch clocks are distributed between CCU1 and CCU2. + + - Above text taken from NXP LPC1850 User Manual. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-ccu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the branch clock names defined in table below. +- clocks: + Shall contain a list of phandles for the base clocks routed + from the CGU to the specific CCU. See mapping of base clocks + and CCU in table below. +- clock-names: + Shall contain a list of names for the base clock routed + from the CGU to the specific CCU. Valid CCU clock names: + "base_usb0_clk", "base_periph_clk", "base_usb1_clk", + "base_cpu_clk", "base_spifi_clk", "base_spi_clk", + "base_apb1_clk", "base_apb3_clk", "base_adchs_clk", + "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk", + "base_uart0_clk", "base_uart1_clk", "base_uart2_clk", + "base_uart3_clk", "base_audio_clk" + +Which branch clocks that are available on the CCU depends on the +specific LPC part. Check the user manual for your specific part. + +A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. + +Example board file: + +soc { + ccu1: clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + + /* A user of CCU brach clocks */ + uart1: serial@40082000 { + ... + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + ... + }; +}; diff --git a/dts/Bindings/clock/lpc1850-cgu.txt b/dts/Bindings/clock/lpc1850-cgu.txt new file mode 100644 index 0000000000..2cc32a9a94 --- /dev/null +++ b/dts/Bindings/clock/lpc1850-cgu.txt @@ -0,0 +1,131 @@ +* NXP LPC1850 Clock Generation Unit (CGU) + +The CGU generates multiple independent clocks for the core and the +peripheral blocks of the LPC18xx. Each independent clock is called +a base clock and itself is one of the inputs to the two Clock +Control Units (CCUs) which control the branch clocks to the +individual peripherals. + +The CGU selects the inputs to the clock generators from multiple +clock sources, controls the clock generation, and routes the outputs +of the clock generators through the clock source bus to the output +stages. Each output stage provides an independent clock source and +corresponds to one of the base clocks for the LPC18xx. + + - Above text taken from NXP LPC1850 User Manual. + + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-cgu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the base clock numbers defined below. +- clocks: + Shall contain a list of phandles for the external input + sources to the CGU. The list shall be in the following + order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin. +- clock-indices: + Shall be an ordered list of numbers defining the base clock + number provided by the CGU. +- clock-output-names: + Shall be an ordered list of strings defining the names of + the clocks provided by the CGU. + +Which base clocks that are available on the CGU depends on the +specific LPC part. Base clocks are numbered from 0 to 27. + +Number: Name: Description: + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT + 1 BASE_USB0_CLK Base clock for USB0 + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, + SPI, and SGPIO + 3 BASE_USB1_CLK Base clock for USB1 + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core + and APB peripheral blocks #0 and #2 + 5 BASE_SPIFI_CLK Base clock for SPIFI + 6 BASE_SPI_CLK Base clock for SPI + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 +11 BASE_LCD_CLK Base clock for LCD +12 BASE_ADCHS_CLK Base clock for ADCHS +13 BASE_SDIO_CLK Base clock for SD/MMC +14 BASE_SSP0_CLK Base clock for SSP0 +15 BASE_SSP1_CLK Base clock for SSP1 +16 BASE_UART0_CLK Base clock for UART0 +17 BASE_UART1_CLK Base clock for UART1 +18 BASE_UART2_CLK Base clock for UART2 +19 BASE_UART3_CLK Base clock for UART3 +20 BASE_OUT_CLK Base clock for CLKOUT pin +24-21 - Reserved +25 BASE_AUDIO_CLK Base clock for audio system (I2S) +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output + +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. +BASE_ADCHS_CLK is only available on LPC4370. + + +Example board file: + +/ { + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; + }; + }; + + soc { + cgu: clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + /* A CGU and CCU clock consumer */ + lcdc: lcdc@40008000 { + ... + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + ... + }; + }; +}; diff --git a/dts/Bindings/clock/marvell,berlin.txt b/dts/Bindings/clock/marvell,berlin.txt new file mode 100644 index 0000000000..c611c495f3 --- /dev/null +++ b/dts/Bindings/clock/marvell,berlin.txt @@ -0,0 +1,31 @@ +Device Tree Clock bindings for Marvell Berlin + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Clock related registers are spread among the chip control registers. Berlin +clock node should be a sub-node of the chip controller node. Marvell Berlin2 +(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some +minor differences in features and register layout. + +Required properties: +- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" +- #clock-cells: must be 1 +- clocks: must be the input parent clock phandle +- clock-names: name of the input parent clock + Allowed clock-names for the reference clocks are + "refclk" for the SoCs oscillator input on all SoCs, + and SoC-specific input clocks for + BG2/BG2CD: "video_ext0" for the external video clock input + + +Example: + +chip_clk: clock { + compatible = "marvell,berlin2q-clk"; + + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; +}; diff --git a/dts/Bindings/clock/marvell,pxa1928.txt b/dts/Bindings/clock/marvell,pxa1928.txt new file mode 100644 index 0000000000..809c5a2d8d --- /dev/null +++ b/dts/Bindings/clock/marvell,pxa1928.txt @@ -0,0 +1,21 @@ +* Marvell PXA1928 Clock Controllers + +The PXA1928 clock subsystem generates and supplies clock to various +controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller +blocks called APMU, MPMU, and APBC roughly corresponding to internal buses. + +Required Properties: + +- compatible: should be one of the following. + - "marvell,pxa1928-apmu" - APMU controller compatible + - "marvell,pxa1928-mpmu" - MPMU controller compatible + - "marvell,pxa1928-apbc" - APBC controller compatible +- reg: physical base address of the clock controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Each clock is assigned an identifier and client nodes use the clock controller +phandle and this identifier to specify the clock which they consume. + +All these identifiers can be found in . diff --git a/dts/Bindings/clock/mvebu-gated-clock.txt b/dts/Bindings/clock/mvebu-gated-clock.txt index 31c7c0c1ce..660e64912c 100644 --- a/dts/Bindings/clock/mvebu-gated-clock.txt +++ b/dts/Bindings/clock/mvebu-gated-clock.txt @@ -19,6 +19,7 @@ ID Clock Peripheral 9 pex1 PCIe Cntrl 1 15 sata0 SATA Host 0 17 sdio SDHCI Host +23 crypto CESA (crypto engine) 25 tdm Time Division Mplx 28 ddr DDR Cntrl 30 sata1 SATA Host 0 diff --git a/dts/Bindings/clock/nvidia,tegra124-car.txt b/dts/Bindings/clock/nvidia,tegra124-car.txt index c6620bc967..7f02fb4ca4 100644 --- a/dts/Bindings/clock/nvidia,tegra124-car.txt +++ b/dts/Bindings/clock/nvidia,tegra124-car.txt @@ -20,15 +20,38 @@ Required properties : - #reset-cells : Should be 1. In clock consumers, this cell represents the bit number in the CAR's array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. +- nvidia,external-memory-controller : phandle of the EMC driver. + +The node should contain a "emc-timings" subnode for each supported RAM type (see +field RAM_CODE in register PMC_STRAPPING_OPT_A). + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set + is used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate to which this timing +relates. +- nvidia,parent-clock-frequency : Should contain the rate at which the current +parent of the EMC clock should be running at this timing. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names : Must include the following entries: + - emc-parent : the clock that should be the parent of the EMC clock at this +timing. Example SoC include file: / { - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra124-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; usb@c5004000 { @@ -62,4 +85,23 @@ Example board file: &tegra_car { clocks = <&clk_32k> <&osc>; }; + + clock@60006000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + }; + }; }; diff --git a/dts/Bindings/clock/qca,ath79-pll.txt b/dts/Bindings/clock/qca,ath79-pll.txt new file mode 100644 index 0000000000..e0fc2c11dd --- /dev/null +++ b/dts/Bindings/clock/qca,ath79-pll.txt @@ -0,0 +1,33 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller + +The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. + +Required Properties: +- compatible: has to be "qca,-cpu-intc" and one of the following + fallbacks: + - "qca,ar7100-pll" + - "qca,ar7240-pll" + - "qca,ar9130-pll" + - "qca,ar9330-pll" + - "qca,ar9340-pll" + - "qca,qca9550-pll" +- reg: Base address and size of the controllers memory area +- clock-names: Name of the input clock, has to be "ref" +- clocks: phandle of the external reference clock +- #clock-cells: has to be one + +Optional properties: +- clock-output-names: should be "cpu", "ddr", "ahb" + +Example: + + memory-controller@18050000 { + compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; + reg = <0x18050000 0x20>; + + clock-names = "ref"; + clocks = <&extosc>; + + #clock-cells = <1>; + clock-output-names = "cpu", "ddr", "ahb"; + }; diff --git a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt index 054f65f931..5ddb684186 100644 --- a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt +++ b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt @@ -10,9 +10,11 @@ Required Properties: - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks + - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks + - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - - "renesas,cpg-div6-clock" for generic DIV6 clocks + and "renesas,cpg-div6-clock" as a fallback. - reg: Base address and length of the memory resource used by the DIV6 clock - clocks: Reference to the parent clock(s); either one, four, or eight clocks must be specified. For clocks with multiple parents, invalid diff --git a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt index 0a80fa70ca..16ed181551 100644 --- a/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/dts/Bindings/clock/renesas,cpg-mstp-clocks.txt @@ -13,12 +13,14 @@ Required Properties: - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks + - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks + - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + and "renesas,cpg-mstp-clocks" as a fallback. - reg: Base address and length of the I/O mapped registers used by the MSTP clocks. The first register is the clock control register and is mandatory. The second register is the clock status register and is optional when not diff --git a/dts/Bindings/clock/renesas,h8300-div-clock.txt b/dts/Bindings/clock/renesas,h8300-div-clock.txt new file mode 100644 index 0000000000..36c2b52824 --- /dev/null +++ b/dts/Bindings/clock/renesas,h8300-div-clock.txt @@ -0,0 +1,24 @@ +* Renesas H8/300 divider clock + +Required Properties: + + - compatible: Must be "renesas,sh73a0-h8300-div-clock" + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - reg: Base address and length of the divide rate selector + + - renesas,width: bit width of selector + +Example +------- + + cclk: cclk { + compatible = "renesas,h8300-div-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee01b 2>; + renesas,width = <2>; + }; diff --git a/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt b/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt new file mode 100644 index 0000000000..500cdadbce --- /dev/null +++ b/dts/Bindings/clock/renesas,h8s2678-pll-clock.txt @@ -0,0 +1,23 @@ +Renesas H8S2678 PLL clock + +This device is Clock multiplyer + +Required Properties: + + - compatible: Must be "renesas,h8s2678-pll-clock" + + - clocks: Reference to the parent clocks + + - #clock-cells: Must be 0 + + - reg: Two rate selector (Multiply / Divide) register address + +Example +------- + + pllclk: pllclk { + compatible = "renesas,h8s2678-pll-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>, <0xfee045 2>; + }; diff --git a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index b02944fba9..56f111bd3e 100644 --- a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -10,7 +10,7 @@ Required Properties: - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG - - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG + and "renesas,rcar-gen2-cpg-clocks" as a fallback. - reg: Base address and length of the memory resource used by the CPG diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt index 98a2574925..b0f7ddb8cd 100644 --- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt +++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt @@ -7,7 +7,7 @@ Required Properties: - compatible: Must be one of - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG - - "renesas,rz-cpg-clocks" for the generic RZ CPG + and "renesas,rz-cpg-clocks" as a fallback. - reg: Base address and length of the memory resource used by the CPG - clocks: References to possible parent clocks. Order must match clock modes in the datasheet. For the r7s72100, this is extal, usb_x1. diff --git a/dts/Bindings/clock/st,stm32-rcc.txt b/dts/Bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000000..fee3205cdf --- /dev/null +++ b/dts/Bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (CRYP) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + }; diff --git a/dts/Bindings/clock/sunxi.txt b/dts/Bindings/clock/sunxi.txt index 4fa11af3d3..8a47b77abf 100644 --- a/dts/Bindings/clock/sunxi.txt +++ b/dts/Bindings/clock/sunxi.txt @@ -67,6 +67,7 @@ Required properties: "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 + "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 diff --git a/dts/Bindings/clock/ti,cdce925.txt b/dts/Bindings/clock/ti,cdce925.txt new file mode 100644 index 0000000000..4c7669ad68 --- /dev/null +++ b/dts/Bindings/clock/ti,cdce925.txt @@ -0,0 +1,42 @@ +Binding for TO CDCE925 programmable I2C clock synthesizers. + +Reference +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] http://www.ti.com/product/cdce925 + +The driver provides clock sources for each output Y1 through Y5. + +Required properties: + - compatible: Shall be "ti,cdce925" + - reg: I2C device address. + - clocks: Points to a fixed parent clock that provides the input frequency. + - #clock-cells: From common clock bindings: Shall be 1. + +Optional properties: + - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a + board, or to compensate for external influences. + +For both PLL1 and PLL2 an optional child node can be used to specify spread +spectrum clocking parameters for a board. + - spread-spectrum: SSC mode as defined in the data sheet. + - spread-spectrum-center: Use "centered" mode instead of "max" mode. When + present, the clock runs at the requested frequency on average. Otherwise + the requested frequency is the maximum value of the SCC range. + + +Example: + + clockgen: cdce925pw@64 { + compatible = "cdce925"; + reg = <0x64>; + clocks = <&xtal_27Mhz>; + #clock-cells = <1>; + xtal-load-pf = <5>; + /* PLL options to get SSC 1% centered */ + PLL2 { + spread-spectrum = <4>; + spread-spectrum-center; + }; + }; diff --git a/dts/Bindings/clock/zx296702-clk.txt b/dts/Bindings/clock/zx296702-clk.txt new file mode 100644 index 0000000000..750442b655 --- /dev/null +++ b/dts/Bindings/clock/zx296702-clk.txt @@ -0,0 +1,35 @@ +Device Tree Clock bindings for ZTE zx296702 + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "zte,zx296702-topcrm-clk": + zx296702 top clock selection, divider and gating + + "zte,zx296702-lsp0crpm-clk" and + "zte,zx296702-lsp1crpm-clk": + zx296702 device level clock selection and gating + +- reg: Address and length of the register set + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h +for the full list of zx296702 clock IDs. + + +topclk: topcrm@0x09800000 { + compatible = "zte,zx296702-topcrm-clk"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; +}; + +uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART0_PCLK>; + status = "disabled"; +}; diff --git a/dts/Bindings/crypto/fsl-sec2.txt b/dts/Bindings/crypto/fsl-sec2.txt index 38988ef133..f0d926bf9f 100644 --- a/dts/Bindings/crypto/fsl-sec2.txt +++ b/dts/Bindings/crypto/fsl-sec2.txt @@ -1,9 +1,11 @@ -Freescale SoC SEC Security Engines versions 2.x-3.x +Freescale SoC SEC Security Engines versions 1.x-2.x-3.x Required properties: - compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" + SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) + e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) + warning: SEC1 and SEC2 are mutually exclusive - reg : Offset and length of the register set for the device - interrupts : the SEC's interrupt number - fsl,num-channels : An integer representing the number of channels diff --git a/dts/Bindings/crypto/marvell-cesa.txt b/dts/Bindings/crypto/marvell-cesa.txt new file mode 100644 index 0000000000..c6c6a4a045 --- /dev/null +++ b/dts/Bindings/crypto/marvell-cesa.txt @@ -0,0 +1,45 @@ +Marvell Cryptographic Engines And Security Accelerator + +Required properties: +- compatible: should be one of the following string + "marvell,orion-crypto" + "marvell,kirkwood-crypto" + "marvell,dove-crypto" + "marvell,armada-370-crypto" + "marvell,armada-xp-crypto" + "marvell,armada-375-crypto" + "marvell,armada-38x-crypto" +- reg: base physical address of the engine and length of memory mapped + region. Can also contain an entry for the SRAM attached to the CESA, + but this representation is deprecated and marvell,crypto-srams should + be used instead +- reg-names: "regs". Can contain an "sram" entry, but this representation + is deprecated and marvell,crypto-srams should be used instead +- interrupts: interrupt number +- clocks: reference to the crypto engines clocks. This property is not + required for orion and kirkwood platforms +- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine + id. + This property is not required for the orion and kirkwoord + platforms. + "cesazX" clocks are not required on armada-370 platforms +- marvell,crypto-srams: phandle to crypto SRAM definitions + +Optional properties: +- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not + specified the whole SRAM is used (2KB) + + +Examples: + + crypto@90000 { + compatible = "marvell,armada-xp-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <48>, <49>; + clocks = <&gateclk 23>, <&gateclk 23>; + clock-names = "cesa0", "cesa1"; + marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; + marvell,crypto-sram-size = <0x600>; + status = "okay"; + }; diff --git a/dts/Bindings/crypto/mv_cesa.txt b/dts/Bindings/crypto/mv_cesa.txt index 47229b1a59..c0c35f0033 100644 --- a/dts/Bindings/crypto/mv_cesa.txt +++ b/dts/Bindings/crypto/mv_cesa.txt @@ -1,20 +1,33 @@ Marvell Cryptographic Engines And Security Accelerator Required properties: -- compatible : should be "marvell,orion-crypto" -- reg : base physical address of the engine and length of memory mapped - region, followed by base physical address of sram and its memory - length -- reg-names : "regs" , "sram"; -- interrupts : interrupt number +- compatible: should be one of the following string + "marvell,orion-crypto" + "marvell,kirkwood-crypto" + "marvell,dove-crypto" +- reg: base physical address of the engine and length of memory mapped + region. Can also contain an entry for the SRAM attached to the CESA, + but this representation is deprecated and marvell,crypto-srams should + be used instead +- reg-names: "regs". Can contain an "sram" entry, but this representation + is deprecated and marvell,crypto-srams should be used instead +- interrupts: interrupt number +- clocks: reference to the crypto engines clocks. This property is only + required for Dove platforms +- marvell,crypto-srams: phandle to crypto SRAM definitions + +Optional properties: +- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not + specified the whole SRAM is used (2KB) Examples: crypto@30000 { compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0x4000000 0x800>; - reg-names = "regs" , "sram"; + reg = <0x30000 0x10000>; + reg-names = "regs"; interrupts = <22>; + marvell,crypto-srams = <&crypto_sram>; + marvell,crypto-sram-size = <0x600>; status = "okay"; }; diff --git a/dts/Bindings/dma/dma.txt b/dts/Bindings/dma/dma.txt index 82104271e7..6312fb00ce 100644 --- a/dts/Bindings/dma/dma.txt +++ b/dts/Bindings/dma/dma.txt @@ -31,6 +31,34 @@ Example: dma-requests = <127>; }; +* DMA router + +DMA routers are transparent IP blocks used to route DMA request lines from +devices to the DMA controller. Some SoCs (like TI DRA7x) have more peripherals +integrated with DMA requests than what the DMA controller can handle directly. + +Required property: +- dma-masters: phandle of the DMA controller or list of phandles for + the DMA controllers the router can direct the signal to. +- #dma-cells: Must be at least 1. Used to provide DMA router specific + information. See DMA client binding below for more + details. + +Optional properties: +- dma-requests: Number of incoming request lines the router can handle. +- In the node pointed by the dma-masters: + - dma-requests: The router driver might need to look for this in order + to configure the routing. + +Example: + sdma_xbar: dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; * DMA client diff --git a/dts/Bindings/dma/mv-xor.txt b/dts/Bindings/dma/mv-xor.txt index 7c6cb7fcec..cc29c35266 100644 --- a/dts/Bindings/dma/mv-xor.txt +++ b/dts/Bindings/dma/mv-xor.txt @@ -1,7 +1,7 @@ * Marvell XOR engines Required properties: -- compatible: Should be "marvell,orion-xor" +- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor" - reg: Should contain registers location and length (two sets) the first set is the low registers, the second set the high registers for the XOR engine. diff --git a/dts/Bindings/dma/sirfsoc-dma.txt b/dts/Bindings/dma/sirfsoc-dma.txt index ecbc96ad36..ccd52d6a23 100644 --- a/dts/Bindings/dma/sirfsoc-dma.txt +++ b/dts/Bindings/dma/sirfsoc-dma.txt @@ -3,7 +3,8 @@ See dma.txt first Required properties: -- compatible: Should be "sirf,prima2-dmac" or "sirf,marco-dmac" +- compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or + "sirf,atlas7-dmac-v2" - reg: Should contain DMA registers location and length. - interrupts: Should contain one interrupt shared by all channel - #dma-cells: must be <1>. used to represent the number of integer diff --git a/dts/Bindings/dma/sun6i-dma.txt b/dts/Bindings/dma/sun6i-dma.txt index 9cdcba24d7..d13c136cef 100644 --- a/dts/Bindings/dma/sun6i-dma.txt +++ b/dts/Bindings/dma/sun6i-dma.txt @@ -4,7 +4,10 @@ This driver follows the generic DMA bindings defined in dma.txt. Required properties: -- compatible: Must be "allwinner,sun6i-a31-dma" or "allwinner,sun8i-a23-dma" +- compatible: Must be one of + "allwinner,sun6i-a31-dma" + "allwinner,sun8i-a23-dma" + "allwinner,sun8i-h3-dma" - reg: Should contain the registers base address and length - interrupts: Should contain a reference to the interrupt used by this device - clocks: Should contain a reference to the parent AHB clock diff --git a/dts/Bindings/dma/ti-dma-crossbar.txt b/dts/Bindings/dma/ti-dma-crossbar.txt new file mode 100644 index 0000000000..63a48928f3 --- /dev/null +++ b/dts/Bindings/dma/ti-dma-crossbar.txt @@ -0,0 +1,52 @@ +Texas Instruments DMA Crossbar (DMA request router) + +Required properties: +- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar +- reg: Memory map for accessing module +- #dma-cells: Should be set to <1>. + Clients should use the crossbar request number (input) +- dma-requests: Number of DMA requests the crossbar can receive +- dma-masters: phandle pointing to the DMA controller + +The DMA controller node need to have the following poroperties: +- dma-requests: Number of DMA requests the controller can handle + +Optional properties: +- ti,dma-safe-map: Safe routing value for unused request lines + +Example: + +/* DMA controller */ +sdma: dma-controller@4a056000 { + compatible = "ti,omap4430-sdma"; + reg = <0x4a056000 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; +}; + +/* DMA crossbar */ +sdma_xbar: dma-router@4a002b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0x4a002b78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; +}; + +/* DMA client */ +uart1: serial@4806a000 { + compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; + dma-names = "tx", "rx"; +}; diff --git a/dts/Bindings/drm/msm/dsi.txt b/dts/Bindings/drm/msm/dsi.txt new file mode 100644 index 0000000000..cd8fe6cf53 --- /dev/null +++ b/dts/Bindings/drm/msm/dsi.txt @@ -0,0 +1,120 @@ +Qualcomm Technologies Inc. adreno/snapdragon DSI output + +DSI Controller: +Required properties: +- compatible: + * "qcom,mdss-dsi-ctrl" +- reg: Physical base address and length of the registers of controller +- reg-names: The names of register regions. The following regions are required: + * "dsi_ctrl" +- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should + be 0 or 1, since we have 2 DSI controllers at most for now. +- interrupts: The interrupt signal from the DSI block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "bus_clk" + * "byte_clk" + * "core_clk" + * "core_mmss_clk" + * "iface_clk" + * "mdp_core_clk" + * "pixel_clk" +- vdd-supply: phandle to vdd regulator device node +- vddio-supply: phandle to vdd-io regulator device node +- vdda-supply: phandle to vdda regulator device node +- qcom,dsi-phy: phandle to DSI PHY device node + +Optional properties: +- panel@0: Node of panel connected to this DSI controller. + See files in Documentation/devicetree/bindings/panel/ for each supported + panel. +- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. +- qcom,master-panel: Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. +- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. +- interrupt-parent: phandle to the MDP block if the interrupt signal is routed + through MDP block + +DSI PHY: +Required properties: +- compatible: Could be the following + * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-lp" +- reg: Physical base address and length of the registers of PLL, PHY and PHY + regulator +- reg-names: The names of register regions. The following regions are required: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_regulator" +- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should + be 0 or 1, since we have 2 DSI PHYs at most for now. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "iface_clk" +- vddio-supply: phandle to vdd-io regulator device node + +Example: + mdss_dsi0: qcom,mdss_dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus_clk", + "byte_clk", + "core_clk", + "core_mmss_clk", + "iface_clk", + "mdp_core_clk", + "pixel_clk"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,dual-panel-mode; + qcom,master-panel; + qcom,sync-dual-panel; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface_clk"; + clocks = <&mmcc MDSS_AHB_CLK>; + vddio-supply = <&pma8084_l12>; + }; diff --git a/dts/Bindings/drm/msm/edp.txt b/dts/Bindings/drm/msm/edp.txt new file mode 100644 index 0000000000..3a20f6ea58 --- /dev/null +++ b/dts/Bindings/drm/msm/edp.txt @@ -0,0 +1,60 @@ +Qualcomm Technologies Inc. adreno/snapdragon eDP output + +Required properties: +- compatible: + * "qcom,mdss-edp" +- reg: Physical base address and length of the registers of controller and PLL +- reg-names: The names of register regions. The following regions are required: + * "edp" + * "pll_base" +- interrupts: The interrupt signal from the eDP block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "core_clk" + * "iface_clk" + * "mdp_core_clk" + * "pixel_clk" + * "link_clk" +- #clock-cells: The value should be 1. +- vdda-supply: phandle to vdda regulator device node +- lvl-vdd-supply: phandle to regulator device node which is used to supply power + to HPD receiving chip +- panel-en-gpios: GPIO pin to supply power to panel. +- panel-hpd-gpios: GPIO pin used for eDP hpd. + + +Optional properties: +- interrupt-parent: phandle to the MDP block if the interrupt signal is routed + through MDP block + +Example: + mdss_edp: qcom,mdss_edp@fd923400 { + compatible = "qcom,mdss-edp"; + reg-names = + "edp", + "pll_base"; + reg = <0xfd923400 0x700>, + <0xfd923a00 0xd4>; + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "core_clk", + "pixel_clk", + "iface_clk", + "link_clk", + "mdp_core_clk"; + clocks = + <&mmcc MDSS_EDPAUX_CLK>, + <&mmcc MDSS_EDPPIXEL_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_EDPLINK_CLK>, + <&mmcc MDSS_MDP_CLK>; + #clock-cells = <1>; + vdda-supply = <&pma8084_l12>; + lvl-vdd-supply = <&lvl_vreg>; + panel-en-gpios = <&tlmm 137 0>; + panel-hpd-gpios = <&tlmm 103 0>; + }; diff --git a/dts/Bindings/drm/msm/hdmi.txt b/dts/Bindings/drm/msm/hdmi.txt index a29a55f3d9..c43aa53deb 100644 --- a/dts/Bindings/drm/msm/hdmi.txt +++ b/dts/Bindings/drm/msm/hdmi.txt @@ -20,6 +20,9 @@ Required properties: Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-1: the "sleep" pinctrl state Example: @@ -44,5 +47,8 @@ Example: qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; core-vdda-supply = <&pm8921_hdmi_mvs>; hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; }; }; diff --git a/dts/Bindings/drm/tilcdc/slave.txt b/dts/Bindings/drm/tilcdc/slave.txt deleted file mode 100644 index 3d2c52460d..0000000000 --- a/dts/Bindings/drm/tilcdc/slave.txt +++ /dev/null @@ -1,18 +0,0 @@ -Device-Tree bindings for tilcdc DRM encoder slave output driver - -Required properties: - - compatible: value should be "ti,tilcdc,slave". - - i2c: the phandle for the i2c device the encoder slave is connected to - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - -Example: - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - }; diff --git a/dts/Bindings/drm/tilcdc/tilcdc.txt b/dts/Bindings/drm/tilcdc/tilcdc.txt index fff10da5e9..2136ee81e0 100644 --- a/dts/Bindings/drm/tilcdc/tilcdc.txt +++ b/dts/Bindings/drm/tilcdc/tilcdc.txt @@ -18,6 +18,12 @@ Optional properties: - max-pixelclock: The maximum pixel clock that can be supported by the lcd controller in KHz. +Optional nodes: + + - port/ports: to describe a connection to an external encoder. The + binding follows Documentation/devicetree/bindings/graph.txt and + suppors a single port with a single endpoint. + Example: fb: fb@4830e000 { @@ -26,4 +32,25 @@ Example: interrupt-parent = <&intc>; interrupts = <36>; ti,hwmods = "lcdc"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; + }; + + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; }; diff --git a/dts/Bindings/edac/apm-xgene-edac.txt b/dts/Bindings/edac/apm-xgene-edac.txt new file mode 100644 index 0000000000..78edb80002 --- /dev/null +++ b/dts/Bindings/edac/apm-xgene-edac.txt @@ -0,0 +1,79 @@ +* APM X-Gene SoC EDAC node + +EDAC node is defined to describe on-chip error detection and correction. +The follow error types are supported: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + +The following section describes the EDAC DT node binding. + +Required properties: +- compatible : Shall be "apm,xgene-edac". +- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. +- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. +- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. +- regmap-efuse : Regmap of the PMD efuse resource. +- reg : First resource shall be the CPU bus (PCP) resource. +- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error + IRQ(s). + +Required properties for memory controller subnode: +- compatible : Shall be "apm,xgene-edac-mc". +- reg : First resource shall be the memory controller unit + (MCU) resource. +- memory-controller : Instance number of the memory controller. + +Required properties for PMD subnode: +- compatible : Shall be "apm,xgene-edac-pmd" or + "apm,xgene-edac-pmd-v2". +- reg : First resource shall be the PMD resource. +- pmd-controller : Instance number of the PMD controller. + +Example: + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + efuse: efuse@1054a000 { + compatible = "apm,xgene-efuse", "syscon"; + reg = <0x0 0x1054a000 0x0 0x20>; + }; + + edac@78800000 { + compatible = "apm,xgene-edac"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + reg = <0x0 0x78800000 0x0 0x100>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + }; diff --git a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt b/dts/Bindings/fuse/nvidia,tegra20-fuse.txt index 23e1d31941..41372d4411 100644 --- a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt +++ b/dts/Bindings/fuse/nvidia,tegra20-fuse.txt @@ -29,7 +29,7 @@ Example: fuse@7000f800 { compatible = "nvidia,tegra20-efuse"; - reg = <0x7000F800 0x400>, + reg = <0x7000f800 0x400>, <0x70000000 0x400>; clocks = <&tegra_car TEGRA20_CLK_FUSE>; clock-names = "fuse"; diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt new file mode 100644 index 0000000000..435f1bcca3 --- /dev/null +++ b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt @@ -0,0 +1,65 @@ +Broadcom STB "UPG GIO" GPIO controller + +The controller's registers are organized as sets of eight 32-bit +registers with each set controlling a bank of up to 32 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: + +- compatible: + Must be "brcm,brcmstb-gpio" + +- reg: + Define the base and range of the I/O address space containing + the brcmstb GPIO controller registers + +- #gpio-cells: + Should be <2>. The first cell is the pin number (within the controller's + pin space), and the second is used for the following: + bit[0]: polarity (0 for active-high, 1 for active-low) + +- gpio-controller: + Specifies that the node is a GPIO controller. + +- brcm,gpio-bank-widths: + Number of GPIO lines for each bank. Number of elements must + correspond to number of banks suggested by the 'reg' property. + +Optional properties: + +- interrupts: + The interrupt shared by all GPIO lines for this controller. + +- interrupt-parent: + phandle of the parent interrupt controller + +- #interrupt-cells: + Should be <2>. The first cell is the GPIO number, the second should specify + flags. The following subset of flags is supported: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +- interrupt-controller: + Marks the device node as an interrupt controller + +- interrupt-names: + The name of the IRQ resource used by this controller + +Example: + upg_gio: gpio@f040a700 { + #gpio-cells = <0x2>; + #interrupt-cells = <0x2>; + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + gpio-controller; + interrupt-controller; + reg = <0xf040a700 0x80>; + interrupt-parent = <0xf>; + interrupts = <0x6>; + interrupt-names = "upg_gio"; + brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>; + }; diff --git a/dts/Bindings/gpio/gpio-ath79.txt b/dts/Bindings/gpio/gpio-ath79.txt new file mode 100644 index 0000000000..c522851017 --- /dev/null +++ b/dts/Bindings/gpio/gpio-ath79.txt @@ -0,0 +1,38 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller + +Required properties: +- compatible: has to be "qca,-gpio" and one of the following + fallbacks: + - "qca,ar7100-gpio" + - "qca,ar9340-gpio" +- reg: Base address and size of the controllers memory area +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters. +- ngpios: Should be set to the number of GPIOs available on the SoC. + +Optional properties: +- interrupt-parent: phandle of the parent interrupt controller. +- interrupts: Interrupt specifier for the controllers interrupt. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 2 + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + + gpio@18040000 { + compatible = "qca,ar9132-gpio", "qca,ar7100-gpio"; + reg = <0x18040000 0x30>; + interrupts = <2>; + + ngpios = <22>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/dts/Bindings/gpio/gpio-atlas7.txt b/dts/Bindings/gpio/gpio-atlas7.txt new file mode 100644 index 0000000000..d7e123fc90 --- /dev/null +++ b/dts/Bindings/gpio/gpio-atlas7.txt @@ -0,0 +1,50 @@ +CSR SiRFatlas7 GPIO controller bindings + +Required properties: +- compatible : "sirf,atlas7-gpio" +- reg : Address range of the pinctrl registers +- interrupts : Interrupts used by every GPIO group +- gpio-banks : How many gpio banks on this controller +- gpio-controller : Indicates this device is a GPIO controller +- interrupt-controller : Marks the device node as an interrupt controller + +The GPIO controller also acts as an interrupt controller. It uses the default +two cells specifier as described in Documentation/devicetree/bindings/ +interrupt-controller/interrupts.txt. + +Example: + + gpio_0: gpio_mediam@17040000 { + compatible = "sirf,atlas7-gpio"; + reg = <0x17040000 0x1000>; + interrupts = <0 13 0>, <0 14 0>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + gpio-controller; + interrupt-controller; + + gpio-banks = <2>; + gpio-ranges = <&pinctrl 0 0 0>, + <&pinctrl 32 0 0>; + gpio-ranges-group-names = "lvds_gpio_grp", + "uart_nand_gpio_grp"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + gpios = <&gpio_1 15 0>; + ... + }; + + led2 { + gpios = <&gpio_2 34 0>; + ... + }; + }; + +Please refer to gpio.txt in this directory for details of the common +gpio properties used by devices. diff --git a/dts/Bindings/gpio/gpio-etraxfs.txt b/dts/Bindings/gpio/gpio-etraxfs.txt new file mode 100644 index 0000000000..abf4db736c --- /dev/null +++ b/dts/Bindings/gpio/gpio-etraxfs.txt @@ -0,0 +1,21 @@ +Axis ETRAX FS General I/O controller bindings + +Required properties: + +- compatible: + - "axis,etraxfs-gio" +- reg: Physical base address and length of the controller's registers. +- #gpio-cells: Should be 3 + - The first cell is the gpio offset number. + - The second cell is reserved and is currently unused. + - The third cell is the port number (hex). +- gpio-controller: Marks the device node as a GPIO controller. + +Example: + + gio: gpio@b001a000 { + compatible = "axis,etraxfs-gio"; + reg = <0xb001a000 0x1000>; + gpio-controller; + #gpio-cells = <3>; + }; diff --git a/dts/Bindings/gpio/gpio-xlp.txt b/dts/Bindings/gpio/gpio-xlp.txt new file mode 100644 index 0000000000..262ee4ddf2 --- /dev/null +++ b/dts/Bindings/gpio/gpio-xlp.txt @@ -0,0 +1,47 @@ +Netlogic XLP Family GPIO +======================== + +This GPIO driver is used for following Netlogic XLP SoCs: + XLP832, XLP316, XLP208, XLP980, XLP532 + +Required properties: +------------------- + +- compatible: Should be one of the following: + - "netlogic,xlp832-gpio": For Netlogic XLP832 + - "netlogic,xlp316-gpio": For Netlogic XLP316 + - "netlogic,xlp208-gpio": For Netlogic XLP208 + - "netlogic,xlp980-gpio": For Netlogic XLP980 + - "netlogic,xlp532-gpio": For Netlogic XLP532 +- reg: Physical base address and length of the controller's registers. +- #gpio-cells: Should be two. The first cell is the pin number and the second + cell is used to specify optional parameters (currently unused). +- gpio-controller: Marks the device node as a GPIO controller. +- nr-gpios: Number of GPIO pins supported by the controller. +- interrupt-cells: Should be two. The first cell is the GPIO Number. The + second cell is used to specify flags. The following subset of flags is + supported: + - trigger type: + 1 = low to high edge triggered. + 2 = high to low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. +- interrupts: Interrupt number for this device. +- interrupt-parent: phandle of the parent interrupt controller. +- interrupt-controller: Identifies the node as an interrupt controller. + +Example: + + gpio: xlp_gpio@34000 { + compatible = "netlogic,xlp316-gpio"; + reg = <0 0x34100 0x1000 + 0 0x35100 0x1000>; + #gpio-cells = <2>; + gpio-controller; + nr-gpios = <57>; + + #interrupt-cells = <2>; + interrupt-parent = <&pic>; + interrupts = <39>; + interrupt-controller; + }; diff --git a/dts/Bindings/gpio/gpio-zynq.txt b/dts/Bindings/gpio/gpio-zynq.txt index 986371a4be..db4c6a663c 100644 --- a/dts/Bindings/gpio/gpio-zynq.txt +++ b/dts/Bindings/gpio/gpio-zynq.txt @@ -6,7 +6,7 @@ Required properties: - First cell is the GPIO line number - Second cell is used to specify optional parameters (unused) -- compatible : Should be "xlnx,zynq-gpio-1.0" +- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" - clocks : Clock specifier (see clock bindings for details) - gpio-controller : Marks the device node as a GPIO controller. - interrupts : Interrupt specifier (see interrupt bindings for diff --git a/dts/Bindings/gpio/nxp,lpc1850-gpio.txt b/dts/Bindings/gpio/nxp,lpc1850-gpio.txt new file mode 100644 index 0000000000..eb7cdd69e1 --- /dev/null +++ b/dts/Bindings/gpio/nxp,lpc1850-gpio.txt @@ -0,0 +1,39 @@ +NXP LPC18xx/43xx GPIO controller Device Tree Bindings +----------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-gpio" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Should be two + - First cell is the GPIO line number + - Second cell is used to specify polarity + +Optional properties: +- gpio-ranges : Mapping between GPIO and pinctrl + +Example: +#define LPC_GPIO(port, pin) (port * 32 + pin) +#define LPC_PIN(port, pin) (0x##port * 32 + pin) + +gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + ... + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; +}; + +gpio_joystick { + compatible = "gpio-keys-polled"; + ... + + button@0 { + ... + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; +}; diff --git a/dts/Bindings/h8300/cpu.txt b/dts/Bindings/h8300/cpu.txt new file mode 100644 index 0000000000..70cd58608f --- /dev/null +++ b/dts/Bindings/h8300/cpu.txt @@ -0,0 +1,13 @@ +* H8/300 CPU bindings + +Required properties: + +- compatible: Compatible property value should be "renesas,h8300". +- clock-frequency: Contains the clock frequency for CPU, in Hz. + +Example: + + cpu@0 { + compatible = "renesas,h8300"; + clock-frequency = <20000000>; + }; diff --git a/dts/Bindings/hwlock/hwlock.txt b/dts/Bindings/hwlock/hwlock.txt new file mode 100644 index 0000000000..085d1f5c91 --- /dev/null +++ b/dts/Bindings/hwlock/hwlock.txt @@ -0,0 +1,59 @@ +Generic hwlock bindings +======================= + +Generic bindings that are common to all the hwlock platform specific driver +implementations. + +Please also look through the individual platform specific hwlock binding +documentations for identifying any additional properties specific to that +platform. + +hwlock providers: +================= + +Required properties: +- #hwlock-cells: Specifies the number of cells needed to represent a + specific lock. + +hwlock users: +============= + +Consumers that require specific hwlock(s) should specify them using the +property "hwlocks", and an optional "hwlock-names" property. + +Required properties: +- hwlocks: List of phandle to a hwlock provider node and an + associated hwlock args specifier as indicated by + #hwlock-cells. The list can have just a single hwlock + or multiple hwlocks, with each hwlock represented by + a phandle and a corresponding args specifier. + +Optional properties: +- hwlock-names: List of hwlock name strings defined in the same order + as the hwlocks, with one name per hwlock. Consumers can + use the hwlock-names to match and get a specific hwlock. + + +1. Example of a node using a single specific hwlock: + +The following example has a node requesting a hwlock in the bank defined by +the node hwlock1. hwlock1 is a hwlock provider with an argument specifier +of length 1. + + node { + ... + hwlocks = <&hwlock1 2>; + ... + }; + +2. Example of a node using multiple specific hwlocks: + +The following example has a node requesting two hwlocks, a hwlock within +the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another +hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2. + + node { + ... + hwlocks = <&hwlock1 2>, <&hwlock2 0 3>; + ... + }; diff --git a/dts/Bindings/hwlock/omap-hwspinlock.txt b/dts/Bindings/hwlock/omap-hwspinlock.txt new file mode 100644 index 0000000000..2c9804f4f4 --- /dev/null +++ b/dts/Bindings/hwlock/omap-hwspinlock.txt @@ -0,0 +1,26 @@ +OMAP4+ HwSpinlock Driver +======================== + +Required properties: +- compatible: Should be "ti,omap4-hwspinlock" for + OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs +- reg: Contains the hwspinlock module register address space + (base address and length) +- ti,hwmods: Name of the hwmod associated with the hwspinlock device +- #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a + 0-indexed relative hwlock number as the argument + specifier value for requesting a specific hwspinlock + within a hwspinlock bank. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example: + +/* OMAP4 */ +hwspinlock: spinlock@4a0f6000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x4a0f6000 0x1000>; + ti,hwmods = "spinlock"; + #hwlock-cells = <1>; +}; diff --git a/dts/Bindings/hwlock/qcom-hwspinlock.txt b/dts/Bindings/hwlock/qcom-hwspinlock.txt new file mode 100644 index 0000000000..4563f52455 --- /dev/null +++ b/dts/Bindings/hwlock/qcom-hwspinlock.txt @@ -0,0 +1,39 @@ +Qualcomm Hardware Mutex Block: + +The hardware block provides mutexes utilized between different processors on +the SoC as part of the communication protocol used by these processors. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,sfpb-mutex", + "qcom,tcsr-mutex" + +- syscon: + Usage: required + Value type: + Definition: one cell containing: + syscon phandle + offset of the hwmutex block within the syscon + stride of the hwmutex registers + +- #hwlock-cells: + Usage: required + Value type: + Definition: must be 1, the specified cell represent the lock id + (hwlock standard property, see hwlock.txt) + +Example: + + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + hwlock@fd484000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; diff --git a/dts/Bindings/hwlock/sirf,hwspinlock.txt b/dts/Bindings/hwlock/sirf,hwspinlock.txt new file mode 100644 index 0000000000..9bb1240a68 --- /dev/null +++ b/dts/Bindings/hwlock/sirf,hwspinlock.txt @@ -0,0 +1,28 @@ +SIRF Hardware spinlock device Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "sirf,hwspinlock" + +- reg : the register address of hwspinlock + +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwlock { + compatible = "sirf,hwspinlock"; + reg = <0x13240000 0x00010000>; + #hwlock-cells = <1>; + }; + +Example of hwlock users: + node { + ... + hwlocks = <&hwlock 2>; + ... + }; diff --git a/dts/Bindings/hwmon/ntc_thermistor.txt b/dts/Bindings/hwmon/ntc_thermistor.txt index fcca8e744f..a04a80f9cc 100644 --- a/dts/Bindings/hwmon/ntc_thermistor.txt +++ b/dts/Bindings/hwmon/ntc_thermistor.txt @@ -9,6 +9,7 @@ Requires node properties: "murata,ncp21wb473" "murata,ncp03wb473" "murata,ncp15wl333" + "murata,ncp03wf104" /* Usage of vendor name "ntc" is deprecated */ "ntc,ncp15wb473" diff --git a/dts/Bindings/i2c/i2c-at91.txt b/dts/Bindings/i2c/i2c-at91.txt index 388f0a275f..6e81dc153f 100644 --- a/dts/Bindings/i2c/i2c-at91.txt +++ b/dts/Bindings/i2c/i2c-at91.txt @@ -2,8 +2,8 @@ I2C for Atmel platforms Required properties : - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", - "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c" - or "atmel,at91sam9x5-i2c" + "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", + "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c" - reg: physical base address of the controller and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -13,6 +13,10 @@ Required properties : Optional properties: - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 +- dmas: A list of two dma specifiers, one for each entry in dma-names. +- dma-names: should contain "tx" and "rx". +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO + capable I2C controllers. - Child nodes conforming to i2c bus binding Examples : @@ -32,3 +36,25 @@ i2c0: i2c@fff84000 { pagesize = <128>; } } + +i2c0: i2c@f8034600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8034600 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(11)>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(12)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0>; + atmel,fifo-size = <16>; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; +}; diff --git a/dts/Bindings/i2c/i2c-brcmstb.txt b/dts/Bindings/i2c/i2c-brcmstb.txt new file mode 100644 index 0000000000..d6f724efdc --- /dev/null +++ b/dts/Bindings/i2c/i2c-brcmstb.txt @@ -0,0 +1,28 @@ +Broadcom stb bsc iic master controller + +Required properties: + +- compatible: should be "brcm,brcmstb-i2c" +- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz + valid values are 375000, 390000, 187500, 200000 + 93750, 97500, 46875 and 50000 +- reg: specifies the base physical address and size of the registers + +Optional properties : + +- interrupt-parent: specifies the phandle to the parent interrupt controller + this one is cascaded from +- interrupts: specifies the interrupt number, the irq line to be used +- interrupt-names: Interrupt name string + +Example: + +bsca: i2c@f0406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&irq0_intc>; + reg = <0xf0406200 0x58>; + interrupts = <0x18>; + interrupt-names = "upg_bsca"; +}; + diff --git a/dts/Bindings/i2c/i2c-mt6577.txt b/dts/Bindings/i2c/i2c-mt6577.txt new file mode 100644 index 0000000000..0ce6fa3242 --- /dev/null +++ b/dts/Bindings/i2c/i2c-mt6577.txt @@ -0,0 +1,41 @@ +* Mediatek's I2C controller + +The Mediatek's I2C controller is used to interface with I2C devices. + +Required properties: + - compatible: value should be either of the following. + (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c. + (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c. + (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c. + (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c. + (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c. + - reg: physical base address of the controller and dma base, length of memory + mapped region. + - interrupts: interrupt number to the cpu. + - clock-div: the fixed value for frequency divider of clock source in i2c + module. Each IC may be different. + - clocks: clock name from clock manager + - clock-names: Must include "main" and "dma", if enable have-pmic need include + "pmic" extra. + +Optional properties: + - clock-frequency: Frequency in Hz of the bus when transfer, the default value + is 100000. + - mediatek,have-pmic: platform can control i2c form special pmic side. + Only mt6589 and mt8135 support this feature. + - mediatek,use-push-pull: IO config use push-pull mode. + +Example: + + i2c0: i2c@1100d000 { + compatible = "mediatek,mt6577-i2c"; + reg = <0x1100d000 0x70>, + <0x11000300 0x80>; + interrupts = ; + clock-frequency = <400000>; + mediatek,have-pmic; + clock-div = <16>; + clocks = <&i2c0_ck>, <&ap_dma_ck>; + clock-names = "main", "dma"; + }; + diff --git a/dts/Bindings/i2c/i2c-xgene-slimpro.txt b/dts/Bindings/i2c/i2c-xgene-slimpro.txt new file mode 100644 index 0000000000..f6b2c20cfb --- /dev/null +++ b/dts/Bindings/i2c/i2c-xgene-slimpro.txt @@ -0,0 +1,15 @@ +APM X-Gene SLIMpro Mailbox I2C Driver + +An I2C controller accessed over the "SLIMpro" mailbox. + +Required properties : + + - compatible : should be "apm,xgene-slimpro-i2c" + - mboxes : use the label reference for the mailbox as the first parameter. + The second parameter is the channel number. + +Example : + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; diff --git a/dts/Bindings/i2c/trivial-devices.txt b/dts/Bindings/i2c/trivial-devices.txt index ad0c4ac916..00f8652e19 100644 --- a/dts/Bindings/i2c/trivial-devices.txt +++ b/dts/Bindings/i2c/trivial-devices.txt @@ -19,8 +19,7 @@ adi,adt7475 +/-1C TDM Extended Temp Range I.C adi,adt7476 +/-1C TDM Extended Temp Range I.C adi,adt7490 +/-1C TDM Extended Temp Range I.C adi,adxl345 Three-Axis Digital Accelerometer -adi,adxl346 Three-Axis Digital Accelerometer -adi,adxl34x Three-Axis Digital Accelerometer +adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) at,24c08 i2c serial eeprom (24cxx) atmel,24c00 i2c serial eeprom (24cxx) atmel,24c01 i2c serial eeprom (24cxx) diff --git a/dts/Bindings/iio/adc/berlin2_adc.txt b/dts/Bindings/iio/adc/berlin2_adc.txt new file mode 100644 index 0000000000..908334c6b0 --- /dev/null +++ b/dts/Bindings/iio/adc/berlin2_adc.txt @@ -0,0 +1,19 @@ +* Berlin Analog to Digital Converter (ADC) + +The Berlin ADC has 8 channels, with one connected to a temperature sensor. +It is part of the system controller register set. The ADC node should be a +sub-node of the system controller node. + +Required properties: +- compatible: must be "marvell,berlin2-adc" +- interrupts: the interrupts for the ADC and the temperature sensor +- interrupt-names: should be "adc" and "tsen" + +Example: + +adc: adc { + compatible = "marvell,berlin2-adc"; + interrupt-parent = <&sic>; + interrupts = <12>, <14>; + interrupt-names = "adc", "tsen"; +}; diff --git a/dts/Bindings/iio/adc/ti-adc128s052.txt b/dts/Bindings/iio/adc/ti-adc128s052.txt index 42ca7deec9..15ca6b4795 100644 --- a/dts/Bindings/iio/adc/ti-adc128s052.txt +++ b/dts/Bindings/iio/adc/ti-adc128s052.txt @@ -1,7 +1,7 @@ -* Texas Instruments' ADC128S052 ADC chip +* Texas Instruments' ADC128S052 and ADC122S021 ADC chip Required properties: - - compatible: Should be "ti,adc128s052" + - compatible: Should be "ti,adc128s052" or "ti,adc122s021" - reg: spi chip select number for the device - vref-supply: The regulator supply for ADC reference voltage diff --git a/dts/Bindings/iio/adc/vf610-adc.txt b/dts/Bindings/iio/adc/vf610-adc.txt index 1a4a43d5c9..3eb40e20c1 100644 --- a/dts/Bindings/iio/adc/vf610-adc.txt +++ b/dts/Bindings/iio/adc/vf610-adc.txt @@ -11,6 +11,13 @@ Required properties: - clock-names: Must contain "adc", matching entry in the clocks property. - vref-supply: The regulator supply ADC reference voltage. +Recommended properties: +- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating + requirements. Three values are required, depending on conversion mode: + - Frequency in normal mode (ADLPC=0, ADHSC=0) + - Frequency in high-speed mode (ADLPC=0, ADHSC=1) + - Frequency in low-power mode (ADLPC=1, ADHSC=0) + Example: adc0: adc@4003b000 { compatible = "fsl,vf610-adc"; @@ -18,5 +25,7 @@ adc0: adc@4003b000 { interrupts = <0 53 0x04>; clocks = <&clks VF610_CLK_ADC0>; clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; vref-supply = <®_vcc_3v3_mcu>; }; diff --git a/dts/Bindings/iio/imu/inv_mpu6050.txt b/dts/Bindings/iio/imu/inv_mpu6050.txt new file mode 100644 index 0000000000..e4d8f1c52f --- /dev/null +++ b/dts/Bindings/iio/imu/inv_mpu6050.txt @@ -0,0 +1,17 @@ +InvenSense MPU-6050 Six-Axis (Gyro + Accelerometer) MEMS MotionTracking Device + +http://www.invensense.com/mems/gyro/mpu6050.html + +Required properties: + - compatible : should be "invensense,mpu6050" + - reg : the I2C address of the sensor + - interrupt-parent : should be the phandle for the interrupt controller + - interrupts : interrupt mapping for GPIO IRQ + +Example: + mpu6050@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <18 1>; + }; diff --git a/dts/Bindings/iio/magnetometer/bmc150_magn.txt b/dts/Bindings/iio/magnetometer/bmc150_magn.txt new file mode 100644 index 0000000000..9f263b7df1 --- /dev/null +++ b/dts/Bindings/iio/magnetometer/bmc150_magn.txt @@ -0,0 +1,22 @@ +* Bosch BMC150 magnetometer sensor + +http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf + +Required properties: + + - compatible : should be "bosch,bmc150_magn" + - reg : the I2C address of the magnetometer + +Optional properties: + + - interrupt-parent : phandle to the parent interrupt controller + - interrupts : interrupt mapping for GPIO IRQ + +Example: + +bmc150_magn@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + interrupt-parent = <&gpio1>; + interrupts = <0 1>; +}; diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt index d2aaca9745..8a6be3bdf2 100644 --- a/dts/Bindings/iio/st-sensors.txt +++ b/dts/Bindings/iio/st-sensors.txt @@ -30,6 +30,7 @@ Accelerometers: - st,lsm330d-accel - st,lsm330dl-accel - st,lsm330dlc-accel +- st,lis331dl-accel - st,lis331dlh-accel - st,lsm303dl-accel - st,lsm303dlm-accel @@ -45,6 +46,7 @@ Gyroscopes: - st,lsm330-gyro Magnetometers: +- st,lsm303dlh-magn - st,lsm303dlhc-magn - st,lsm303dlm-magn - st,lis3mdl-magn diff --git a/dts/Bindings/iio/temperature/mlx90614.txt b/dts/Bindings/iio/temperature/mlx90614.txt new file mode 100644 index 0000000000..9be57b0360 --- /dev/null +++ b/dts/Bindings/iio/temperature/mlx90614.txt @@ -0,0 +1,24 @@ +* Melexis MLX90614 contactless IR temperature sensor + +http://melexis.com/Infrared-Thermometer-Sensors/Infrared-Thermometer-Sensors/MLX90614-615.aspx + +Required properties: + + - compatible: should be "melexis,mlx90614" + - reg: the I2C address of the sensor + +Optional properties: + + - wakeup-gpios: device tree identifier of the GPIO connected to the SDA line + to hold low in order to wake up the device. In normal operation, the + GPIO is set as input and will not interfere in I2C communication. There + is no need for a GPIO driving the SCL line. If no GPIO is given, power + management is disabled. + +Example: + +mlx90614@5a { + compatible = "melexis,mlx90614"; + reg = <0x5a>; + wakeup-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +}; diff --git a/dts/Bindings/input/ti,drv2665.txt b/dts/Bindings/input/ti,drv2665.txt new file mode 100644 index 0000000000..1ba97ac043 --- /dev/null +++ b/dts/Bindings/input/ti,drv2665.txt @@ -0,0 +1,17 @@ +* Texas Instruments - drv2665 Haptics driver + +Required properties: + - compatible - "ti,drv2665" - DRV2665 + - reg - I2C slave address + - vbat-supply - Required supply regulator + +Example: + +haptics: haptics@59 { + compatible = "ti,drv2665"; + reg = <0x59>; + vbat-supply = <&vbat>; +}; + +For more product information please see the link below: +http://www.ti.com/product/drv2665 diff --git a/dts/Bindings/input/touchscreen/ti-tsc-adc.txt b/dts/Bindings/input/touchscreen/ti-tsc-adc.txt index 6c4fb34823..b1163bf971 100644 --- a/dts/Bindings/input/touchscreen/ti-tsc-adc.txt +++ b/dts/Bindings/input/touchscreen/ti-tsc-adc.txt @@ -42,6 +42,27 @@ Optional properties: hardware knob for adjusting the amount of "settling time". +- child "adc" + ti,chan-step-opendelay: List of open delays for each channel of + ADC in the order of ti,adc-channels. The + value corresponds to the number of ADC + clock cycles to wait after applying the + step configuration registers and before + sending the start of ADC conversion. + Maximum value is 0x3FFFF. + ti,chan-step-sampledelay: List of sample delays for each channel + of ADC in the order of ti,adc-channels. + The value corresponds to the number of + ADC clock cycles to sample (to hold + start of conversion high). + Maximum value is 0xFF. + ti,chan-step-avg: Number of averages to be performed for each + channel of ADC. If average is 16 then input + is sampled 16 times and averaged to get more + accurate value. This increases the time taken + by ADC to generate a sample. Valid range is 0 + average to 16 averages. Maximum value is 16. + Example: tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; @@ -55,5 +76,8 @@ Example: adc { ti,adc-channels = <4 5 6 7>; + ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>; + ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>; + ti,chan-step-avg = <16 2 4 8>; }; } diff --git a/dts/Bindings/interrupt-controller/atmel,aic.txt b/dts/Bindings/interrupt-controller/atmel,aic.txt index f292917fa0..0e9f09a6a2 100644 --- a/dts/Bindings/interrupt-controller/atmel,aic.txt +++ b/dts/Bindings/interrupt-controller/atmel,aic.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "atmel,-aic" - can be "at91rm9200", "sama5d3" or "sama5d4" + can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - interrupt-controller: Identifies the node as an interrupt controller. - interrupt-parent: For single AIC system, it is an empty property. - #interrupt-cells: The number of cells to define the interrupts. It should be 3. diff --git a/dts/Bindings/interrupt-controller/ingenic,intc.txt b/dts/Bindings/interrupt-controller/ingenic,intc.txt new file mode 100644 index 0000000000..5f89fb635a --- /dev/null +++ b/dts/Bindings/interrupt-controller/ingenic,intc.txt @@ -0,0 +1,28 @@ +Ingenic SoC Interrupt Controller + +Required properties: + +- compatible : should be "ingenic,-intc". Valid strings are: + ingenic,jz4740-intc + ingenic,jz4770-intc + ingenic,jz4775-intc + ingenic,jz4780-intc +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + +intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; +}; diff --git a/dts/Bindings/interrupt-controller/qca,ath79-cpu-intc.txt b/dts/Bindings/interrupt-controller/qca,ath79-cpu-intc.txt new file mode 100644 index 0000000000..aabce7810d --- /dev/null +++ b/dts/Bindings/interrupt-controller/qca,ath79-cpu-intc.txt @@ -0,0 +1,44 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller + +On most SoC the IRQ controller need to flush the DDR FIFO before running +the interrupt handler of some devices. This is configured using the +qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. + +Required Properties: + +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-cpu-intc" + as fallback +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 for intc + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Optional Properties: + +- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write + buffer flush +- qca,ddr-wb-channels: List of phandles to the write buffer channels for + each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt + default to the entry's index. + +Example: + + interrupt-controller { + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; + + ... + + ddr_ctrl: memory-controller@18000000 { + ... + #qca,ddr-wb-channel-cells = <1>; + }; diff --git a/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt new file mode 100644 index 0000000000..391717a68f --- /dev/null +++ b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt @@ -0,0 +1,30 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller + +The MISC interrupt controller is a secondary controller for lower priority +interrupt. + +Required Properties: +- compatible: has to be "qca,-cpu-intc", "qca,ar7100-misc-intc" + as fallback +- reg: Base address and size of the controllers memory area +- interrupt-parent: phandle of the parent interrupt controller. +- interrupts: Interrupt specifier for the controllers interrupt. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode interrupt + source, should be 1 + +Please refer to interrupts.txt in this directory for details of the common +Interrupt Controllers bindings used by client devices. + +Example: + + interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/dts/Bindings/interrupt-controller/renesas,h8300h-intc.txt b/dts/Bindings/interrupt-controller/renesas,h8300h-intc.txt new file mode 100644 index 0000000000..56e8d82aff --- /dev/null +++ b/dts/Bindings/interrupt-controller/renesas,h8300h-intc.txt @@ -0,0 +1,22 @@ +* H8/300H Interrupt controller + +Required properties: + +- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback. +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory +- regs: Base address of interrupt controller registers. + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties + +Example: + + h8intc: interrupt-controller@fee012 { + compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfee012 7>; + }; diff --git a/dts/Bindings/interrupt-controller/renesas,h8s-intc.txt b/dts/Bindings/interrupt-controller/renesas,h8s-intc.txt new file mode 100644 index 0000000000..faded2b155 --- /dev/null +++ b/dts/Bindings/interrupt-controller/renesas,h8s-intc.txt @@ -0,0 +1,22 @@ +* H8S Interrupt controller + +Required properties: + +- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback. +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory +- regs: Base address of interrupt controller registers. + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties + +Example: + + h8intc: interrupt-controller@fffe00 { + compatible = "renesas,h8s-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfffe00 24>; + }; diff --git a/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt b/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt index 4f7946ae8a..772c550d3b 100644 --- a/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/dts/Bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -13,9 +13,12 @@ Required properties: - reg: Base address and length of each register bank used by the external IRQ pins driven by the interrupt controller hardware module. The base addresses, length and number of required register banks varies with soctype. - +- interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory + interrupts.txt in this directory. +- interrupts: Must contain a list of interrupt specifiers. For each interrupt + provided by this irqpin controller instance, there must be one entry, + referring to the corresponding parent interrupt. Optional properties: @@ -25,3 +28,35 @@ Optional properties: if different from the default 4 bits - control-parent: disable and enable interrupts on the parent interrupt controller, needed for some broken implementations +- clocks: Must contain a reference to the functional clock. This property is + mandatory if the hardware implements a controllable functional clock for + the irqpin controller instance. +- power-domains: Must contain a reference to the power domain. This property is + mandatory if the irqpin controller instance is part of a controllable power + domain. + + +Example +------- + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", + "renesas,intc-irqpin"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt new file mode 100644 index 0000000000..c03eec1168 --- /dev/null +++ b/dts/Bindings/iommu/arm,smmu-v3.txt @@ -0,0 +1,37 @@ +* ARM SMMUv3 Architecture Implementation + +The SMMUv3 architecture is a significant deparature from previous +revisions, replacing the MMIO register interface with in-memory command +and event queues and adding support for the ATS and PRI components of +the PCIe specification. + +** SMMUv3 required properties: + +- compatible : Should include: + + * "arm,smmu-v3" for any SMMUv3 compliant + implementation. This entry should be last in the + compatible list. + +- reg : Base address and size of the SMMU. + +- interrupts : Non-secure interrupt list describing the wired + interrupt sources corresponding to entries in + interrupt-names. If no wired interrupts are + present then this property may be omitted. + +- interrupt-names : When the interrupts property is present, should + include the following: + * "eventq" - Event Queue not empty + * "priq" - PRI Queue not empty + * "cmdq-sync" - CMD_SYNC complete + * "gerror" - Global Error activated + +** SMMUv3 optional properties: + +- dma-coherent : Present if DMA operations made by the SMMU (page + table walks, stream table accesses etc) are cache + coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. diff --git a/dts/Bindings/leds/leds-aat1290.txt b/dts/Bindings/leds/leds-aat1290.txt new file mode 100644 index 0000000000..c05ed91a4e --- /dev/null +++ b/dts/Bindings/leds/leds-aat1290.txt @@ -0,0 +1,73 @@ +* Skyworks Solutions, Inc. AAT1290 Current Regulator for Flash LEDs + +The device is controlled through two pins: FL_EN and EN_SET. The pins when, +asserted high, enable flash strobe and movie mode (max 1/2 of flash current) +respectively. In order to add a capability of selecting the strobe signal source +(e.g. CPU or camera sensor) there is an additional switch required, independent +of the flash chip. The switch is controlled with pin control. + +Required properties: + +- compatible : Must be "skyworks,aat1290". +- flen-gpios : Must be device tree identifier of the flash device FL_EN pin. +- enset-gpios : Must be device tree identifier of the flash device EN_SET pin. + +Optional properties: +- pinctrl-names : Must contain entries: "default", "host", "isp". Entries + "default" and "host" must refer to the same pin configuration + node, which sets the host as a strobe signal provider. Entry + "isp" must refer to the pin configuration node, which sets the + ISP as a strobe signal provider. + +A discrete LED element connected to the device must be represented by a child +node - see Documentation/devicetree/bindings/leds/common.txt. + +Required properties of the LED child node: +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Maximum flash LED supply current can be calculated using + following formula: I = 1A * 162kohm / Rset. +- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + Maximum flash timeout can be calculated using following + formula: T = 8.82 * 10^9 * Ct. + +Optional properties of the LED child node: +- label : see Documentation/devicetree/bindings/leds/common.txt + +Example (by Ct = 220nF, Rset = 160kohm and exynos4412-trats2 board with +a switch that allows for routing strobe signal either from the host or from +the camera sensor): + +#include "exynos4412.dtsi" + +aat1290 { + compatible = "skyworks,aat1290"; + flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; + enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "host", "isp"; + pinctrl-0 = <&camera_flash_host>; + pinctrl-1 = <&camera_flash_host>; + pinctrl-2 = <&camera_flash_isp>; + + camera_flash: flash-led { + label = "aat1290-flash"; + led-max-microamp = <520833>; + flash-max-microamp = <1012500>; + flash-timeout-us = <1940000>; + }; +}; + +&pinctrl_0 { + camera_flash_host: camera-flash-host { + samsung,pins = "gpj1-0"; + samsung,pin-function = <1>; + samsung,pin-val = <0>; + }; + + camera_flash_isp: camera-flash-isp { + samsung,pins = "gpj1-0"; + samsung,pin-function = <1>; + samsung,pin-val = <1>; + }; +}; diff --git a/dts/Bindings/leds/leds-bcm6328.txt b/dts/Bindings/leds/leds-bcm6328.txt new file mode 100644 index 0000000000..f9e36adc0e --- /dev/null +++ b/dts/Bindings/leds/leds-bcm6328.txt @@ -0,0 +1,309 @@ +LEDs connected to Broadcom BCM6328 controller + +This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. +In these SoCs it's possible to control LEDs both as GPIOs or by hardware. +However, on some devices there are Serial LEDs (LEDs connected to a 74x164 +controller), which can either be controlled by software (exporting the 74x164 +as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. +Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and +exporting the 74x164 as spi-gpio prevents those LEDs to be hardware +controlled, so the only chance to keep them working is by using this driver. + +BCM6328 LED controller has a HWDIS register, which controls whether a LED +should be controlled by a hardware signal instead of the MODE register value, +with 0 meaning hardware control enabled and 1 hardware control disabled. This +is usually 1:1 for hardware to LED signals, but through the activity/link +registers you have some limited control over rerouting the LEDs (as +explained later in brcm,link-signal-sources). Even if a LED is hardware +controlled you are still able to make it blink or light it up if it isn't, +but you can't turn it off if the hardware decides to light it up. For this +reason, hardware controlled LEDs aren't registered as LED class devices. + +Required properties: + - compatible : should be "brcm,bcm6328-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6328 LED controller address and size. + +Optional properties: + - brcm,serial-leds : Boolean, enables Serial LEDs. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6328-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 23 are valid). + +LED sub-node optional properties: + a) Optional properties for sub-nodes related to software controlled LEDs: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + - default-state : see + Documentation/devicetree/bindings/leds/leds-gpio.txt + - linux,default-trigger : see + Documentation/devicetree/bindings/leds/common.txt + + b) Optional properties for sub-nodes related to hardware controlled LEDs: + - brcm,hardware-controlled : Boolean, makes this LED hardware controlled. + Default : false + - brcm,link-signal-sources : An array of hardware link + signal sources. Up to four link hardware signals can get muxed into + these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may + be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs + 4 to 7. A signal can be muxed to more than one LED, and one LED can + have more than one source signal. + - brcm,activity-signal-sources : An array of hardware activity + signal sources. Up to four activity hardware signals can get muxed into + these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may + be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs + 4 to 7. A signal can be muxed to more than one LED, and one LED can + have more than one source signal. + +Examples: +Scenario 1 : BCM6328 with 4 EPHY LEDs + leds0: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10000800 0x24>; + + alarm_red@2 { + reg = <2>; + active-low; + label = "red:alarm"; + }; + inet_green@3 { + reg = <3>; + active-low; + label = "green:inet"; + }; + power_green@4 { + reg = <4>; + active-low; + label = "green:power"; + default-state = "on"; + }; + ephy0_spd@17 { + reg = <17>; + brcm,hardware-controlled; + }; + ephy1_spd@18 { + reg = <18>; + brcm,hardware-controlled; + }; + ephy2_spd@19 { + reg = <19>; + brcm,hardware-controlled; + }; + ephy3_spd@20 { + reg = <20>; + brcm,hardware-controlled; + }; + }; + +Scenario 2 : BCM63268 with Serial/GPHY0 LEDs + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + brcm,serial-leds; + + gphy0_spd0@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + }; + gphy0_spd1@1 { + reg = <1>; + brcm,hardware-controlled; + brcm,link-signal-sources = <1>; + }; + inet_red@2 { + reg = <2>; + active-low; + label = "red:inet"; + }; + dsl_green@3 { + reg = <3>; + active-low; + label = "green:dsl"; + }; + usb_green@4 { + reg = <4>; + active-low; + label = "green:usb"; + }; + wps_green@7 { + reg = <7>; + active-low; + label = "green:wps"; + }; + inet_green@8 { + reg = <8>; + active-low; + label = "green:inet"; + }; + ephy0_act@9 { + reg = <9>; + brcm,hardware-controlled; + }; + ephy1_act@10 { + reg = <10>; + brcm,hardware-controlled; + }; + ephy2_act@11 { + reg = <11>; + brcm,hardware-controlled; + }; + gphy0_act@12 { + reg = <12>; + brcm,hardware-controlled; + }; + ephy0_spd@13 { + reg = <13>; + brcm,hardware-controlled; + }; + ephy1_spd@14 { + reg = <14>; + brcm,hardware-controlled; + }; + ephy2_spd@15 { + reg = <15>; + brcm,hardware-controlled; + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 3 : BCM6362 with 1 LED for each EPHY + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + brcm,activity-signal-sources = <0>; + /* USB link/activity routed to USB LED */ + }; + inet@1 { + reg = <1>; + brcm,hardware-controlled; + brcm,activity-signal-sources = <1>; + /* INET activity routed to INET LED */ + }; + ephy0@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4>; + /* EPHY0 link routed to EPHY0 LED */ + }; + ephy1@5 { + reg = <5>; + brcm,hardware-controlled; + brcm,link-signal-sources = <5>; + /* EPHY1 link routed to EPHY1 LED */ + }; + ephy2@6 { + reg = <6>; + brcm,hardware-controlled; + brcm,link-signal-sources = <6>; + /* EPHY2 link routed to EPHY2 LED */ + }; + ephy3@7 { + reg = <7>; + brcm,hardware-controlled; + brcm,link-signal-sources = <7>; + /* EPHY3 link routed to EPHY3 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 4 : BCM6362 with 1 LED for all EPHYs + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0 1>; + brcm,activity-signal-sources = <0 1>; + /* USB/INET link/activity routed to USB LED */ + }; + ephy@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4 5 6 7>; + /* EPHY0/1/2/3 link routed to EPHY0 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; + +Scenario 5 : BCM6362 with EPHY LEDs swapped + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + + usb@0 { + reg = <0>; + brcm,hardware-controlled; + brcm,link-signal-sources = <0>; + brcm,activity-signal-sources = <0 1>; + /* USB link/act and INET act routed to USB LED */ + }; + ephy0@4 { + reg = <4>; + brcm,hardware-controlled; + brcm,link-signal-sources = <7>; + /* EPHY3 link routed to EPHY0 LED */ + }; + ephy1@5 { + reg = <5>; + brcm,hardware-controlled; + brcm,link-signal-sources = <6>; + /* EPHY2 link routed to EPHY1 LED */ + }; + ephy2@6 { + reg = <6>; + brcm,hardware-controlled; + brcm,link-signal-sources = <5>; + /* EPHY1 link routed to EPHY2 LED */ + }; + ephy3@7 { + reg = <7>; + brcm,hardware-controlled; + brcm,link-signal-sources = <4>; + /* EPHY0 link routed to EPHY3 LED */ + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + default-state = "on"; + }; + }; diff --git a/dts/Bindings/leds/leds-bcm6358.txt b/dts/Bindings/leds/leds-bcm6358.txt new file mode 100644 index 0000000000..b22a55bcc6 --- /dev/null +++ b/dts/Bindings/leds/leds-bcm6358.txt @@ -0,0 +1,145 @@ +LEDs connected to Broadcom BCM6358 controller + +This controller is present on BCM6358 and BCM6368. +In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), +which can either be controlled by software (exporting the 74x164 as spi-gpio. +See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. + +Required properties: + - compatible : should be "brcm,bcm6358-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6358 LED controller address and size. + +Optional properties: + - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8. + Default : 1 + - brcm,clk-dat-low : Boolean, makes clock and data signals active low. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6358-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 31 are valid). + +LED sub-node optional properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + - default-state : see + Documentation/devicetree/bindings/leds/leds-gpio.txt + - linux,default-trigger : see + Documentation/devicetree/bindings/leds/common.txt + +Examples: +Scenario 1 : BCM6358 + leds0: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe00d0 0x8>; + + alarm_white { + reg = <0>; + active-low; + label = "white:alarm"; + }; + tv_white { + reg = <2>; + active-low; + label = "white:tv"; + }; + tel_white { + reg = <3>; + active-low; + label = "white:tel"; + }; + adsl_white { + reg = <4>; + active-low; + label = "white:adsl"; + }; + }; + +Scenario 2 : BCM6368 + leds0: led-controller@100000d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100000d0 0x8>; + brcm,pol-low; + brcm,clk-div = <4>; + + power_red { + reg = <0>; + active-low; + label = "red:power"; + }; + power_green { + reg = <1>; + active-low; + label = "green:power"; + default-state = "on"; + }; + power_blue { + reg = <2>; + label = "blue:power"; + }; + broadband_red { + reg = <3>; + active-low; + label = "red:broadband"; + }; + broadband_green { + reg = <4>; + label = "green:broadband"; + }; + broadband_blue { + reg = <5>; + active-low; + label = "blue:broadband"; + }; + wireless_red { + reg = <6>; + active-low; + label = "red:wireless"; + }; + wireless_green { + reg = <7>; + active-low; + label = "green:wireless"; + }; + wireless_blue { + reg = <8>; + label = "blue:wireless"; + }; + phone_red { + reg = <9>; + active-low; + label = "red:phone"; + }; + phone_green { + reg = <10>; + active-low; + label = "green:phone"; + }; + phone_blue { + reg = <11>; + label = "blue:phone"; + }; + upgrading_red { + reg = <12>; + active-low; + label = "red:upgrading"; + }; + upgrading_green { + reg = <13>; + active-low; + label = "green:upgrading"; + }; + upgrading_blue { + reg = <14>; + label = "blue:upgrading"; + }; + }; diff --git a/dts/Bindings/leds/leds-ktd2692.txt b/dts/Bindings/leds/leds-ktd2692.txt new file mode 100644 index 0000000000..8537374525 --- /dev/null +++ b/dts/Bindings/leds/leds-ktd2692.txt @@ -0,0 +1,50 @@ +* Kinetic Technologies - KTD2692 Flash LED Driver + +KTD2692 is the ideal power solution for high-power flash LEDs. +It uses ExpressWire single-wire programming for maximum flexibility. + +The ExpressWire interface through CTRL pin can control LED on/off and +enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current, +Flash timeout, LVP(low voltage protection). + +Also, When the AUX pin is pulled high while CTRL pin is high, +LED current will be ramped up to the flash-mode current level. + +Required properties: +- compatible : Should be "kinetic,ktd2692". +- ctrl-gpios : Specifier of the GPIO connected to CTRL pin. +- aux-gpios : Specifier of the GPIO connected to AUX pin. + +Optional properties: +- vin-supply : "vin" LED supply (2.7V to 5.5V). + See Documentation/devicetree/bindings/regulator/regulator.txt + +A discrete LED element connected to the device must be represented by a child +node - See Documentation/devicetree/bindings/leds/common.txt + +Required properties for flash LED child nodes: + See Documentation/devicetree/bindings/leds/common.txt +- led-max-microamp : Minimum Threshold for Timer protection + is defined internally (Maximum 300mA). +- flash-max-microamp : Flash LED maximum current + Formula : I(mA) = 15000 / Rset. +- flash-max-timeout-us : Flash LED maximum timeout. + +Optional properties for flash LED child nodes: +- label : See Documentation/devicetree/bindings/leds/common.txt + +Example: + +ktd2692 { + compatible = "kinetic,ktd2692"; + ctrl-gpios = <&gpc0 1 0>; + aux-gpios = <&gpc0 2 0>; + vin-supply = <&vbat>; + + flash-led { + label = "ktd2692-flash"; + led-max-microamp = <300000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1835000>; + }; +}; diff --git a/dts/Bindings/leds/leds-tlc591xx.txt b/dts/Bindings/leds/leds-tlc591xx.txt new file mode 100644 index 0000000000..3bbbf70244 --- /dev/null +++ b/dts/Bindings/leds/leds-tlc591xx.txt @@ -0,0 +1,40 @@ +LEDs connected to tlc59116 or tlc59108 + +Required properties +- compatible: should be "ti,tlc59116" or "ti,tlc59108" +- #address-cells: must be 1 +- #size-cells: must be 0 +- reg: typically 0x68 + +Each led is represented as a sub-node of the ti,tlc59116. +See Documentation/devicetree/bindings/leds/common.txt + +LED sub-node properties: +- reg: number of LED line, 0 to 15 or 0 to 7 +- label: (optional) name of LED +- linux,default-trigger : (optional) + +Examples: + +tlc59116@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59116"; + reg = <0x68>; + + wan@0 { + label = "wrt1900ac:amber:wan"; + reg = <0x0>; + }; + + 2g@2 { + label = "wrt1900ac:white:2g"; + reg = <0x2>; + }; + + alive@9 { + label = "wrt1900ac:green:alive"; + reg = <0x9>; + linux,default_trigger = "heartbeat"; + }; +}; diff --git a/dts/Bindings/mailbox/brcm,bcm2835-mbox.txt b/dts/Bindings/mailbox/brcm,bcm2835-mbox.txt new file mode 100644 index 0000000000..e893615ef6 --- /dev/null +++ b/dts/Bindings/mailbox/brcm,bcm2835-mbox.txt @@ -0,0 +1,26 @@ +Broadcom BCM2835 VideoCore mailbox IPC + +Required properties: + +- compatible: Should be "brcm,bcm2835-mbox" +- reg: Specifies base physical address and size of the registers +- interrupts: The interrupt number + See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +- #mbox-cells: Specifies the number of cells needed to encode a mailbox + channel. The value shall be 0, since there is only one + mailbox channel implemented by the device. + +Example: + +mailbox: mailbox@7e00b800 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; + #mbox-cells = <0>; +}; + +firmware: firmware { + compatible = "raspberrypi,firmware"; + mboxes = <&mailbox>; + #power-domain-cells = <1>; +}; diff --git a/dts/Bindings/mailbox/mailbox.txt b/dts/Bindings/mailbox/mailbox.txt index 1a2cd3d266..be05b9746c 100644 --- a/dts/Bindings/mailbox/mailbox.txt +++ b/dts/Bindings/mailbox/mailbox.txt @@ -22,17 +22,11 @@ Required property: - mboxes: List of phandle and mailbox channel specifiers. Optional property: -- mbox-names: List of identifier strings for each mailbox channel - required by the client. The use of this property - is discouraged in favor of using index in list of - 'mboxes' while requesting a mailbox. Instead the - platforms may define channel indices, in DT headers, - to something legible. +- mbox-names: List of identifier strings for each mailbox channel. Example: pwr_cntrl: power { ... mbox-names = "pwr-ctrl", "rpc"; - mboxes = <&mailbox 0 - &mailbox 1>; + mboxes = <&mailbox 0 &mailbox 1>; }; diff --git a/dts/Bindings/media/i2c/adp1653.txt b/dts/Bindings/media/i2c/adp1653.txt new file mode 100644 index 0000000000..5ce66f2104 --- /dev/null +++ b/dts/Bindings/media/i2c/adp1653.txt @@ -0,0 +1,37 @@ +* Analog Devices ADP1653 flash LED driver + +Required Properties: + + - compatible: Must contain "adi,adp1653" + + - reg: I2C slave address + + - enable-gpios: Specifier of the GPIO connected to EN pin + +There are two LED outputs available - flash and indicator. One LED is +represented by one child node, nodes need to be named "flash" and "indicator". + +Required properties of the LED child node: +- max-microamp : see Documentation/devicetree/bindings/leds/common.txt + +Required properties of the flash LED child node: + +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt +- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + +Example: + + adp1653: led-controller@30 { + compatible = "adi,adp1653"; + reg = <0x30>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ + + flash { + flash-timeout-us = <500000>; + flash-max-microamp = <320000>; + max-microamp = <50000>; + }; + indicator { + max-microamp = <17500>; + }; + }; diff --git a/dts/Bindings/media/st,stih4xx.txt b/dts/Bindings/media/st,stih4xx.txt new file mode 100644 index 0000000000..df655cd3a4 --- /dev/null +++ b/dts/Bindings/media/st,stih4xx.txt @@ -0,0 +1,32 @@ +STMicroelectronics stih4xx platforms + +bdisp: 2D blitter for STMicroelectronics SoC. + +Required properties: +- compatible: should be "st,stih407-bdisp". +- reg: BDISP physical address location and length. +- interrupts: BDISP interrupt number. +- clocks: from common clock binding: handle hardware IP needed clocks, the + number of clocks may depend on the SoC type. + See ../clocks/clock-bindings.txt for details. +- clock-names: names of the clocks listed in clocks property in the same order. + +Example: + + bdisp0:bdisp@9f10000 { + compatible = "st,stih407-bdisp"; + reg = <0x9f10000 0x1000>; + interrupts = ; + clock-names = "bdisp"; + clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; + }; + +Aliases: +Each BDISP should have a numbered alias in the aliases node, in the form of +bdispN, N = 0 or 1. + +Example: + + aliases { + bdisp0 = &bdisp0; + }; diff --git a/dts/Bindings/memory-controllers/ath79-ddr-controller.txt b/dts/Bindings/memory-controllers/ath79-ddr-controller.txt new file mode 100644 index 0000000000..efe35a0657 --- /dev/null +++ b/dts/Bindings/memory-controllers/ath79-ddr-controller.txt @@ -0,0 +1,35 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller + +The DDR controller of the ARxxx and AR9xxx families provides an interface +to flush the FIFO between various devices and the DDR. This is mainly used +by the IRQ controller to flush the FIFO before running the interrupt handler +of such devices. + +Required properties: + +- compatible: has to be "qca,-ddr-controller", + "qca,[ar7100|ar7240]-ddr-controller" as fallback. + On SoC with PCI support "qca,ar7100-ddr-controller" should be used as + fallback, otherwise "qca,ar7240-ddr-controller" should be used. +- reg: Base address and size of the controllers memory area +- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer + channel + +Example: + + ddr_ctrl: memory-controller@18000000 { + compatible = "qca,ar9132-ddr-controller", + "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + ... + + interrupt-controller { + ... + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; diff --git a/dts/Bindings/memory-controllers/nvidia,tegra-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra-mc.txt index f3db93c85e..3338a2834a 100644 --- a/dts/Bindings/memory-controllers/nvidia,tegra-mc.txt +++ b/dts/Bindings/memory-controllers/nvidia,tegra-mc.txt @@ -1,6 +1,9 @@ NVIDIA Tegra Memory Controller device tree bindings =================================================== +memory-controller node +---------------------- + Required properties: - compatible: Should be "nvidia,tegra-mc" - reg: Physical base address and length of the controller's registers. @@ -15,9 +18,49 @@ Required properties: This device implements an IOMMU that complies with the generic IOMMU binding. See ../iommu/iommu.txt for details. -Example: --------- +emc-timings subnode +------------------- + +The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in +register PMC_STRAPPING_OPT_A). + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. + +timing subnode +-------------- + +Each "emc-timings" node should contain a subnode for every supported EMC clock rate. + +Required properties for timing nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC +(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be +specified, according to the board documentation: + + MC_EMEM_ARB_CFG + MC_EMEM_ARB_OUTSTANDING_REQ + MC_EMEM_ARB_TIMING_RCD + MC_EMEM_ARB_TIMING_RP + MC_EMEM_ARB_TIMING_RC + MC_EMEM_ARB_TIMING_RAS + MC_EMEM_ARB_TIMING_FAW + MC_EMEM_ARB_TIMING_RRD + MC_EMEM_ARB_TIMING_RAP2PRE + MC_EMEM_ARB_TIMING_WAP2PRE + MC_EMEM_ARB_TIMING_R2R + MC_EMEM_ARB_TIMING_W2W + MC_EMEM_ARB_TIMING_R2W + MC_EMEM_ARB_TIMING_W2R + MC_EMEM_ARB_DA_TURNS + MC_EMEM_ARB_DA_COVERS + MC_EMEM_ARB_MISC0 + MC_EMEM_ARB_MISC1 + MC_EMEM_ARB_RING1_THROTTLE +Example SoC include file: + +/ { mc: memory-controller@0,70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -34,3 +77,40 @@ Example: ... iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; }; +}; + +Example board file: + +/ { + memory-controller@0,70019000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; +}; diff --git a/dts/Bindings/memory-controllers/renesas,h8300-bsc.txt b/dts/Bindings/memory-controllers/renesas,h8300-bsc.txt new file mode 100644 index 0000000000..cdf406c902 --- /dev/null +++ b/dts/Bindings/memory-controllers/renesas,h8300-bsc.txt @@ -0,0 +1,12 @@ +* H8/300 bus controller + +Required properties: + - compatible: Must be "renesas,h8300-bsc". + - reg: Base address and length of BSC registers. + +Example. + bsc: memory-controller@fee01e { + compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; + reg = <0xfee01e 8>; + }; + diff --git a/dts/Bindings/memory-controllers/tegra-emc.txt b/dts/Bindings/memory-controllers/tegra-emc.txt new file mode 100644 index 0000000000..b59c625d63 --- /dev/null +++ b/dts/Bindings/memory-controllers/tegra-emc.txt @@ -0,0 +1,374 @@ +NVIDIA Tegra124 SoC EMC (external memory controller) +==================================================== + +Required properties : +- compatible : Should be "nvidia,tegra124-emc". +- reg : physical base address and length of the controller's registers. +- nvidia,memory-controller : phandle of the MC driver. + +The node should contain a "emc-timings" subnode for each supported RAM type +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address +being its RAM_CODE. + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is +used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as +their unit address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- The following properties contain EMC timing characterization values +(specified in the board documentation) : + - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG + - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2 + - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3 + - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL + - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0 + - nvidia,emc-cfg : EMC_CFG + - nvidia,emc-cfg-2 : EMC_CFG_2 + - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL + - nvidia,emc-mode-1 : Mode Register 1 + - nvidia,emc-mode-2 : Mode Register 2 + - nvidia,emc-mode-4 : Mode Register 4 + - nvidia,emc-mode-reset : Mode Register 0 + - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT + - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL + - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2 + - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change + - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL +- nvidia,emc-configuration : EMC timing characterization data. These are the +registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to +be specified, according to the board documentation: + + EMC_RC + EMC_RFC + EMC_RFC_SLR + EMC_RAS + EMC_RP + EMC_R2W + EMC_W2R + EMC_R2P + EMC_W2P + EMC_RD_RCD + EMC_WR_RCD + EMC_RRD + EMC_REXT + EMC_WEXT + EMC_WDV + EMC_WDV_MASK + EMC_QUSE + EMC_QUSE_WIDTH + EMC_IBDLY + EMC_EINPUT + EMC_EINPUT_DURATION + EMC_PUTERM_EXTRA + EMC_PUTERM_WIDTH + EMC_PUTERM_ADJ + EMC_CDB_CNTL_1 + EMC_CDB_CNTL_2 + EMC_CDB_CNTL_3 + EMC_QRST + EMC_QSAFE + EMC_RDV + EMC_RDV_MASK + EMC_REFRESH + EMC_BURST_REFRESH_NUM + EMC_PRE_REFRESH_REQ_CNT + EMC_PDEX2WR + EMC_PDEX2RD + EMC_PCHG2PDEN + EMC_ACT2PDEN + EMC_AR2PDEN + EMC_RW2PDEN + EMC_TXSR + EMC_TXSRDLL + EMC_TCKE + EMC_TCKESR + EMC_TPD + EMC_TFAW + EMC_TRPAB + EMC_TCLKSTABLE + EMC_TCLKSTOP + EMC_TREFBW + EMC_FBIO_CFG6 + EMC_ODT_WRITE + EMC_ODT_READ + EMC_FBIO_CFG5 + EMC_CFG_DIG_DLL + EMC_CFG_DIG_DLL_PERIOD + EMC_DLL_XFORM_DQS0 + EMC_DLL_XFORM_DQS1 + EMC_DLL_XFORM_DQS2 + EMC_DLL_XFORM_DQS3 + EMC_DLL_XFORM_DQS4 + EMC_DLL_XFORM_DQS5 + EMC_DLL_XFORM_DQS6 + EMC_DLL_XFORM_DQS7 + EMC_DLL_XFORM_DQS8 + EMC_DLL_XFORM_DQS9 + EMC_DLL_XFORM_DQS10 + EMC_DLL_XFORM_DQS11 + EMC_DLL_XFORM_DQS12 + EMC_DLL_XFORM_DQS13 + EMC_DLL_XFORM_DQS14 + EMC_DLL_XFORM_DQS15 + EMC_DLL_XFORM_QUSE0 + EMC_DLL_XFORM_QUSE1 + EMC_DLL_XFORM_QUSE2 + EMC_DLL_XFORM_QUSE3 + EMC_DLL_XFORM_QUSE4 + EMC_DLL_XFORM_QUSE5 + EMC_DLL_XFORM_QUSE6 + EMC_DLL_XFORM_QUSE7 + EMC_DLL_XFORM_ADDR0 + EMC_DLL_XFORM_ADDR1 + EMC_DLL_XFORM_ADDR2 + EMC_DLL_XFORM_ADDR3 + EMC_DLL_XFORM_ADDR4 + EMC_DLL_XFORM_ADDR5 + EMC_DLL_XFORM_QUSE8 + EMC_DLL_XFORM_QUSE9 + EMC_DLL_XFORM_QUSE10 + EMC_DLL_XFORM_QUSE11 + EMC_DLL_XFORM_QUSE12 + EMC_DLL_XFORM_QUSE13 + EMC_DLL_XFORM_QUSE14 + EMC_DLL_XFORM_QUSE15 + EMC_DLI_TRIM_TXDQS0 + EMC_DLI_TRIM_TXDQS1 + EMC_DLI_TRIM_TXDQS2 + EMC_DLI_TRIM_TXDQS3 + EMC_DLI_TRIM_TXDQS4 + EMC_DLI_TRIM_TXDQS5 + EMC_DLI_TRIM_TXDQS6 + EMC_DLI_TRIM_TXDQS7 + EMC_DLI_TRIM_TXDQS8 + EMC_DLI_TRIM_TXDQS9 + EMC_DLI_TRIM_TXDQS10 + EMC_DLI_TRIM_TXDQS11 + EMC_DLI_TRIM_TXDQS12 + EMC_DLI_TRIM_TXDQS13 + EMC_DLI_TRIM_TXDQS14 + EMC_DLI_TRIM_TXDQS15 + EMC_DLL_XFORM_DQ0 + EMC_DLL_XFORM_DQ1 + EMC_DLL_XFORM_DQ2 + EMC_DLL_XFORM_DQ3 + EMC_DLL_XFORM_DQ4 + EMC_DLL_XFORM_DQ5 + EMC_DLL_XFORM_DQ6 + EMC_DLL_XFORM_DQ7 + EMC_XM2CMDPADCTRL + EMC_XM2CMDPADCTRL4 + EMC_XM2CMDPADCTRL5 + EMC_XM2DQPADCTRL2 + EMC_XM2DQPADCTRL3 + EMC_XM2CLKPADCTRL + EMC_XM2CLKPADCTRL2 + EMC_XM2COMPPADCTRL + EMC_XM2VTTGENPADCTRL + EMC_XM2VTTGENPADCTRL2 + EMC_XM2VTTGENPADCTRL3 + EMC_XM2DQSPADCTRL3 + EMC_XM2DQSPADCTRL4 + EMC_XM2DQSPADCTRL5 + EMC_XM2DQSPADCTRL6 + EMC_DSR_VTTGEN_DRV + EMC_TXDSRVTTGEN + EMC_FBIO_SPARE + EMC_ZCAL_WAIT_CNT + EMC_MRS_WAIT_CNT2 + EMC_CTT + EMC_CTT_DURATION + EMC_CFG_PIPE + EMC_DYN_SELF_REF_CONTROL + EMC_QPOP + +Example SoC include file: + +/ { + emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; +}; + +Example board file: + +/ { + emc@0,7001b000 { + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + }; + }; +}; diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt index 7665aa9597..a8fee60dc2 100644 --- a/dts/Bindings/mfd/arizona.txt +++ b/dts/Bindings/mfd/arizona.txt @@ -10,6 +10,9 @@ Required properties: "wlf,wm5110" "wlf,wm8280" "wlf,wm8997" + "wlf,wm8998" + "wlf,wm1814" + - reg : I2C slave address when connected using I2C, chip select number when using SPI. @@ -31,10 +34,10 @@ Required properties: as covered in Documentation/devicetree/bindings/regulator/regulator.txt - DBVDD2-supply, DBVDD3-supply : Additional databus power supplies (wm5102, - wm5110, wm8280) + wm5110, wm8280, wm8998, wm1814) - SPKVDDL-supply, SPKVDDR-supply : Speaker driver power supplies (wm5102, - wm5110, wm8280) + wm5110, wm8280, wm8998, wm1814) - SPKVDD-supply : Speaker driver power supply (wm8997) @@ -53,8 +56,10 @@ Optional properties: of input signals. Valid values are 0 (Differential), 1 (Single-ended) and 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. If present, values must be specified less than or equal to the number of - input singals. If values less than the number of input signals, elements - that has not been specifed are set to 0 by default. + input signals. If values less than the number of input signals, elements + that have not been specified are set to 0 by default. Entries are: + (wm5102, wm5110, wm8280, wm8997) + (wm8998, wm1814) - wlf,dmic-ref : DMIC reference voltage source for each input, can be selected from either MICVDD or one of the MICBIAS's, defines @@ -62,6 +67,12 @@ Optional properties: present, the number of values should be less than or equal to the number of inputs, unspecified inputs will use the chip default. + - wlf,hpdet-channel : Headphone detection channel. + ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL + ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR + If this node is not mentioned or if the value is unknown, then + headphone detection mode is set to HPDETL. + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if they are being externally supplied. As covered in Documentation/devicetree/bindings/regulator/regulator.txt diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt index 98685f291a..753f14f46e 100644 --- a/dts/Bindings/mfd/axp20x.txt +++ b/dts/Bindings/mfd/axp20x.txt @@ -1,15 +1,16 @@ -AXP202/AXP209 device tree bindings +AXP family PMIC device tree bindings The axp20x family current members : axp202 (X-Powers) axp209 (X-Powers) +axp221 (X-Powers) Required properties: -- compatible: "x-powers,axp202" or "x-powers,axp209" +- compatible: "x-powers,axp202", "x-powers,axp209", "x-powers,axp221" - reg: The I2C slave address for the AXP chip - interrupt-parent: The parent interrupt controller - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin -- interrupt-controller: axp20x has its own internal IRQs +- interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 Optional properties: @@ -48,6 +49,31 @@ LDO3 : LDO : ldo3in-supply LDO4 : LDO : ldo24in-supply : shared supply LDO5 : LDO : ldo5in-supply +AXP221 regulators, type, and corresponding input supply names: + +Regulator Type Supply Name Notes +--------- ---- ----------- ----- +DCDC1 : DC-DC buck : vin1-supply +DCDC2 : DC-DC buck : vin2-supply +DCDC3 : DC-DC buck : vin3-supply +DCDC4 : DC-DC buck : vin4-supply +DCDC5 : DC-DC buck : vin5-supply +DC1SW : On/Off Switch : dcdc1-supply : DCDC1 secondary output +DC5LDO : LDO : dcdc5-supply : input from DCDC5 +ALDO1 : LDO : aldoin-supply : shared supply +ALDO2 : LDO : aldoin-supply : shared supply +ALDO3 : LDO : aldoin-supply : shared supply +DLDO1 : LDO : dldoin-supply : shared supply +DLDO2 : LDO : dldoin-supply : shared supply +DLDO3 : LDO : dldoin-supply : shared supply +DLDO4 : LDO : dldoin-supply : shared supply +ELDO1 : LDO : eldoin-supply : shared supply +ELDO2 : LDO : eldoin-supply : shared supply +ELDO3 : LDO : eldoin-supply : shared supply +LDO_IO0 : LDO : ips-supply : GPIO 0 +LDO_IO1 : LDO : ips-supply : GPIO 1 +RTC_LDO : LDO : ips-supply : always on + Example: axp209: pmic@34 { diff --git a/dts/Bindings/mfd/cros-ec.txt b/dts/Bindings/mfd/cros-ec.txt index 8009c3d87f..1777916e9e 100644 --- a/dts/Bindings/mfd/cros-ec.txt +++ b/dts/Bindings/mfd/cros-ec.txt @@ -18,6 +18,10 @@ Required properties (SPI): - reg: SPI chip select Optional properties (SPI): +- google,cros-ec-spi-pre-delay: Some implementations of the EC need a little + time to wake up from sleep before they can receive SPI transfers at a high + clock rate. This property specifies the delay, in usecs, between the + assertion of the CS to the start of the first clock pulse. - google,cros-ec-spi-msg-delay: Some implementations of the EC require some additional processing time in order to accept new transactions. If the delay between transactions is not long enough the EC may not be able to respond diff --git a/dts/Bindings/mfd/da9063.txt b/dts/Bindings/mfd/da9063.txt index 42c6fa6f1c..05b21bcb85 100644 --- a/dts/Bindings/mfd/da9063.txt +++ b/dts/Bindings/mfd/da9063.txt @@ -5,6 +5,7 @@ DA9093 consists of a large and varied group of sub-devices (I2C Only): Device Supply Names Description ------ ------------ ----------- da9063-regulator : : LDOs & BUCKs +da9063-onkey : : On Key da9063-rtc : : Real-Time Clock da9063-watchdog : : Watchdog @@ -51,6 +52,18 @@ Sub-nodes: the DA9063. There are currently no entries in this binding, however compatible = "dlg,da9063-rtc" should be added if a node is created. +- onkey : This node defines the OnKey settings for controlling the key + functionality of the device. The node should contain the compatible property + with the value "dlg,da9063-onkey". + + Optional onkey properties: + + - dlg,disable-key-power : Disable power-down using a long key-press. If this + entry exists the OnKey driver will remove support for the KEY_POWER key + press. If this entry does not exist then by default the key-press + triggered power down is enabled and the OnKey will support both KEY_POWER + and KEY_SLEEP. + - watchdog : This node defines settings for the Watchdog timer associated with the DA9063. There are currently no entries in this binding, however compatible = "dlg,da9063-watchdog" should be added if a node is created. @@ -73,6 +86,11 @@ Example: compatible = "dlg,da9063-watchdog"; }; + onkey { + compatible = "dlg,da9063-onkey"; + dlg,disable-key-power; + }; + regulators { DA9063_BCORE1: bcore1 { regulator-name = "BCORE1"; diff --git a/dts/Bindings/mfd/max77686.txt b/dts/Bindings/mfd/max77686.txt index e39f0bc1f5..163bd81a46 100644 --- a/dts/Bindings/mfd/max77686.txt +++ b/dts/Bindings/mfd/max77686.txt @@ -1,6 +1,6 @@ Maxim MAX77686 multi-function device -MAX77686 is a Mulitifunction device with PMIC, RTC and Charger on chip. It is +MAX77686 is a Multifunction device with PMIC, RTC and Charger on chip. It is interfaced to host controller using i2c interface. PMIC and Charger submodules are addressed using same i2c slave address whereas RTC submodule uses different i2c slave address,presently for which we are statically creating i2c diff --git a/dts/Bindings/mfd/max77693.txt b/dts/Bindings/mfd/max77693.txt index 38e64405e9..d3425846aa 100644 --- a/dts/Bindings/mfd/max77693.txt +++ b/dts/Bindings/mfd/max77693.txt @@ -76,7 +76,60 @@ Optional properties: Valid values: 4300000, 4700000, 4800000, 4900000 Default: 4300000 +- led : the LED submodule device node + +There are two LED outputs available - FLED1 and FLED2. Each of them can +control a separate LED or they can be connected together to double +the maximum current for a single connected LED. One LED is represented +by one child node. + +Required properties: +- compatible : Must be "maxim,max77693-led". + +Optional properties: +- maxim,boost-mode : + In boost mode the device can produce up to 1.2A of total current + on both outputs. The maximum current on each output is reduced + to 625mA then. If not enabled explicitly, boost setting defaults to + LEDS_BOOST_FIXED in case both current sources are used. + Possible values: + LEDS_BOOST_OFF (0) - no boost, + LEDS_BOOST_ADAPTIVE (1) - adaptive mode, + LEDS_BOOST_FIXED (2) - fixed mode. +- maxim,boost-mvout : Output voltage of the boost module in millivolts. + Valid values: 3300 - 5500, step by 25 (rounded down) + Default: 3300 +- maxim,mvsys-min : Low input voltage level in millivolts. Flash is not fired + if chip estimates that system voltage could drop below this level due + to flash power consumption. + Valid values: 2400 - 3400, step by 33 (rounded down) + Default: 2400 + +Required properties for the LED child node: +- led-sources : see Documentation/devicetree/bindings/leds/common.txt; + device current output identifiers: 0 - FLED1, 1 - FLED2 +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Valid values for a LED connected to one FLED output: + 15625 - 250000, step by 15625 (rounded down) + Valid values for a LED connected to both FLED outputs: + 15625 - 500000, step by 15625 (rounded down) +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + Valid values for a single LED connected to one FLED output + (boost mode must be turned off): + 15625 - 1000000, step by 15625 (rounded down) + Valid values for a single LED connected to both FLED outputs: + 15625 - 1250000, step by 15625 (rounded down) + Valid values for two LEDs case: + 15625 - 625000, step by 15625 (rounded down) +- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt + Valid values: 62500 - 1000000, step by 62500 (rounded down) + +Optional properties for the LED child node: +- label : see Documentation/devicetree/bindings/leds/common.txt + Example: +#include + max77693@66 { compatible = "maxim,max77693"; reg = <0x66>; @@ -117,5 +170,19 @@ Example: maxim,thermal-regulation-celsius = <75>; maxim,battery-overcurrent-microamp = <3000000>; maxim,charge-input-threshold-microvolt = <4300000>; + + led { + compatible = "maxim,max77693-led"; + maxim,boost-mode = ; + maxim,boost-mvout = <5000>; + maxim,mvsys-min = <2400>; + + camera_flash: flash-led { + label = "max77693-flash"; + led-sources = <0>, <1>; + led-max-microamp = <500000>; + flash-max-microamp = <1250000>; + flash-max-timeout-us = <1000000>; + }; }; }; diff --git a/dts/Bindings/mfd/mfd.txt b/dts/Bindings/mfd/mfd.txt new file mode 100644 index 0000000000..af9d6931a1 --- /dev/null +++ b/dts/Bindings/mfd/mfd.txt @@ -0,0 +1,41 @@ +Multi-Function Devices (MFD) + +These devices comprise a nexus for heterogeneous hardware blocks containing +more than one non-unique yet varying hardware functionality. + +A typical MFD can be: + +- A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management + Integrated Circuit) that is manufactured in a lower technology node (rough + silicon) that handles analog drivers for things like audio amplifiers, LED + drivers, level shifters, PHY (physical interfaces to things like USB or + ethernet), regulators etc. + +- A range of memory registers containing "miscellaneous system registers" also + known as a system controller "syscon" or any other memory range containing a + mix of unrelated hardware devices. + +Optional properties: + +- compatible : "simple-mfd" - this signifies that the operating system should + consider all subnodes of the MFD device as separate devices akin to how + "simple-bus" inidicates when to see subnodes as children for a simple + memory-mapped bus. For more complex devices, when the nexus driver has to + probe registers to figure out what child devices exist etc, this should not + be used. In the latter case the child devices will be determined by the + operating system. + +Example: + +foo@1000 { + compatible = "syscon", "simple-mfd"; + reg = <0x01000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "myled"; + default-state = "on"; + }; +}; diff --git a/dts/Bindings/mfd/tps6507x.txt b/dts/Bindings/mfd/tps6507x.txt old mode 100755 new mode 100644 diff --git a/dts/Bindings/mips/ath79-soc.txt b/dts/Bindings/mips/ath79-soc.txt new file mode 100644 index 0000000000..88a12a43e4 --- /dev/null +++ b/dts/Bindings/mips/ath79-soc.txt @@ -0,0 +1,21 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC + +Each device tree must specify a compatible value for the AR SoC +it uses in the compatible property of the root node. The compatible +value must be one of the following values: + +- qca,ar7130 +- qca,ar7141 +- qca,ar7161 +- qca,ar7240 +- qca,ar7241 +- qca,ar7242 +- qca,ar9130 +- qca,ar9132 +- qca,ar9330 +- qca,ar9331 +- qca,ar9341 +- qca,ar9342 +- qca,ar9344 +- qca,qca9556 +- qca,qca9558 diff --git a/dts/Bindings/misc/nvidia,tegra20-apbmisc.txt b/dts/Bindings/misc/nvidia,tegra20-apbmisc.txt index 47b205cc9c..4556359c58 100644 --- a/dts/Bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/dts/Bindings/misc/nvidia,tegra20-apbmisc.txt @@ -10,3 +10,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt index 98ee2abbe1..7e9490313d 100644 --- a/dts/Bindings/mmc/arasan,sdhci.txt +++ b/dts/Bindings/mmc/arasan,sdhci.txt @@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' + - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or + 'arasan,sdhci-4.9a' - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.txt b/dts/Bindings/mmc/fsl-imx-esdhc.txt index 415c5575cb..5d0376b8f2 100644 --- a/dts/Bindings/mmc/fsl-imx-esdhc.txt +++ b/dts/Bindings/mmc/fsl-imx-esdhc.txt @@ -7,7 +7,14 @@ This file documents differences between the core properties described by mmc.txt and the properties used by the sdhci-esdhc-imx driver. Required properties: -- compatible : Should be "fsl,-esdhc" +- compatible : Should be "fsl,-esdhc", the supported chips include + "fsl,imx25-esdhc" + "fsl,imx35-esdhc" + "fsl,imx51-esdhc" + "fsl,imx53-esdhc" + "fsl,imx6q-usdhc" + "fsl,imx6sl-usdhc" + "fsl,imx6sx-usdhc" Optional properties: - fsl,cd-controller : Indicate to use controller internal card detection diff --git a/dts/Bindings/mmc/k3-dw-mshc.txt b/dts/Bindings/mmc/k3-dw-mshc.txt index 3b35449314..df370585cb 100644 --- a/dts/Bindings/mmc/k3-dw-mshc.txt +++ b/dts/Bindings/mmc/k3-dw-mshc.txt @@ -13,6 +13,10 @@ Required Properties: * compatible: should be one of the following. - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions. + - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions. + +Optional Properties: +- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. Example: @@ -42,3 +46,27 @@ Example: cap-mmc-highspeed; cap-sd-highspeed; }; + + /* for Hi6220 */ + + dwmmc_1: dwmmc1@f723e000 { + compatible = "hisilicon,hi6220-dw-mshc"; + num-slots = <0x1>; + bus-width = <0x4>; + disable-wp; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + card-detect-delay = <200>; + hisilicon,peripheral-syscon = <&ao_ctrl>; + reg = <0x0 0xf723e000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>; + clock-names = "ciu", "biu"; + cd-gpios = <&gpio1 0 1>; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; + vqmmc-supply = <&ldo7>; + vmmc-supply = <&ldo10>; + }; diff --git a/dts/Bindings/mmc/mmc-pwrseq-simple.txt b/dts/Bindings/mmc/mmc-pwrseq-simple.txt index a462c50f19..ce0e767496 100644 --- a/dts/Bindings/mmc/mmc-pwrseq-simple.txt +++ b/dts/Bindings/mmc/mmc-pwrseq-simple.txt @@ -21,5 +21,7 @@ Example: sdhci0_pwrseq { compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 12 0>; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + clocks = <&clk_32768_ck>; + clock-names = "ext_clock"; } diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt index 438899e882..0384fc3f64 100644 --- a/dts/Bindings/mmc/mmc.txt +++ b/dts/Bindings/mmc/mmc.txt @@ -21,6 +21,11 @@ Optional properties: below for the case, when a GPIO is used for the CD line - wp-inverted: when present, polarity on the WP line is inverted. See the note below for the case, when a GPIO is used for the WP line +- disable-wp: When set no physical WP line is present. This property should + only be specified when the controller has a dedicated write-protect + detection logic. If a GPIO is always used for the write-protect detection + logic it is sufficient to not specify wp-gpios property in the absence of a WP + line. - max-frequency: maximum operating clock frequency - no-1-8-v: when present, denotes that 1.8v card voltage is not supported on this system, even if the controller claims it is. diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt new file mode 100644 index 0000000000..a1adfa495a --- /dev/null +++ b/dts/Bindings/mmc/mtk-sd.txt @@ -0,0 +1,32 @@ +* MTK MMC controller + +The MTK MSDC can act as a MMC controller +to support MMC, SD, and SDIO types of memory cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the msdc driver. + +Required properties: +- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc" +- interrupts: Should contain MSDC interrupt number +- clocks: MSDC source clock, HCLK +- clock-names: "source", "hclk" +- pinctrl-names: should be "default", "state_uhs" +- pinctrl-0: should contain default/high speed pin ctrl +- pinctrl-1: should contain uhs mode pin ctrl +- vmmc-supply: power to the Core +- vqmmc-supply: power to the IO + +Examples: +mmc0: mmc@11230000 { + compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x108>; + interrupts = ; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; +}; diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt index 299081f94a..d38942f6c5 100644 --- a/dts/Bindings/mmc/renesas,mmcif.txt +++ b/dts/Bindings/mmc/renesas,mmcif.txt @@ -18,6 +18,8 @@ Required properties: dma-names property. - dma-names: must contain "tx" for the transmit DMA channel and "rx" for the receive DMA channel. +- max-frequency: Maximum operating clock frequency, driver uses default clock + frequency if it is not set. Example: R8A7790 (R-Car H2) MMCIF0 @@ -29,4 +31,5 @@ Example: R8A7790 (R-Car H2) MMCIF0 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; dma-names = "tx", "rx"; + max-frequency = <97500000>; }; diff --git a/dts/Bindings/mtd/brcm,brcmnand.txt b/dts/Bindings/mtd/brcm,brcmnand.txt new file mode 100644 index 0000000000..4ff7128ee3 --- /dev/null +++ b/dts/Bindings/mtd/brcm,brcmnand.txt @@ -0,0 +1,150 @@ +* Broadcom STB NAND Controller + +The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND +flash chips. It has a memory-mapped register interface for both control +registers and for its data input/output buffer. On some SoCs, this controller is +paired with a custom DMA engine (inventively named "Flash DMA") which supports +basic PROGRAM and READ functions, among other features. + +This controller was originally designed for STB SoCs (BCM7xxx) but is now +available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and +iProc/Cygnus. Its history includes several similar (but not fully register +compatible) versions. + +Required properties: +- compatible : May contain an SoC-specific compatibility string (see below) + to account for any SoC-specific hardware bits that may be + added on top of the base core controller. + In addition, must contain compatibility information about + the core NAND controller, of the following form: + "brcm,brcmnand" and an appropriate version compatibility + string, like "brcm,brcmnand-v7.0" + Possible values: + brcm,brcmnand-v4.0 + brcm,brcmnand-v5.0 + brcm,brcmnand-v6.0 + brcm,brcmnand-v6.1 + brcm,brcmnand-v7.0 + brcm,brcmnand-v7.1 + brcm,brcmnand +- reg : the register start and length for NAND register region. + (optional) Flash DMA register range (if present) + (optional) NAND flash cache range (if at non-standard offset) +- reg-names : a list of the names corresponding to the previous register + ranges. Should contain "nand" and (optionally) + "flash-dma" and/or "nand-cache". +- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) + FLASH_DMA_DONE +- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as + individual interrupts. + May be "nand", if the SoC has the individual NAND + interrupts multiplexed behind another custom piece of + hardware +- interrupt-parent : See standard interrupt bindings +- #address-cells : <1> - subnodes give the chip-select number +- #size-cells : <0> + +Optional properties: +- brcm,nand-has-wp : Some versions of this IP include a write-protect + (WP) control bit. It is always available on >= + v7.0. Use this property to describe the rare + earlier versions of this core that include WP + + -- Additonal SoC-specific NAND controller properties -- + +The NAND controller is integrated differently on the variety of SoCs on which it +is found. Part of this integration involves providing status and enable bits +with which to control the 8 exposed NAND interrupts, as well as hardware for +configuring the endianness of the data bus. On some SoCs, these features are +handled via standard, modular components (e.g., their interrupts look like a +normal IRQ chip), but on others, they are controlled in unique and interesting +ways, sometimes with registers that lump multiple NAND-related functions +together. The former case can be described simply by the standard interrupts +properties in the main controller node. But for the latter exceptional cases, +we define additional 'compatible' properties and associated register resources within the NAND controller node above. + + - compatible: Can be one of several SoC-specific strings. Each SoC may have + different requirements for its additional properties, as described below each + bullet point below. + + * "brcm,nand-bcm63138" + - reg: (required) the 'NAND_INT_BASE' register range, with separate status + and enable registers + - reg-names: (required) "nand-int-base" + + * "brcm,nand-iproc" + - reg: (required) the "IDM" register range, for interrupt enable and APB + bus access endianness configuration, and the "EXT" register range, + for interrupt status/ack. + - reg-names: (required) a list of the names corresponding to the previous + register ranges. Should contain "iproc-idm" and "iproc-ext". + + +* NAND chip-select + +Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes +to represent enabled chip-selects which (may) contain NAND flash chips. Their +properties are as follows. + +Required properties: +- compatible : should contain "brcm,nandcs" +- reg : a single integer representing the chip-select + number (e.g., 0, 1, 2, etc.) +- #address-cells : see partition.txt +- #size-cells : see partition.txt +- nand-ecc-strength : see nand.txt +- nand-ecc-step-size : must be 512 or 1024. See nand.txt + +Optional properties: +- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this + chip-select. See nand.txt +- brcm,nand-oob-sector-size : integer, to denote the spare area sector size + expected for the ECC layout in use. This size, in + addition to the strength and step-size, + determines how the hardware BCH engine will lay + out the parity bytes it stores on the flash. + This property can be automatically determined by + the flash geometry (particularly the NAND page + and OOB size) in many cases, but when booting + from NAND, the boot controller has only a limited + number of available options for its default ECC + layout. + +Each nandcs device node may optionally contain sub-nodes describing the flash +partition mapping. See partition.txt for more detail. + + +Example: + +nand@f0442800 { + compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; + reg = <0xF0442800 0x600>, + <0xF0443000 0x100>; + reg-names = "nand", "flash-dma"; + interrupt-parent = <&hif_intr2_intc>; + interrupts = <24>, <4>; + + #address-cells = <1>; + #size-cells = <0>; + + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <1>; // Chip select 1 + nand-on-flash-bbt; + nand-ecc-strength = <12>; + nand-ecc-step-size = <512>; + + // Partitions + #address-cells = <1>; // <2>, for 64-bit offset + #size-cells = <1>; // <2>, for 64-bit length + flash0.rootfs@0 { + reg = <0 0x10000000>; + }; + flash0@0 { + reg = <0 0>; // MTDPART_SIZ_FULL + }; + flash0.kernel@10000000 { + reg = <0x10000000 0x400000>; + }; + }; +}; diff --git a/dts/Bindings/net/amd-xgbe-phy.txt b/dts/Bindings/net/amd-xgbe-phy.txt deleted file mode 100644 index 8db32384a4..0000000000 --- a/dts/Bindings/net/amd-xgbe-phy.txt +++ /dev/null @@ -1,48 +0,0 @@ -* AMD 10GbE PHY driver (amd-xgbe-phy) - -Required properties: -- compatible: Should be "amd,xgbe-phy-seattle-v1a" and - "ethernet-phy-ieee802.3-c45" -- reg: Address and length of the register sets for the device - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device -- interrupts: Should contain the amd-xgbe-phy interrupt. - -Optional properties: -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe_phy@e1240800 { - compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45"; - reg = <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 323 4>; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/dts/Bindings/net/amd-xgbe.txt b/dts/Bindings/net/amd-xgbe.txt index 26efd526d1..4bb624a73b 100644 --- a/dts/Bindings/net/amd-xgbe.txt +++ b/dts/Bindings/net/amd-xgbe.txt @@ -5,12 +5,16 @@ Required properties: - reg: Address and length of the register sets for the device - MAC registers - PCS registers + - SerDes Rx/Tx registers + - SerDes integration registers (1/2) + - SerDes integration registers (2/2) - interrupt-parent: Should be the phandle for the interrupt controller that services interrupts for this device - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt listed is required and is the general device interrupt. If the optional amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified + interrupt for each DMA channel supported by the device should be specified. + The last interrupt listed should be the PCS auto-negotiation interrupt. - clocks: - DMA clock for the amd-xgbe device (used for calculating the correct Rx interrupt watchdog timer value on a DMA channel @@ -19,7 +23,6 @@ Required properties: - clock-names: Should be the names of the clocks - "dma_clk" for the DMA clock - "ptp_clk" for the PTP clock -- phy-handle: See ethernet.txt file in the same directory - phy-mode: See ethernet.txt file in the same directory Optional properties: @@ -29,19 +32,46 @@ Optional properties: - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate a unique interrupt for each DMA channel - this requires an additional interrupt be configured for each DMA channel +- amd,speed-set: Speed capabilities of the device + 0 - 1GbE and 10GbE (default) + 1 - 2.5GbE and 10GbE + +The following optional properties are represented by an array with each +value corresponding to a particular speed. The first array value represents +the setting for the 1GbE speed, the second value for the 2.5GbE speed and +the third value for the 10GbE speed. All three values are required if the +property is used. +- amd,serdes-blwc: Baseline wandering correction enablement + 0 - Off + 1 - On +- amd,serdes-cdr-rate: CDR rate speed selection +- amd,serdes-pq-skew: PQ (data sampling) skew +- amd,serdes-tx-amp: TX amplitude boost +- amd,serdes-dfe-tap-config: DFE taps available to run +- amd,serdes-dfe-tap-enable: DFE taps to enable Example: xgbe@e0700000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>; + <0 0xe0780000 0 0x80000>, + <0 0xe1240800 0 0x00400>, + <0 0xe1250000 0 0x00060>, + <0 0xe1250080 0 0x00004>; interrupt-parent = <&gic>; interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>; + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, + <0 323 4>; amd,per-channel-interrupt; clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <&phy>; phy-mode = "xgmii"; mac-address = [ 02 a1 a2 a3 a4 a5 ]; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <30>; + amd,serdes-tx-amp = <15>, <15>, <10>; + amd,serdes-dfe-tap-config = <3>, <3>, <1>; + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; }; diff --git a/dts/Bindings/net/ezchip_enet.txt b/dts/Bindings/net/ezchip_enet.txt new file mode 100644 index 0000000000..4e29b2b828 --- /dev/null +++ b/dts/Bindings/net/ezchip_enet.txt @@ -0,0 +1,15 @@ +* EZchip NPS Management Ethernet port driver + +Required properties: +- compatible: Should be "ezchip,nps-mgt-enet" +- reg: Address and length of the register set for the device +- interrupts: Should contain the ENET interrupt + +Examples: + + ethernet@f0003000 { + compatible = "ezchip,nps-mgt-enet"; + reg = <0xf0003000 0x44>; + interrupts = <7>; + mac-address = [ 00 11 22 33 44 55 ]; + }; diff --git a/dts/Bindings/net/ipq806x-dwmac.txt b/dts/Bindings/net/ipq806x-dwmac.txt new file mode 100644 index 0000000000..6d7ab4e524 --- /dev/null +++ b/dts/Bindings/net/ipq806x-dwmac.txt @@ -0,0 +1,35 @@ +* IPQ806x DWMAC Ethernet controller + +The device inherits all the properties of the dwmac/stmmac devices +described in the file net/stmmac.txt with the following changes. + +Required properties: + +- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" + and any applicable more detailed version number + described in net/stmmac.txt + +- qcom,nss-common: should contain a phandle to a syscon device mapping the + nss-common registers. + +- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the + qsgmii-csr registers. + +Example: + + gmac: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + }; diff --git a/dts/Bindings/net/macb.txt b/dts/Bindings/net/macb.txt index ba19d671e8..b5d79761ac 100644 --- a/dts/Bindings/net/macb.txt +++ b/dts/Bindings/net/macb.txt @@ -7,8 +7,10 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem". - Use "cdns,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. - Use "cdns,sama5d4-gem" for the Gigabit IP available on Atmel sama5d4 SoCs. + Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. + Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. + Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. + Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: See ethernet.txt file in the same directory. diff --git a/dts/Bindings/net/marvell-armada-370-neta.txt b/dts/Bindings/net/marvell-armada-370-neta.txt index 750d577e80..f5a8ca29af 100644 --- a/dts/Bindings/net/marvell-armada-370-neta.txt +++ b/dts/Bindings/net/marvell-armada-370-neta.txt @@ -1,7 +1,7 @@ * Marvell Armada 370 / Armada XP Ethernet Controller (NETA) Required properties: -- compatible: should be "marvell,armada-370-neta". +- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta". - reg: address and length of the register set for the device. - interrupts: interrupt for the device - phy: See ethernet.txt file in the same directory. diff --git a/dts/Bindings/net/nfc/nfcmrvl.txt b/dts/Bindings/net/nfc/nfcmrvl.txt new file mode 100644 index 0000000000..7c4a0cc370 --- /dev/null +++ b/dts/Bindings/net/nfc/nfcmrvl.txt @@ -0,0 +1,29 @@ +* Marvell International Ltd. NCI NFC Controller + +Required properties: +- compatible: Should be "mrvl,nfc-uart". + +Optional SoC specific properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. +- reset-n-io: Output GPIO pin used to reset the chip (active low). +- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. + +Optional UART-based chip specific properties: +- flow-control: Specifies that the chip is using RTS/CTS. +- break-control: Specifies that the chip needs specific break management. + +Example (for ARM-based BeagleBoard Black with 88W8887 on UART5): + +&uart5 { + status = "okay"; + + nfcmrvluart: nfcmrvluart@5 { + compatible = "mrvl,nfc-uart"; + + reset-n-io = <&gpio3 16 0>; + + hci-muxed; + flow-control; + } +}; diff --git a/dts/Bindings/net/nfc/st-nci.txt b/dts/Bindings/net/nfc/st-nci.txt new file mode 100644 index 0000000000..d707588ed7 --- /dev/null +++ b/dts/Bindings/net/nfc/st-nci.txt @@ -0,0 +1,33 @@ +* STMicroelectronics SAS. ST NCI NFC Controller + +Required properties: +- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". +- clock-frequency: I²C work frequency. +- reg: address on the bus +- interrupt-parent: phandle for the interrupt gpio controller +- interrupts: GPIO interrupt to which the chip is connected +- reset-gpios: Output GPIO pin used to reset the ST21NFCB + +Optional SoC Specific Properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. + +Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): + +&i2c2 { + + status = "okay"; + + st21nfcb: st21nfcb@8 { + + compatible = "st,st21nfcb-i2c"; + + reg = <0x08>; + clock-frequency = <400000>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/dts/Bindings/net/nfc/st21nfcb.txt b/dts/Bindings/net/nfc/st21nfcb.txt deleted file mode 100644 index bb237072db..0000000000 --- a/dts/Bindings/net/nfc/st21nfcb.txt +++ /dev/null @@ -1,33 +0,0 @@ -* STMicroelectronics SAS. ST21NFCB NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupt-parent: phandle for the interrupt gpio controller -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): - -&i2c2 { - - status = "okay"; - - st21nfcb: st21nfcb@8 { - - compatible = "st,st21nfcb-i2c"; - - reg = <0x08>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/dts/Bindings/net/nfc/trf7970a.txt b/dts/Bindings/net/nfc/trf7970a.txt index 7c89ca290c..32b35a07ab 100644 --- a/dts/Bindings/net/nfc/trf7970a.txt +++ b/dts/Bindings/net/nfc/trf7970a.txt @@ -18,6 +18,9 @@ Optional SoC Specific Properties: "IRQ Status Read" erratum. - en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" erratum. +- t5t-rmb-extra-byte-quirk: Specify that the trf7970a has the erratum + where an extra byte is returned by Read Multiple Block commands issued + to Type 5 tags. Example (for ARM-based BeagleBone with TRF7970A on SPI1): @@ -39,6 +42,7 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1): autosuspend-delay = <30000>; irq-status-read-quirk; en2-rf-quirk; + t5t-rmb-extra-byte-quirk; status = "okay"; }; }; diff --git a/dts/Bindings/net/nxp,lpc1850-dwmac.txt b/dts/Bindings/net/nxp,lpc1850-dwmac.txt new file mode 100644 index 0000000000..7edba1264f --- /dev/null +++ b/dts/Bindings/net/nxp,lpc1850-dwmac.txt @@ -0,0 +1,20 @@ +* NXP LPC1850 GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: + - compatible: Should contain "nxp,lpc1850-dwmac" + +Examples: + +mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + resets = <&rgu 22>; + reset-names = "stmmaceth"; +} diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt index 40831fbaff..525e1658f2 100644 --- a/dts/Bindings/net/phy.txt +++ b/dts/Bindings/net/phy.txt @@ -30,6 +30,9 @@ Optional Properties: - max-speed: Maximum PHY supported speed (10, 100, 1000...) +- broken-turn-around: If set, indicates the PHY device does not correctly + release the turn around line low at the end of a MDIO transaction. + Example: ethernet-phy@0 { diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt new file mode 100644 index 0000000000..1fd8831437 --- /dev/null +++ b/dts/Bindings/net/renesas,ravb.txt @@ -0,0 +1,48 @@ +* Renesas Electronics Ethernet AVB + +This file provides information on what the device node for the Ethernet AVB +interface contains. + +Required properties: +- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC. + "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC. +- reg: offset and length of (1) the register block and (2) the stream buffer. +- interrupts: interrupt specifier for the sole interrupt. +- phy-mode: see ethernet.txt file in the same directory. +- phy-handle: see ethernet.txt file in the same directory. +- #address-cells: number of address cells for the MDIO bus, must be equal to 1. +- #size-cells: number of size cells on the MDIO bus, must be equal to 0. +- clocks: clock phandle and specifier pair. +- pinctrl-0: phandle, referring to a default pin configuration node. + +Optional properties: +- interrupt-parent: the phandle for the interrupt controller that services + interrupts for this device. +- pinctrl-names: pin configuration state name ("default"). +- renesas,no-ether-link: boolean, specify when a board does not provide a proper + AVB_LINK signal. +- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is + active-low instead of normal active-high. + +Example: + + ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupt-parent = <&gic>; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt index 21fd199e89..93eac7ce14 100644 --- a/dts/Bindings/net/rockchip-dwmac.txt +++ b/dts/Bindings/net/rockchip-dwmac.txt @@ -3,7 +3,7 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) The device node has following properties. Required properties: - - compatible: Can be "rockchip,rk3288-gmac". + - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac" - reg: addresses and length of the register sets for the device. - interrupts: Should contain the GMAC interrupts. - interrupt-names: Should contain the interrupt names "macirq". diff --git a/dts/Bindings/net/ti,dp83867.txt b/dts/Bindings/net/ti,dp83867.txt new file mode 100644 index 0000000000..58d935b585 --- /dev/null +++ b/dts/Bindings/net/ti,dp83867.txt @@ -0,0 +1,25 @@ +* Texas Instruments - dp83867 Giga bit ethernet phy + +Required properties: + - reg - The ID number for the phy, usually a small integer + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h + for applicable values + +Default child nodes are standard Ethernet PHY device +nodes as described in Documentation/devicetree/bindings/net/phy.txt + +Example: + + ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + }; + +Datasheet can be found: +http://www.ti.com/product/DP83867IR/datasheet diff --git a/dts/Bindings/panel/hannstar,hsd100pxn1.txt b/dts/Bindings/panel/hannstar,hsd100pxn1.txt new file mode 100644 index 0000000000..8270319a99 --- /dev/null +++ b/dts/Bindings/panel/hannstar,hsd100pxn1.txt @@ -0,0 +1,7 @@ +HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel + +Required properties: +- compatible: should be "hannstar,hsd100pxn1" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/panel/lg,lb070wv8.txt b/dts/Bindings/panel/lg,lb070wv8.txt new file mode 100644 index 0000000000..a7588e5259 --- /dev/null +++ b/dts/Bindings/panel/lg,lb070wv8.txt @@ -0,0 +1,7 @@ +LG 7" (800x480 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lb070wv8" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/dts/Bindings/pci/xgene-pci-msi.txt b/dts/Bindings/pci/xgene-pci-msi.txt new file mode 100644 index 0000000000..36d881c8e6 --- /dev/null +++ b/dts/Bindings/pci/xgene-pci-msi.txt @@ -0,0 +1,68 @@ +* AppliedMicro X-Gene v1 PCIe MSI controller + +Required properties: + +- compatible: should be "apm,xgene1-msi" to identify + X-Gene v1 PCIe MSI controller block. +- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node +- reg: physical base address (0x79000000) and length (0x900000) for controller + registers. These registers include the MSI termination address and data + registers as well as the MSI interrupt status registers. +- reg-names: not required +- interrupts: A list of 16 interrupt outputs of the controller, starting from + interrupt number 0x10 to 0x1f. +- interrupt-names: not required + +Each PCIe node needs to have property msi-parent that points to msi controller node + +Examples: + +SoC DTSI: + + + MSI node: + msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = <0x0 0x10 0x4> + <0x0 0x11 0x4> + <0x0 0x12 0x4> + <0x0 0x13 0x4> + <0x0 0x14 0x4> + <0x0 0x15 0x4> + <0x0 0x16 0x4> + <0x0 0x17 0x4> + <0x0 0x18 0x4> + <0x0 0x19 0x4> + <0x0 0x1a 0x4> + <0x0 0x1b 0x4> + <0x0 0x1c 0x4> + <0x0 0x1d 0x4> + <0x0 0x1e 0x4> + <0x0 0x1f 0x4>; + }; + + + PCIe controller node with msi-parent property pointing to MSI node: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent= <&msi>; + }; diff --git a/dts/Bindings/pci/xilinx-pcie.txt b/dts/Bindings/pci/xilinx-pcie.txt index 3e2c88d97a..02f979a48a 100644 --- a/dts/Bindings/pci/xilinx-pcie.txt +++ b/dts/Bindings/pci/xilinx-pcie.txt @@ -58,5 +58,5 @@ Example: interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; - } + }; }; diff --git a/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt b/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt new file mode 100644 index 0000000000..7f81ef9014 --- /dev/null +++ b/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt @@ -0,0 +1,40 @@ +* Broadcom SATA3 PHY for STB + +Required properties: +- compatible: should be one or more of + "brcm,bcm7445-sata-phy" + "brcm,phy-sata3" +- address-cells: should be 1 +- size-cells: should be 0 +- reg: register range for the PHY PCB interface +- reg-names: should be "phy" + +Sub-nodes: + Each port's PHY should be represented as a sub-node. + +Sub-nodes required properties: +- reg: the PHY number +- phy-cells: generic PHY binding; must be 0 +Optional: +- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port + + +Example: + + sata-phy@f0458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/pistachio-usb-phy.txt b/dts/Bindings/phy/pistachio-usb-phy.txt new file mode 100644 index 0000000000..afbc7e24a3 --- /dev/null +++ b/dts/Bindings/phy/pistachio-usb-phy.txt @@ -0,0 +1,29 @@ +IMG Pistachio USB PHY +===================== + +Required properties: +-------------------- + - compatible: Must be "img,pistachio-usb-phy". + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include "usb_phy". + - img,cr-top: Must constain a phandle to the CR_TOP syscon node. + - img,refclk: Indicates the reference clock source for the USB PHY. + See for a list of valid values. + +Optional properties: +-------------------- + - phy-supply: USB VBUS supply. Must supply 5.0V. + +Example: +-------- +usb_phy: usb-phy { + compatible = "img,pistachio-usb-phy"; + clocks = <&clk_core CLK_USB_PHY>; + clock-names = "usb_phy"; + phy-supply = <&usb_vbus>; + img,refclk = ; + img,cr-top = <&cr_top>; + #phy-cells = <0>; +}; diff --git a/dts/Bindings/phy/pxa1928-usb-phy.txt b/dts/Bindings/phy/pxa1928-usb-phy.txt new file mode 100644 index 0000000000..660a13ca90 --- /dev/null +++ b/dts/Bindings/phy/pxa1928-usb-phy.txt @@ -0,0 +1,18 @@ +* Marvell PXA1928 USB and HSIC PHYs + +Required properties: +- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy" +- reg: base address and length of the registers +- clocks - A single clock. From common clock binding. +- #phys-cells: should be 0. From commmon phy binding. +- resets: reference to the reset controller + +Example: + + usbphy: phy@7000 { + compatible = "marvell,pxa1928-usb-phy"; + reg = <0x7000 0xe0>; + clocks = <&apmu_clocks PXA1928_CLK_USB>; + #phy-cells = <0>; + }; + diff --git a/dts/Bindings/phy/rcar-gen2-phy.txt b/dts/Bindings/phy/rcar-gen2-phy.txt index 00fc52a034..d564ba4f1c 100644 --- a/dts/Bindings/phy/rcar-gen2-phy.txt +++ b/dts/Bindings/phy/rcar-gen2-phy.txt @@ -6,6 +6,7 @@ This file provides information on what the device node for the R-Car generation Required properties: - compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. + "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. - reg: offset and length of the register block. - #address-cells: number of address cells for the USB channel subnodes, must be <1>. diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt index fdd8046e65..9462ab7ddd 100644 --- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -16,6 +16,8 @@ Required properties: "allwinner,sun7i-a20-pinctrl" "allwinner,sun8i-a23-pinctrl" "allwinner,sun8i-a23-r-pinctrl" + "allwinner,sun8i-a33-pinctrl" + - reg: Should contain the register physical address and length for the pin controller. diff --git a/dts/Bindings/pinctrl/berlin,pinctrl.txt b/dts/Bindings/pinctrl/berlin,pinctrl.txt new file mode 100644 index 0000000000..a8bb5e2601 --- /dev/null +++ b/dts/Bindings/pinctrl/berlin,pinctrl.txt @@ -0,0 +1,43 @@ +* Pin-controller driver for the Marvell Berlin SoCs + +Pin control registers are part of both chip controller and system +controller register sets. Pin controller nodes should be a sub-node of +either the chip controller or system controller node. The pins +controlled are organized in groups, so no actual pin information is +needed. + +A pin-controller node should contain subnodes representing the pin group +configurations, one per function. Each subnode has the group name and +the muxing function used. + +Be aware the Marvell Berlin datasheets use the keyword 'mode' for what +is called a 'function' in the pin-controller subsystem. + +Required properties: +- compatible: should be one of: + "marvell,berlin2-soc-pinctrl", + "marvell,berlin2-system-pinctrl", + "marvell,berlin2cd-soc-pinctrl", + "marvell,berlin2cd-system-pinctrl", + "marvell,berlin2q-soc-pinctrl", + "marvell,berlin2q-system-pinctrl" + +Required subnode-properties: +- groups: a list of strings describing the group names. +- function: a string describing the function used to mux the groups. + +Example: + +sys_pinctrl: pin-controller { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0_pmux: uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; +}; diff --git a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt new file mode 100644 index 0000000000..8bbf25d586 --- /dev/null +++ b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -0,0 +1,27 @@ +* Freescale i.MX7 Dual IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx7d-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_PUS_100K_DOWN (0 << 5) +PAD_CTL_PUS_5K_UP (1 << 5) +PAD_CTL_PUS_47K_UP (2 << 5) +PAD_CTL_PUS_100K_UP (3 << 5) +PAD_CTL_PUE (1 << 4) +PAD_CTL_HYS (1 << 3) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_FAST (0 << 2) +PAD_CTL_DSE_X1 (0 << 0) +PAD_CTL_DSE_X2 (1 << 0) +PAD_CTL_DSE_X3 (2 << 0) +PAD_CTL_DSE_X4 (3 << 0) diff --git a/dts/Bindings/pinctrl/img,pistachio-pinctrl.txt b/dts/Bindings/pinctrl/img,pistachio-pinctrl.txt new file mode 100644 index 0000000000..08a4a32c8e --- /dev/null +++ b/dts/Bindings/pinctrl/img,pistachio-pinctrl.txt @@ -0,0 +1,217 @@ +Imagination Technologies Pistachio SoC pin controllers +====================================================== + +The pin controllers on Pistachio are a combined GPIO controller, (GPIO) +interrupt controller, and pinmux + pinconf device. The system ("east") pin +controller on Pistachio has 99 pins, 90 of which are MFIOs which can be +configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs +each. The GPIO banks are represented as sub-nodes of the pad controller node. + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +Required properties for pin controller node: +-------------------------------------------- + - compatible: "img,pistachio-system-pinctrl". + - reg: Address range of the pinctrl registers. + +Required properties for GPIO bank sub-nodes: +-------------------------------------------- + - interrupts: Interrupt line for the GPIO bank. + - gpio-controller: Indicates the device is a GPIO controller. + - #gpio-cells: Must be two. The first cell is the GPIO pin number and the + second cell indicates the polarity. See for + a list of possible values. + - interrupt-controller: Indicates the device is an interrupt controller. + - #interrupt-cells: Must be two. The first cell is the GPIO pin number and + the second cell encodes the interrupt flags. See + for a list of valid flags. + +Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. + +Required properties for pin configuration sub-nodes: +---------------------------------------------------- + - pins: List of pins to which the configuration applies. See below for a + list of possible pins. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. This is not applicable for + non-MFIO pins. See below for a list of valid functions for each pin. + - bias-high-impedance: Enable high-impedance mode. + - bias-pull-up: Enable weak pull-up. + - bias-pull-down: Enable weak pull-down. + - bias-bus-hold: Enable bus-keeper mode. + - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. + - input-schmitt-enable: Enable Schmitt trigger. + - input-schmitt-disable: Disable Schmitt trigger. + - slew-rate: Slew rate control. 0 for slow, 1 for fast. + +Pin Functions +--- --------- +mfio0 spim1 +mfio1 spim1, spim0, uart1 +mfio2 spim1, spim0, uart1 +mfio3 spim1 +mfio4 spim1 +mfio5 spim1 +mfio6 spim1 +mfio7 spim1 +mfio8 spim0 +mfio9 spim0 +mfio10 spim0 +mfio11 spis +mfio12 spis +mfio13 spis +mfio14 spis +mfio15 sdhost, mips_trace_clk, mips_trace_data +mfio16 sdhost, mips_trace_dint, mips_trace_data +mfio17 sdhost, mips_trace_trigout, mips_trace_data +mfio18 sdhost, mips_trace_trigin, mips_trace_data +mfio19 sdhost, mips_trace_dm, mips_trace_data +mfio20 sdhost, mips_trace_probe_n, mips_trace_data +mfio21 sdhost, mips_trace_data +mfio22 sdhost, mips_trace_data +mfio23 sdhost +mfio24 sdhost +mfio25 sdhost +mfio26 sdhost +mfio27 sdhost +mfio28 i2c0, spim0 +mfio29 i2c0, spim0 +mfio30 i2c1, spim0 +mfio31 i2c1, spim1 +mfio32 i2c2 +mfio33 i2c2 +mfio34 i2c3 +mfio35 i2c3 +mfio36 i2s_out, audio_clk_in +mfio37 i2s_out, debug_raw_cca_ind +mfio38 i2s_out, debug_ed_sec20_cca_ind +mfio39 i2s_out, debug_ed_sec40_cca_ind +mfio40 i2s_out, debug_agc_done_0 +mfio41 i2s_out, debug_agc_done_1 +mfio42 i2s_out, debug_ed_cca_ind +mfio43 i2s_out, debug_s2l_done +mfio44 i2s_out +mfio45 i2s_dac_clk, audio_sync +mfio46 audio_trigger +mfio47 i2s_in +mfio48 i2s_in +mfio49 i2s_in +mfio50 i2s_in +mfio51 i2s_in +mfio52 i2s_in +mfio53 i2s_in +mfio54 i2s_in, spdif_in +mfio55 uart0, spim0, spim1 +mfio56 uart0, spim0, spim1 +mfio57 uart0, spim0, spim1 +mfio58 uart0, spim1 +mfio59 uart1 +mfio60 uart1 +mfio61 spdif_out +mfio62 spdif_in +mfio63 eth, mips_trace_clk, mips_trace_data +mfio64 eth, mips_trace_dint, mips_trace_data +mfio65 eth, mips_trace_trigout, mips_trace_data +mfio66 eth, mips_trace_trigin, mips_trace_data +mfio67 eth, mips_trace_dm, mips_trace_data +mfio68 eth, mips_trace_probe_n, mips_trace_data +mfio69 eth, mips_trace_data +mfio70 eth, mips_trace_data +mfio71 eth +mfio72 ir +mfio73 pwmpdm, mips_trace_clk, sram_debug +mfio74 pwmpdm, mips_trace_dint, sram_debug +mfio75 pwmpdm, mips_trace_trigout, rom_debug +mfio76 pwmpdm, mips_trace_trigin, rom_debug +mfio77 mdc_debug, mips_trace_dm, rpu_debug +mfio78 mdc_debug, mips_trace_probe_n, rpu_debug +mfio79 ddr_debug, mips_trace_data, mips_debug +mfio80 ddr_debug, mips_trace_data, mips_debug +mfio81 dreq0, mips_trace_data, eth_debug +mfio82 dreq1, mips_trace_data, eth_debug +mfio83 mips_pll_lock, mips_trace_data, usb_debug +mfio84 sys_pll_lock, mips_trace_data, usb_debug +mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug +mfio86 bt_pll_lock, mips_trace_data, sdhost_debug +mfio87 rpu_v_pll_lock, dreq2, socif_debug +mfio88 rpu_l_pll_lock, dreq3, socif_debug +mfio89 audio_pll_lock, dreq4, dreq5 +tck +trstn +tdi +tms +tdo +jtag_comply +safe_mode +por_disable +resetn + +Example: +-------- +pinctrl@18101C00 { + compatible = "img,pistachio-system-pinctrl"; + reg = <0x18101C00 0x400>; + + gpio0: gpio0 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + gpio5: gpio5 { + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + uart0_xfer: uart0-xfer { + uart0-rxd { + pins = "mfio55"; + function = "uart0"; + }; + uart0-txd { + pins = "mfio56"; + function = "uart0"; + }; + }; + + uart0_rts_cts: uart0-rts-cts { + uart0-rts { + pins = "mfio57"; + function = "uart0"; + }; + uart0-cts { + pins = "mfio58"; + function = "uart0"; + }; + }; +}; + +uart@... { + ... + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; + ... +}; + +usb_vbus: fixed-regulator { + ... + gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + ... +}; diff --git a/dts/Bindings/pinctrl/lantiq,falcon-pinumx.txt b/dts/Bindings/pinctrl/lantiq,falcon-pinumx.txt deleted file mode 100644 index ac4da9fe07..0000000000 --- a/dts/Bindings/pinctrl/lantiq,falcon-pinumx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Lantiq FALCON pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-falcon" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, - jtag, slic, pcm, asc1 - - functions: - rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down -- lantiq,drive-current: Boolean, enables drive-current -- lantiq,slew-rate: Boolean, enables slew-rate - -Example: - pinmux0 { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - i2c { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - }; diff --git a/dts/Bindings/pinctrl/lantiq,pinctrl-falcon.txt b/dts/Bindings/pinctrl/lantiq,pinctrl-falcon.txt new file mode 100644 index 0000000000..ac4da9fe07 --- /dev/null +++ b/dts/Bindings/pinctrl/lantiq,pinctrl-falcon.txt @@ -0,0 +1,83 @@ +Lantiq FALCON pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-falcon" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, + jtag, slic, pcm, asc1 + + functions: + rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down +- lantiq,drive-current: Boolean, enables drive-current +- lantiq,slew-rate: Boolean, enables slew-rate + +Example: + pinmux0 { + compatible = "lantiq,pinctrl-falcon"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + asc0 { + lantiq,groups = "asc0"; + lantiq,function = "asc"; + }; + ntr { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + }; + i2c { + lantiq,groups = "i2c"; + lantiq,function = "i2c"; + }; + hrst { + lantiq,groups = "hrst"; + lantiq,function = "rst"; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/lantiq,pinctrl-xway.txt b/dts/Bindings/pinctrl/lantiq,pinctrl-xway.txt new file mode 100644 index 0000000000..e89b467756 --- /dev/null +++ b/dts/Bindings/pinctrl/lantiq,pinctrl-xway.txt @@ -0,0 +1,97 @@ +Lantiq XWAY pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, + ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, + spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, + gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, + req3 + + additional mux groups (XR9 only): + mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio + + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- lantiq,open-drain: Boolean, enables open-drain on the defined pin. + +Valid values for XWAY pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for XR9 pin names: + Pinconf pins can be referenced via the names io0-io55. + +Example: + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + diff --git a/dts/Bindings/pinctrl/lantiq,xway-pinumx.txt b/dts/Bindings/pinctrl/lantiq,xway-pinumx.txt deleted file mode 100644 index e89b467756..0000000000 --- a/dts/Bindings/pinctrl/lantiq,xway-pinumx.txt +++ /dev/null @@ -1,97 +0,0 @@ -Lantiq XWAY pinmux controller - -Required properties: -- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" -- reg: Should contain the physical address and length of the gpio/pinmux - register range - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Lantiq's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and two pin configuration parameters: -pull-up and open-drain - -The name of each subnode is not important as long as it is unique; all subnodes -should be enumerated and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -We support 2 types of nodes. - -Definition of mux function groups: - -Required subnode-properties: -- lantiq,groups : An array of strings. Each string contains the name of a group. - Valid values for these names are listed below. -- lantiq,function: A string containing the name of the function to mux to the - group. Valid values for function names are listed below. - -Valid values for group and function names: - - mux groups: - exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, - ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, - spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, - gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, - req3 - - additional mux groups (XR9 only): - mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 - - functions: - spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio - - - -Definition of pin configurations: - -Required subnode-properties: -- lantiq,pins : An array of strings. Each string contains the name of a pin. - Valid values for these names are listed below. - -Optional subnode-properties: -- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- lantiq,open-drain: Boolean, enables open-drain on the defined pin. - -Valid values for XWAY pin names: - Pinconf pins can be referenced via the names io0-io31. - -Valid values for XR9 pin names: - Pinconf pins can be referenced via the names io0-io55. - -Example: - gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - diff --git a/dts/Bindings/pinctrl/marvell,armada-370-pinctrl.txt b/dts/Bindings/pinctrl/marvell,armada-370-pinctrl.txt index adda2a8d1d..add7c38ec7 100644 --- a/dts/Bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ b/dts/Bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -17,10 +17,10 @@ mpp0 0 gpio, uart0(rxd) mpp1 1 gpo, uart0(txd) mpp2 2 gpio, i2c0(sck), uart0(txd) mpp3 3 gpio, i2c0(sda), uart0(rxd) -mpp4 4 gpio, cpu_pd(vdd) -mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) +mpp4 4 gpio, vdd(cpu-pd) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) -mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk) +mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) @@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) mpp31 31 gpio, tclk, ge0(txerr) mpp32 32 gpio, spi0(cs0) mpp33 33 gpio, dev(bootcs), spi0(cs0) -mpp34 34 gpo, dev(wen0), spi0(mosi) -mpp35 35 gpo, dev(oen), spi0(sck) +mpp34 34 gpo, dev(we0), spi0(mosi) +mpp35 35 gpo, dev(oe), spi0(sck) mpp36 36 gpo, dev(a1), spi0(miso) mpp37 37 gpo, dev(a0), sata0(prsnt) mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) @@ -86,11 +86,11 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), uart0(rts) mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) -mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), +mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), audio(sdi) -mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) +mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), audio(mclk), uart0(cts) mpp63 63 gpo, spi0(sck), tclk -mpp64 64 gpio, spi0(miso), spi0-1(cs1) -mpp65 65 gpio, spi0(mosi), spi0-1(cs2) +mpp64 64 gpio, spi0(miso), spi0(cs1) +mpp65 65 gpio, spi0(mosi), spi0(cs2) diff --git a/dts/Bindings/pinctrl/marvell,armada-375-pinctrl.txt b/dts/Bindings/pinctrl/marvell,armada-375-pinctrl.txt index 7de0cda4a3..06e5bb0367 100644 --- a/dts/Bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/dts/Bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -15,24 +15,24 @@ name pins functions ================================================================================ mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) -mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) -mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) +mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) +mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) -mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) +mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) -mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) +mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) mpp14 14 gpio, i2c0(sda), uart1(txd) mpp15 15 gpio, i2c0(sck), uart1(rxd) mpp16 16 gpio, uart0(txd) mpp17 17 gpio, uart0(rxd) -mpp18 18 gpio, tdm(intn) -mpp19 19 gpio, tdm(rstn) +mpp18 18 gpio, tdm(int) +mpp19 19 gpio, tdm(rst) mpp20 20 gpio, tdm(pclk) mpp21 21 gpio, tdm(fsync) mpp22 22 gpio, tdm(drx) @@ -45,12 +45,12 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) mpp30 30 gpio, ge1(txd0), spi1(cs0) mpp31 31 gpio, ge1(txd1), spi1(mosi) -mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) +mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) mpp33 33 gpio, ge1(txd3), spi1(miso) mpp34 34 gpio, ge1(txclkout), spi1(sck) mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) mpp36 36 gpio, pcie0(clkreq) -mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) +mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) mpp38 38 gpio, pcie1(clkreq), ge(mdio) mpp39 39 gpio, ref(clkout) mpp40 40 gpio, uart1(txd) @@ -58,25 +58,25 @@ mpp41 41 gpio, uart1(rxd) mpp42 42 gpio, spi1(cs2), led(c0) mpp43 43 gpio, sata0(prsnt), dram(vttctrl) mpp44 44 gpio, sata0(prsnt) -mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) -mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) +mpp45 45 gpio, spi0(cs2), pcie0(rstout) +mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) -mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) -mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) +mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) +mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) mpp55 55 gpio, ge0(rxclk), ge1(rxclk) mpp56 56 gpio, ge0(txclkout), ge1(txclkout) -mpp57 57 gpio, ge0(txctl), ge1(txctl) +mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) mpp58 58 gpio, led(c0) mpp59 59 gpio, led(c1) mpp60 60 gpio, uart1(txd), led(c2) mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) mpp62 62 gpio, i2c1(sck), led(p1) -mpp63 63 gpio, ptp(triggen), led(p2) +mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) mpp64 64 gpio, dram(vttctrl), led(p3) mpp65 65 gpio, sata1(prsnt) -mpp66 66 gpio, ptp(eventreq), spi1(cs3) +mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/dts/Bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/dts/Bindings/pinctrl/marvell,armada-38x-pinctrl.txt index b17c96849f..54ec4c0a0d 100644 --- a/dts/Bindings/pinctrl/marvell,armada-38x-pinctrl.txt +++ b/dts/Bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -27,16 +27,16 @@ mpp8 8 gpio, ge0(txd1), dev(ad10) mpp9 9 gpio, ge0(txd2), dev(ad11) mpp10 10 gpio, ge0(txd3), dev(ad12) mpp11 11 gpio, ge0(txctl), dev(ad13) -mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14) -mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15) -mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1) -mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1] -mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq) -mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) -mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1] -mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts) -mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts) -mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) +mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) +mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) +mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] +mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) +mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) +mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) +mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) @@ -45,36 +45,36 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) mpp29 29 gpio, ge1(txd1), dev(ale0) -mpp30 30 gpio, ge1(txd2), dev(oen) +mpp30 30 gpio, ge1(txd2), dev(oe) mpp31 31 gpio, ge1(txd3), dev(ale1) -mpp32 32 gpio, ge1(txctl), dev(wen0) -mpp33 33 gpio, m(decc_err), dev(ad3) +mpp32 32 gpio, ge1(txctl), dev(we0) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk_out1), dev(a1) -mpp36 36 gpio, ptp(trig_gen), dev(a0) +mpp36 36 gpio, ptp(trig), dev(a0) mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) -mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) +mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) -mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) +mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout) -mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout) -mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) -mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2] -mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4) -mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5) -mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd) -mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) -mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6) -mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) -mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3) -mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) -mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) -mpp57 57 gpio, spi1(sck), sd0(clk) -mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) +mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] +mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) +mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) +mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) +mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) [1]: only available on 88F6820 and 88F6828 [2]: only available on 88F6828 diff --git a/dts/Bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/dts/Bindings/pinctrl/marvell,armada-39x-pinctrl.txt index 5b1a9dc004..a40b60f1ca 100644 --- a/dts/Bindings/pinctrl/marvell,armada-39x-pinctrl.txt +++ b/dts/Bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl" - depending on the specific variant of the SoC being used. +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or + "marvell,88f6928-pinctrl" depending on the specific variant of the + SoC being used. - reg: register specifier of MPP registers Available mpp pins/groups and functions: @@ -24,55 +25,60 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio) mpp7 7 gpio, dev(ad9), xsmi(mdc) mpp8 8 gpio, dev(ad10), ptp(trig) mpp9 9 gpio, dev(ad11), ptp(clk) -mpp10 10 gpio, dev(ad12), ptp(event) +mpp10 10 gpio, dev(ad12), ptp(evreq) mpp11 11 gpio, dev(ad13), led(clk) mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) -mpp13 13 gpio, dev(ad15), led(data) -mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd) +mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) +mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) -mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda) -mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio) +mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) +mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) -mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda) -mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc) -mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0) +mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), + sata1(prsnt) [1], ge(rxd0) mpp22 22 gpio, spi0(mosi), dev(ad0) mpp23 23 gpio, spi0(sck), dev(ad2) -mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn) -mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0) -mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1) -mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout) -mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) mpp29 29 gpio, dev(ale0), ge(txd1) -mpp30 30 gpio, dev(oen), ge(txd2) +mpp30 30 gpio, dev(oe), ge(txd2) mpp31 31 gpio, dev(ale1), ge(txd3) -mpp32 32 gpio, dev(wen0), ge(txctl) -mpp33 33 gpio, m(decc), dev(ad3) +mpp32 32 gpio, dev(we0), ge(txctl) +mpp33 33 gpio, dram(deccerr), dev(ad3) mpp34 34 gpio, dev(ad1) mpp35 35 gpio, ref(clk), dev(a1) mpp36 36 gpio, dev(a0) -mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk) -mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1) -mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2) -mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3) -mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl) +mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) -mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1) -mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(clk) mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) -mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data) -mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd) -mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd) -mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd) -mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd) -mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck) -mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda) -mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd) -mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd) -mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd) -mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd) -mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd) -mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], + audio(lrclk) [2], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) +mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) -[1]: only available on 88F6928 +[1]: only available on 88F6925/88F6928 +[2]: only available on 88F6928 diff --git a/dts/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/dts/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt index 373dbccd7a..76da7222ff 100644 --- a/dts/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ b/dts/Bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -18,7 +18,7 @@ only for more detailed description in this document. name pins functions ================================================================================ -mpp0 0 gpio, ge0(txclko), lcd(d0) +mpp0 0 gpio, ge0(txclkout), lcd(d0) mpp1 1 gpio, ge0(txd0), lcd(d1) mpp2 2 gpio, ge0(txd1), lcd(d2) mpp3 3 gpio, ge0(txd2), lcd(d3) @@ -30,49 +30,50 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8) mpp9 9 gpio, ge0(rxd3), lcd(d9) mpp10 10 gpio, ge0(rxctl), lcd(d10) mpp11 11 gpio, ge0(rxclk), lcd(d11) -mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) -mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) -mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) -mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) -mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) -mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) +mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) +mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) +mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) +mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) +mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) -mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) +mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) -mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) -mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) -mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) +mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) +mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) +mpp26 26 gpio, lcd(clk), tdm(fsync) mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) -mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) +mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) mpp30 30 gpio, tdm(int1), sd0(clk) -mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) -mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) -mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) -mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) +mpp31 31 gpio, tdm(int2), sd0(cmd) +mpp32 32 gpio, tdm(int3), sd0(d0) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) -mpp36 36 gpio, spi(mosi) -mpp37 37 gpio, spi(miso) -mpp38 38 gpio, spi(sck) -mpp39 39 gpio, spi(cs0) -mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), - pcie(clkreq0) -mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), - pcie(clkreq1) -mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), - vdd(cpu0-pd) -mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), - vdd(cpu2-3-pd){1} -mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), - mem(bat) -mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) -mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) -mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), - ref(clkout) -mpp48 48 gpio, tclk, dev(burst/last) +mpp36 36 gpio, spi0(mosi) +mpp37 37 gpio, spi0(miso) +mpp38 38 gpio, spi0(sck) +mpp39 39 gpio, spi0(cs0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), + spi1(cs1) +mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), + pcie(clkreq1), spi1(cs2) +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), + spi1(cs3) +mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), + dram(bat), spi1(cs4) +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), + spi1(cs5), dram(vttctrl) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), + spi1(cs6) +mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), + ref(clkout), spi1(cs7) +mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) * Marvell Armada XP (mv78260 and mv78460 only) @@ -84,9 +85,9 @@ mpp51 51 gpio, dev(ad16) mpp52 52 gpio, dev(ad17) mpp53 53 gpio, dev(ad18) mpp54 54 gpio, dev(ad19) -mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) -mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) -mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} +mpp55 55 gpio, dev(ad20) +mpp56 56 gpio, dev(ad21) +mpp57 57 gpio, dev(ad22) mpp58 58 gpio, dev(ad23) mpp59 59 gpio, dev(ad24) mpp60 60 gpio, dev(ad25) @@ -96,6 +97,3 @@ mpp63 63 gpio, dev(ad28) mpp64 64 gpio, dev(ad29) mpp65 65 gpio, dev(ad30) mpp66 66 gpio, dev(ad31) - -Notes: -* {1} vdd(cpu2-3-pd) only available on mv78460. diff --git a/dts/Bindings/pinctrl/nxp,lpc1850-scu.txt b/dts/Bindings/pinctrl/nxp,lpc1850-scu.txt new file mode 100644 index 0000000000..df0309c575 --- /dev/null +++ b/dts/Bindings/pinctrl/nxp,lpc1850-scu.txt @@ -0,0 +1,57 @@ +NXP LPC18xx/43xx SCU pin controller Device Tree Bindings +-------------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-scu" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) + +The lpc1850-scu driver uses the generic pin multiplexing and generic pin +configuration documented in pinctrl-bindings.txt. + +The following generic nodes are supported: + - function + - pins + - bias-disable + - bias-pull-up + - bias-pull-down + - drive-strength + - input-enable + - input-disable + - input-schmitt-enable + - input-schmitt-disable + - slew-rate + +Not all pins support all properties so either refer to the NXP 1850/4350 +user manual or the pin table in the pinctrl-lpc18xx driver for supported +pin properties. + +Example: +pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-disable; + }; + }; +}; diff --git a/dts/Bindings/pinctrl/pinctrl-atlas7.txt b/dts/Bindings/pinctrl/pinctrl-atlas7.txt new file mode 100644 index 0000000000..eecf028ff4 --- /dev/null +++ b/dts/Bindings/pinctrl/pinctrl-atlas7.txt @@ -0,0 +1,109 @@ +CSR SiRFatlas7 pinmux controller + +Required properties: +- compatible : "sirf,atlas7-ioc" +- reg : Address range of the pinctrl registers + +For example, pinctrl might have properties like the following: + pinctrl: ioc@18880000 { + compatible = "sirf,atlas7-ioc"; + reg = <0x18880000 0x1000>; + + a_ac97_pmx: ac97@0 { + ac97 { + groups = "audio_ac97_grp"; + function = "audio_ac97"; + }; + }; + + ... + + sd2_pmx: sd2@0 { + sd2 { + groups = "sd2_grp0"; + function = "sd2"; + }; + }; + + ... + + + sample0_cfg: sample0@0 { + sample0 { + pins = "ldd_0", "ldd_1"; + bias-pull-up; + }; + }; + + sample1_cfg: sample1@0 { + sample1 { + pins = "ldd_2", "ldd_3"; + input-schmitt-enable; + }; + }; + + sample2_cfg: sample2@0 { + sample2 { + groups = "uart4_nopause_grp"; + bias-pull-down; + }; + }; + + sample3_cfg: sample3@0 { + sample3 { + pins = "ldd_4", "ldd_5"; + drive-strength = <2>; + }; + }; + }; + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes. +Each of these subnodes represents some desired configuration for a group of pins. + +Required subnode-properties: +- groups : An array of strings. Each string contains the name of a group. +- function: A string containing the name of the function to mux to the + group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/pinctrl-sirf.c + +For example, pinctrl might have subnodes like the following: + sd0_pmx: sd0@0 { + sd0 { + groups = "sd0_grp"; + function = "sd0"; + }; + }; + + sd1_pmx0: sd1@0 { + sd1 { + groups = "sd1_grp0"; + function = "sd1_m0"; + }; + }; + + sd1_pmx1: sd1@1 { + sd1 { + groups = "sd1_grp1"; + function = "sd1_m1"; + }; + }; + +For a specific board, if it wants to use sd1, +it can add the following to its board-specific .dts file. +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx0>; +} + +or + +sd1: sd@0x12340000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pmx1>; +} diff --git a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt index 5868a0f725..0480bc31bf 100644 --- a/dts/Bindings/pinctrl/pinctrl-mt65xx.txt +++ b/dts/Bindings/pinctrl/pinctrl-mt65xx.txt @@ -3,9 +3,11 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: -- compatible: value should be either of the following. +- compatible: value should be one of the following. (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. -- mediatek,pctl-regmap: Should be a phandle of the syscfg node. + (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. + (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. + (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. - gpio-controller : Marks the device node as a gpio controller. @@ -24,6 +26,9 @@ Required properties: Only the following flags are supported: 0 - GPIO_ACTIVE_HIGH 1 - GPIO_ACTIVE_LOW + +Optional properties: +- mediatek,pctl-regmap: Should be a phandle of the syscfg node. - reg: physicall address base for EINT registers - interrupt-controller: Marks the device node as an interrupt controller - #interrupt-cells: Should be two. diff --git a/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt b/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt new file mode 100644 index 0000000000..77aa117901 --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -0,0 +1,90 @@ +Qualcomm MSM8660 TLMM block + +Required properties: +- compatible: "qcom,msm8660-pinctrl" +- reg: Should be the base address and length of the TLMM block. +- interrupts: Should be the parent IRQ of the TLMM block. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. + The first cell is the gpio pin number and the + second cell is used for optional parameters. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Qualcomm's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, + output-low, output-high. + +Non-empty subnodes must specify the 'pins' property. + +Valid values for pins are: + gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data + +Valid values for function are: + gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b, + gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, + gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, + gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, + gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, + lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, + usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, + +Example: + + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0x4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gsbi12_uart>; + + gsbi12_uart: gsbi12-uart { + mux { + pins = "gpio117", "gpio118"; + function = "gsbi12"; + }; + + tx { + pins = "gpio118"; + drive-strength = <8>; + bias-disable; + }; + + rx { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt index bfe72ec055..51cee44fc1 100644 --- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -16,7 +16,9 @@ Required Properties: - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller. + - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. + - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. + - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.txt b/dts/Bindings/pinctrl/rockchip,pinctrl.txt index 388b213249..391ef4be8d 100644 --- a/dts/Bindings/pinctrl/rockchip,pinctrl.txt +++ b/dts/Bindings/pinctrl/rockchip,pinctrl.txt @@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" + "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl" - rockchip,grf: phandle referencing a syscon providing the "general register files" Optional properties for iomux controller: - rockchip,pmu: phandle referencing a syscon providing the pmu registers as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. Deprecated properties for iomux controller: - reg: first element is the general register space of the iomux controller diff --git a/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.txt b/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.txt index b7b55a964f..f488b0f774 100644 --- a/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.txt +++ b/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.txt @@ -45,8 +45,9 @@ to specify in a pinconf subnode: Valid values for groups are: ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, - qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp, - spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp, + qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, + spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, + spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, @@ -59,7 +60,7 @@ to specify in a pinconf subnode: Valid values for function are: ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, - spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, + spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp, smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 diff --git a/dts/Bindings/power/bq24257.txt b/dts/Bindings/power/bq24257.txt new file mode 100644 index 0000000000..5c9d3940d0 --- /dev/null +++ b/dts/Bindings/power/bq24257.txt @@ -0,0 +1,21 @@ +Binding for TI bq24257 Li-Ion Charger + +Required properties: +- compatible: Should contain one of the following: + * "ti,bq24257" +- reg: integer, i2c address of the device. +- ti,battery-regulation-voltage: integer, maximum charging voltage in uV. +- ti,charge-current: integer, maximum charging current in uA. +- ti,termination-current: integer, charge will be terminated when current in + constant-voltage phase drops below this value (in uA). + +Example: + +bq24257 { + compatible = "ti,bq24257"; + reg = <0x6a>; + + ti,battery-regulation-voltage = <4200000>; + ti,charge-current = <1000000>; + ti,termination-current = <50000>; +}; diff --git a/dts/Bindings/power/bq25890.txt b/dts/Bindings/power/bq25890.txt new file mode 100644 index 0000000000..c9dd17d142 --- /dev/null +++ b/dts/Bindings/power/bq25890.txt @@ -0,0 +1,46 @@ +Binding for TI bq25890 Li-Ion Charger + +Required properties: +- compatible: Should contain one of the following: + * "ti,bq25890" +- reg: integer, i2c address of the device. +- ti,battery-regulation-voltage: integer, maximum charging voltage (in uV); +- ti,charge-current: integer, maximum charging current (in uA); +- ti,termination-current: integer, charge will be terminated when current in + constant-voltage phase drops below this value (in uA); +- ti,precharge-current: integer, maximum charge current during precharge + phase (in uA); +- ti,minimum-sys-voltage: integer, when battery is charging and it is below + minimum system voltage, the system will be regulated above + minimum-sys-voltage setting (in uV); +- ti,boost-voltage: integer, VBUS voltage level in boost mode (in uV); +- ti,boost-max-current: integer, maximum allowed current draw in boost mode + (in uA). + +Optional properties: +- ti,boost-low-freq: boolean, if present boost mode frequency will be 500kHz, + otherwise 1.5MHz; +- ti,use-ilim-pin: boolean, if present the ILIM resistor will be used and the + input current will be the lower between the resistor setting and the IINLIM + register setting; +- ti,thermal-regulation-threshold: integer, temperature above which the charge + current is lowered, to avoid overheating (in degrees Celsius). If omitted, + the default setting will be used (120 degrees); + +Example: + +bq25890 { + compatible = "ti,bq25890"; + reg = <0x6a>; + + ti,battery-regulation-voltage = <4200000>; + ti,charge-current = <1000000>; + ti,termination-current = <50000>; + ti,precharge-current = <128000>; + ti,minimum-sys-voltage = <3600000>; + ti,boost-voltage = <5000000>; + ti,boost-max-current = <1000000>; + + ti,use-ilim-pin; + ti,thermal-regulation-threshold = <120>; +}; diff --git a/dts/Bindings/power/opp.txt b/dts/Bindings/power/opp.txt index 74499e5033..0d5e7c9781 100644 --- a/dts/Bindings/power/opp.txt +++ b/dts/Bindings/power/opp.txt @@ -1,8 +1,19 @@ -* Generic OPP Interface +Generic OPP (Operating Performance Points) Bindings +---------------------------------------------------- -SoCs have a standard set of tuples consisting of frequency and -voltage pairs that the device will support per voltage domain. These -are called Operating Performance Points or OPPs. +Devices work at voltage-current-frequency combinations and some implementations +have the liberty of choosing these. These combinations are called Operating +Performance Points aka OPPs. This document defines bindings for these OPPs +applicable across wide range of devices. For illustration purpose, this document +uses CPU as a device. + +This document contain multiple versions of OPP binding and only one of them +should be used per device. + +Binding 1: operating-points +============================ + +This binding only supports voltage-frequency pairs. Properties: - operating-points: An array of 2-tuples items, and each item consists @@ -23,3 +34,432 @@ cpu@0 { 198000 850000 >; }; + + +Binding 2: operating-points-v2 +============================ + +* Property: operating-points-v2 + +Devices supporting OPPs must set their "operating-points-v2" property with +phandle to a OPP table in their DT node. The OPP core will use this phandle to +find the operating points for the device. + +Devices may want to choose OPP tables at runtime and so can provide a list of +phandles here. But only *one* of them should be chosen at runtime. This must be +accompanied by a corresponding "operating-points-names" property, to uniquely +identify the OPP tables. + +If required, this can be extended for SoC vendor specfic bindings. Such bindings +should be documented as Documentation/devicetree/bindings/power/-opp.txt +and should have a compatible description like: "operating-points-v2-". + +Optional properties: +- operating-points-names: Names of OPP tables (required if multiple OPP + tables are present), to uniquely identify them. The same list must be present + for all the CPUs which are sharing clock/voltage rails and hence the OPP + tables. + +* OPP Table Node + +This describes the OPPs belonging to a device. This node can have following +properties: + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2". + +- OPP nodes: One or more OPP nodes describing voltage-current-frequency + combinations. Their name isn't significant but their phandle can be used to + reference an OPP. + +Optional properties: +- opp-shared: Indicates that device nodes using this OPP Table Node's phandle + switch their DVFS state together, i.e. they share clock/voltage/current lines. + Missing property means devices have independent clock/voltage/current lines, + but they share OPP tables. + +- status: Marks the OPP table enabled/disabled. + + +* OPP Node + +This defines voltage-current-frequency combinations along with other related +properties. + +Required properties: +- opp-hz: Frequency in Hz + +Optional properties: +- opp-microvolt: voltage in micro Volts. + + A single regulator's voltage is specified with an array of size one or three. + Single entry is for target voltage and three entries are for + voltages. + + Entries for multiple regulators must be present in the same order as + regulators are specified in device's DT node. + +- opp-microamp: The maximum current drawn by the device in microamperes + considering system specific parameters (such as transients, process, aging, + maximum operating temperature range etc.) as necessary. This may be used to + set the most efficient regulator operating mode. + + Should only be set if opp-microvolt is set for the OPP. + + Entries for multiple regulators must be present in the same order as + regulators are specified in device's DT node. If this property isn't required + for few regulators, then this should be marked as zero for them. If it isn't + required for any regulator, then this property need not be present. + +- clock-latency-ns: Specifies the maximum possible transition latency (in + nanoseconds) for switching to this OPP from any other OPP. + +- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is + available on some platforms, where the device can run over its operating + frequency for a short duration of time limited by the device's power, current + and thermal limits. + +- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in + the table should have this. + +- status: Marks the node enabled/disabled. + +Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states +independently. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@1 { + compatible = "qcom,krait"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@2 { + compatible = "qcom,krait"; + reg = <2>; + next-level-cache = <&L2>; + clocks = <&clk_controller 2>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply2>; + operating-points-v2 = <&cpu_opp_table>; + }; + + cpu@3 { + compatible = "qcom,krait"; + reg = <3>; + next-level-cache = <&L2>; + clocks = <&clk_controller 3>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + /* + * Missing opp-shared property means CPUs switch DVFS states + * independently. + */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + opp-microamp = <90000; + lock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch +DVFS state together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@100 { + compatible = "arm,cortex-a15"; + reg = <100>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + + cpu@101 { + compatible = "arm,cortex-a15"; + reg = <101>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp01 { + opp-hz = <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + }; + opp02 { + opp-hz = <1200000000>; + opp-microvolt = <1025000>; + opp-microamp = <90000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp10 { + opp-hz = <1300000000>; + opp-microvolt = <1045000 1050000 1055000>; + opp-microamp = <95000>; + clock-latency-ns = <400000>; + opp-suspend; + }; + opp11 { + opp-hz = <1400000000>; + opp-microvolt = <1075000>; + opp-microamp = <100000>; + clock-latency-ns = <400000>; + }; + opp12 { + opp-hz = <1500000000>; + opp-microvolt = <1010000 1100000 1110000>; + opp-microamp = <95000>; + clock-latency-ns = <400000>; + turbo-mode; + }; + }; +}; + +Example 4: Handling multiple regulators + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + cpu-supply = <&cpu_supply0>, <&cpu_supply1>, <&cpu_supply2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000>, /* Supply 0 */ + <960000>, /* Supply 1 */ + <960000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + + /* OR */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>, /* Supply 0 */ + <960000 965000 975000>, /* Supply 1 */ + <960000 965000 975000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + + /* OR */ + + opp00 { + opp-hz = <1000000000>; + opp-microvolt = <970000 975000 985000>, /* Supply 0 */ + <960000 965000 975000>, /* Supply 1 */ + <960000 965000 975000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <0>, /* Supply 1 doesn't need this */ + <70000>; /* Supply 2 */ + clock-latency-ns = <300000>; + }; + }; +}; + +Example 5: Multiple OPP tables + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + cpu-supply = <&cpu_supply> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; + operating-points-names = "slow", "fast"; + }; + }; + + cpu0_opp_table_slow: opp_table_slow { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp00 { + opp-hz = <600000000>; + ... + }; + + opp01 { + opp-hz = <800000000>; + ... + }; + }; + + cpu0_opp_table_fast: opp_table_fast { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp10 { + opp-hz = <1000000000>; + ... + }; + + opp11 { + opp-hz = <1100000000>; + ... + }; + }; +}; diff --git a/dts/Bindings/power/rt9455_charger.txt b/dts/Bindings/power/rt9455_charger.txt new file mode 100644 index 0000000000..5d9ad5cf2c --- /dev/null +++ b/dts/Bindings/power/rt9455_charger.txt @@ -0,0 +1,48 @@ +Binding for Richtek rt9455 battery charger + +Required properties: +- compatible: it should contain one of the following: + "richtek,rt9455". +- reg: integer, i2c address of the device. +- interrupt-parent: the phandle for the interrupt controller that + services interrupts for this device. +- interrupts: interrupt mapping for GPIO IRQ, it should be + configured with IRQ_TYPE_LEVEL_LOW flag. +- richtek,output-charge-current: integer, output current from the charger to the + battery, in uA. +- richtek,end-of-charge-percentage: integer, percent of the output charge current. + When the current in constant-voltage phase drops + below output_charge_current x end-of-charge-percentage, + charge is terminated. +- richtek,battery-regulation-voltage: integer, maximum battery voltage in uV. +- richtek,boost-output-voltage: integer, maximum voltage provided to consumer + devices, when the charger is in boost mode, in uV. + +Optional properties: +- richtek,min-input-voltage-regulation: integer, input voltage level in uV, used to + decrease voltage level when the over current + of the input power source occurs. + This prevents input voltage drop due to insufficient + current provided by the power source. + Default: 4500000 uV (4.5V) +- richtek,avg-input-current-regulation: integer, input current value in uA drained by the + charger from the power source. + Default: 500000 uA (500mA) + +Example: + +rt9455@22 { + compatible = "richtek,rt9455"; + reg = <0x22>; + + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + richtek,output-charge-current = <500000>; + richtek,end-of-charge-percentage = <10>; + richtek,battery-regulation-voltage = <4200000>; + richtek,boost-output-voltage = <5050000>; + + richtek,min-input-voltage-regulation = <4500000>; + richtek,avg-input-current-regulation = <500000>; +}; diff --git a/dts/Bindings/power/twl-charger.txt b/dts/Bindings/power/twl-charger.txt index d5c706216d..3b4ea1b73b 100644 --- a/dts/Bindings/power/twl-charger.txt +++ b/dts/Bindings/power/twl-charger.txt @@ -1,5 +1,15 @@ TWL BCI (Battery Charger Interface) +The battery charger needs to interact with the USB phy in order +to know when charging is permissible, and when there is a connection +or disconnection. + +The choice of phy cannot be configured at a hardware level, so there +is no value in explicit configuration in device-tree. Rather +if there is a sibling of the BCI node which is compatible with +"ti,twl4030-usb", then that is used to determine when and how +use USB power for charging. + Required properties: - compatible: - "ti,twl4030-bci" diff --git a/dts/Bindings/power_supply/max17042_battery.txt b/dts/Bindings/power_supply/max17042_battery.txt index 5bc9b685cf..3f3894aaee 100644 --- a/dts/Bindings/power_supply/max17042_battery.txt +++ b/dts/Bindings/power_supply/max17042_battery.txt @@ -9,10 +9,23 @@ Optional properties : (datasheet-recommended value is 10000). Defining this property enables current-sense functionality. +Optional threshold properties : + If skipped the condition won't be reported. + - maxim,cold-temp : Temperature threshold to report battery + as cold (in tenths of degree Celsius). + - maxim,over-heat-temp : Temperature threshold to report battery + as over heated (in tenths of degree Celsius). + - maxim,dead-volt : Voltage threshold to report battery + as dead (in mV). + - maxim,over-volt : Voltage threshold to report battery + as over voltage (in mV). + Example: battery-charger@36 { compatible = "maxim,max17042"; reg = <0x36>; maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4300>; }; diff --git a/dts/Bindings/powerpc/fsl/fman.txt b/dts/Bindings/powerpc/fsl/fman.txt index edda55f740..1fc5328c06 100644 --- a/dts/Bindings/powerpc/fsl/fman.txt +++ b/dts/Bindings/powerpc/fsl/fman.txt @@ -189,6 +189,19 @@ PROPERTIES Definition: There is one reg region describing the port configuration registers. +- fsl,fman-10g-port + Usage: optional + Value type: boolean + Definition: The default port rate is 1G. + If this property exists, the port is s 10G port. + +- fsl,fman-best-effort-port + Usage: optional + Value type: boolean + Definition: Can be defined only if 10G-support is set. + This property marks a best-effort 10G port (10G port that + may not be capable of line rate). + EXAMPLE port@a8000 { diff --git a/dts/Bindings/powerpc/fsl/guts.txt b/dts/Bindings/powerpc/fsl/guts.txt index 7f150b5012..b71b2039e1 100644 --- a/dts/Bindings/powerpc/fsl/guts.txt +++ b/dts/Bindings/powerpc/fsl/guts.txt @@ -9,6 +9,11 @@ Required properties: - compatible : Should define the compatible device type for global-utilities. + Possible compatibles: + "fsl,qoriq-device-config-1.0" + "fsl,qoriq-device-config-2.0" + "fsl,-device-config" + "fsl,-guts" - reg : Offset and length of the register set for the device. Recommended properties: diff --git a/dts/Bindings/regulator/max8973-regulator.txt b/dts/Bindings/regulator/max8973-regulator.txt index 4f15d8a1bf..55efb24e56 100644 --- a/dts/Bindings/regulator/max8973-regulator.txt +++ b/dts/Bindings/regulator/max8973-regulator.txt @@ -2,12 +2,30 @@ Required properties: -- compatible: must be "maxim,max8973" +- compatible: must be one of following: + "maxim,max8973" + "maxim,max77621". - reg: the i2c slave address of the regulator. It should be 0x1b. Any standard regulator properties can be used to configure the single max8973 DCDC. +Optional properties: + +-maxim,externally-enable: boolean, externally control the regulator output + enable/disable. +-maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided + then externally enable control will be considered. +-maxim,dvs-gpio: GPIO which is connected to DVS pin of device. +-maxim,dvs-default-state: Default state of GPIO during initialisation. + 1 for HIGH and 0 for LOW. +-maxim,enable-remote-sense: boolean, enable reote sense. +-maxim,enable-falling-slew-rate: boolean, enable falling slew rate. +-maxim,enable-active-discharge: boolean: enable active discharge. +-maxim,enable-frequency-shift: boolean, enable 9% frequency shift. +-maxim,enable-bias-control: boolean, enable bias control. By enabling this + startup delay can be reduce to 20us from 220us. + Example: max8973@1b { diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.txt b/dts/Bindings/regulator/qcom,spmi-regulator.txt new file mode 100644 index 0000000000..75b4604bad --- /dev/null +++ b/dts/Bindings/regulator/qcom,spmi-regulator.txt @@ -0,0 +1,121 @@ +Qualcomm SPMI Regulators + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,pm8841-regulators" + "qcom,pm8916-regulators" + "qcom,pm8941-regulators" + +- interrupts: + Usage: optional + Value type: + Definition: List of OCP interrupts. + +- interrupt-names: + Usage: required if 'interrupts' property present + Value type: + Definition: List of strings defining the names of the + interrupts in the 'interrupts' property 1-to-1. + Supported values are "ocp-", where + corresponds to a voltage switch + type regulator. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_s8-supply: + Usage: optional (pm8841 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_l1_l3-supply: +- vdd_l2-supply: +- vdd_l4_l5_l6-supply: +- vdd_l7-supply: +- vdd_l8_l11_l14_l15_l16-supply: +- vdd_l9_l10_l12_l13_l17_l18-supply: + Usage: optional (pm8916 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_l1_l3-supply: +- vdd_l2_lvs_1_2_3-supply: +- vdd_l4_l11-supply: +- vdd_l5_l7-supply: +- vdd_l6_l12_l14_l15-supply: +- vdd_l8_l16_l18_19-supply: +- vdd_l9_l10_l17_l22-supply: +- vdd_l13_l20_l23_l24-supply: +- vdd_l21-supply: +- vin_5vs-supply: + Usage: optional (pm8941 only) + Value type: + Definition: Reference to regulator supplying the input pin, as + described in the data sheet. + + +The regulator node houses sub-nodes for each regulator within the device. Each +sub-node is identified using the node's name, with valid values listed for each +of the PMICs below. + +pm8841: + s1, s2, s3, s4, s5, s6, s7, s8 + +pm8916: + s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, + l14, l15, l16, l17, l18 + +pm8941: + s1, s2, s3, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, + l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3, + mvs1, mvs2 + +The content of each sub-node is defined by the standard binding for regulators - +see regulator.txt - with additional custom properties described below: + +- regulator-initial-mode: + Usage: optional + Value type: + Descrption: 1 = Set initial mode to high power mode (HPM), also referred + to as NPM. HPM consumes more ground current than LPM, but + it can source significantly higher load current. HPM is not + available on boost type regulators. For voltage switch type + regulators, HPM implies that over current protection and + soft start are active all the time. 0 = Set initial mode to + low power mode (LPM). + +Example: + + regulators { + compatible = "qcom,pm8941-regulators"; + vdd_l1_l3-supply = <&s1>; + + s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + }; + + ... + + l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + .... + }; diff --git a/dts/Bindings/regulator/regulator.txt b/dts/Bindings/regulator/regulator.txt index abb26b58c8..db88feb28c 100644 --- a/dts/Bindings/regulator/regulator.txt +++ b/dts/Bindings/regulator/regulator.txt @@ -7,18 +7,20 @@ Optional properties: - regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops - regulator-min-microamp: smallest current consumers may set - regulator-max-microamp: largest current consumers may set +- regulator-input-current-limit-microamp: maximum input current regulator allows - regulator-always-on: boolean, regulator should never be disabled - regulator-boot-on: bootloader/firmware enabled regulator - regulator-allow-bypass: allow the regulator to go into bypass mode - -supply: phandle to the parent supply/regulator node - regulator-ramp-delay: ramp delay for regulator(in uV/uS) For hardware which supports disabling ramp rate, it should be explicitly - intialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay. + initialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay. - regulator-enable-ramp-delay: The time taken, in microseconds, for the supply rail to reach the target voltage, plus/minus whatever tolerance the board design requires. This property describes the total system ramp time required due to the combination of internal ramping of the regulator itself, and board design issues such as trace capacitance and load on the supply. +- regulator-soft-start: Enable soft start so that voltage ramps slowly - regulator-state-mem sub-root node for Suspend-to-RAM mode : suspend to memory, the device goes to sleep, but all data stored in memory, only some external interrupt can wake the device. @@ -37,6 +39,9 @@ Optional properties: - regulator-initial-mode: initial operating mode. The set of possible operating modes depends on the capabilities of every hardware so each device binding documentation explains which values the regulator supports. +- regulator-system-load: Load in uA present on regulator that is not captured by + any consumer request. +- regulator-pull-down: Enable pull down resistor when the regulator is disabled. Deprecated properties: - regulator-compatible: If a regulator chip contains multiple diff --git a/dts/Bindings/remoteproc/wkup_m3_rproc.txt b/dts/Bindings/remoteproc/wkup_m3_rproc.txt new file mode 100644 index 0000000000..3a70073797 --- /dev/null +++ b/dts/Bindings/remoteproc/wkup_m3_rproc.txt @@ -0,0 +1,52 @@ +TI Wakeup M3 Remoteproc Driver +============================== + +The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor +(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks +that cannot be controlled from the MPU. This CM3 processor requires a firmware +binary to accomplish this. The wkup_m3 remoteproc driver handles the loading of +the firmware and booting of the CM3. + +Wkup M3 Device Node: +==================== +A wkup_m3 device node is used to represent the Wakeup M3 processor instance +within the SoC. It is added as a child node of the parent interconnect bus +(l4_wkup) through which it is accessible to the MPU. + +Required properties: +-------------------- +- compatible: Should be one of, + "ti,am3352-wkup-m3" for AM33xx SoCs + "ti,am4372-wkup-m3" for AM43xx SoCs +- reg: Should contain the address ranges for the two internal + memory regions, UMEM and DMEM. The parent node should + provide an appropriate ranges property for properly + translating these into bus addresses. +- reg-names: Contains the corresponding names for the two memory + regions. These should be named "umem" & "dmem". +- ti,hwmods: Name of the hwmod associated with the wkupm3 device. +- ti,pm-firmware: Name of firmware file to be used for loading and + booting the wkup_m3 remote processor. + +Example: +-------- +/* AM33xx */ +ocp { + l4_wkup: l4_wkup@44c00000 { + compatible = "am335-l4-wkup", "simple-bus"; + ranges = <0 0x44c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + + wkup_m3: wkup_m3@100000 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x100000 0x4000>, + <0x180000 0x2000>; + reg-names = "umem", "dmem"; + ti,hwmods = "wkup_m3"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + }; + + ... +}; diff --git a/dts/Bindings/reset/berlin,reset.txt b/dts/Bindings/reset/berlin,reset.txt new file mode 100644 index 0000000000..514fee098b --- /dev/null +++ b/dts/Bindings/reset/berlin,reset.txt @@ -0,0 +1,23 @@ +Marvell Berlin reset controller +=============================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller node must be a sub-node of the chip controller +node on Berlin SoCs. + +Required properties: +- compatible: should be "marvell,berlin2-reset" +- #reset-cells: must be set to 2 + +Example: + +chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; +}; + +&usb_phy0 { + resets = <&chip_rst 0x104 12>; +}; diff --git a/dts/Bindings/reset/brcm,bcm63138-pmb.txt b/dts/Bindings/reset/brcm,bcm63138-pmb.txt new file mode 100644 index 0000000000..a98872d278 --- /dev/null +++ b/dts/Bindings/reset/brcm,bcm63138-pmb.txt @@ -0,0 +1,19 @@ +Broadcom BCM63138 Processor Monitor Bus binding +=============================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Require properties: + +- compatible: must be "brcm,bcm63138-pmb" +- reg: base register address and size for this bus controller +- #reset-cells: must be 2 first cell is the address within the bus instance designated + by the phandle, and the second is the number of zones for this peripheral + +Example: + pmb0: reset-controller@4800c0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800c0 0x10>; + #reset-cells = <2>; + }; diff --git a/dts/Bindings/rtc/haoyu,hym8563.txt b/dts/Bindings/rtc/haoyu,hym8563.txt index 5c199ee044..a8934fe2ab 100644 --- a/dts/Bindings/rtc/haoyu,hym8563.txt +++ b/dts/Bindings/rtc/haoyu,hym8563.txt @@ -6,11 +6,11 @@ as well as a clock output of up to 32kHz. Required properties: - compatible: should be: "haoyu,hym8563" - reg: i2c address -- interrupts: rtc alarm/event interrupt - #clock-cells: the value should be 0 Optional properties: - clock-output-names: From common clock binding +- interrupts: rtc alarm/event interrupt Example: diff --git a/dts/Bindings/rtc/rtc-st-lpc.txt b/dts/Bindings/rtc/rtc-st-lpc.txt new file mode 100644 index 0000000000..73407f502e --- /dev/null +++ b/dts/Bindings/rtc/rtc-st-lpc.txt @@ -0,0 +1,25 @@ +STMicroelectronics Low Power Controller (LPC) - RTC +=================================================== + +LPC currently supports Watchdog OR Real Time Clock functionality. + +[See: ../watchdog/st_lpc_wdt.txt for Watchdog options] + +Required properties + +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc" + "st,stih415-lpc" "st,stid127-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or + ST_LPC_MODE_WDT [1]. One (and only one) mode must be + selected. + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,lpc-mode = ; + }; diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt index ab757b84da..ac2fcd6ff4 100644 --- a/dts/Bindings/rtc/s3c-rtc.txt +++ b/dts/Bindings/rtc/s3c-rtc.txt @@ -6,7 +6,8 @@ Required properties: * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc. * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc. * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. - * "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc. + * "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with + exynos3250 rtc (use "samsung,s3c6410-rtc"). - reg: physical base address of the controller and length of memory mapped region. - interrupts: Two interrupt numbers to the cpu should be specified. First diff --git a/dts/Bindings/serial/arm_sbsa_uart.txt b/dts/Bindings/serial/arm_sbsa_uart.txt new file mode 100644 index 0000000000..4163e7eb77 --- /dev/null +++ b/dts/Bindings/serial/arm_sbsa_uart.txt @@ -0,0 +1,10 @@ +* ARM SBSA defined generic UART +This UART uses a subset of the PL011 registers and consequently lives +in the PL011 driver. It's baudrate and other communication parameters +cannot be adjusted at runtime, so it lacks a clock specifier here. + +Required properties: +- compatible: must be "arm,sbsa-uart" +- reg: exactly one register range +- interrupts: exactly one interrupt specifier +- current-speed: the (fixed) baud rate set by the firmware diff --git a/dts/Bindings/serial/ingenic,uart.txt b/dts/Bindings/serial/ingenic,uart.txt new file mode 100644 index 0000000000..c2d3b3abe7 --- /dev/null +++ b/dts/Bindings/serial/ingenic,uart.txt @@ -0,0 +1,22 @@ +* Ingenic SoC UART + +Required properties: +- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart" +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clocks : phandles to the module & baud clocks. +- clock-names: tuple listing input clock names. + Required elements: "baud", "module" + +Example: + +uart0: serial@10030000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10030000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <9>; + + clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; + clock-names = "baud", "module"; +}; diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt index 44152261e5..8d63f1da07 100644 --- a/dts/Bindings/serial/mtk-uart.txt +++ b/dts/Bindings/serial/mtk-uart.txt @@ -14,7 +14,14 @@ Required properties: - interrupts: A single interrupt specifier. -- clocks: Clock driving the hardware. +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: + - "baud": The clock the baudrate is derived from + - "bus": The bus clock for register accesses (optional) + +For compatibility with older device trees an unnamed clock is used for the +baud clock if the baudclk does not exist. Do not use this for new designs. Example: @@ -22,5 +29,6 @@ Example: compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; reg = <0x11006000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&uart_clk>, <&bus_clk>; + clock-names = "baud", "bus"; }; diff --git a/dts/Bindings/serial/nxp,lpc1850-uart.txt b/dts/Bindings/serial/nxp,lpc1850-uart.txt new file mode 100644 index 0000000000..04e23e63ee --- /dev/null +++ b/dts/Bindings/serial/nxp,lpc1850-uart.txt @@ -0,0 +1,28 @@ +* NXP LPC1850 UART + +Required properties: +- compatible : "nxp,lpc1850-uart", "ns16550a". +- reg : offset and length of the register set for the device. +- interrupts : should contain uart interrupt. +- clocks : phandle to the input clocks. +- clock-names : required elements: "uartclk", "reg". + +Optional properties: +- dmas : Two or more DMA channel specifiers following the + convention outlined in bindings/dma/dma.txt +- dma-names : Names for the dma channels, if present. There must + be at least one channel named "tx" for transmit + and named "rx" for receive. + +Since it's also possible to also use the of_serial.c driver all +parameters from 8250.txt also apply but are optional. + +Example: +uart0: serial@40081000 { + compatible = "nxp,lpc1850-uart", "ns16550a"; + reg = <0x40081000 0x1000>; + reg-shift = <2>; + interrupts = <24>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; +}; diff --git a/dts/Bindings/serial/nxp,sc16is7xx.txt b/dts/Bindings/serial/nxp,sc16is7xx.txt index 246c795668..fbfe53635a 100644 --- a/dts/Bindings/serial/nxp,sc16is7xx.txt +++ b/dts/Bindings/serial/nxp,sc16is7xx.txt @@ -1,4 +1,5 @@ * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART) +* i2c as bus Required properties: - compatible: Should be one of the following: @@ -31,3 +32,39 @@ Example: gpio-controller; #gpio-cells = <2>; }; + +* spi as bus + +Required properties: +- compatible: Should be one of the following: + - "nxp,sc16is740" for NXP SC16IS740, + - "nxp,sc16is741" for NXP SC16IS741, + - "nxp,sc16is750" for NXP SC16IS750, + - "nxp,sc16is752" for NXP SC16IS752, + - "nxp,sc16is760" for NXP SC16IS760, + - "nxp,sc16is762" for NXP SC16IS762. +- reg: SPI chip select number. +- interrupt-parent: The phandle for the interrupt controller that + services interrupts for this IC. +- interrupts: Specifies the interrupt source of the parent interrupt + controller. The format of the interrupt specifier depends on the + parent interrupt controller. +- clocks: phandle to the IC source clock. + +Optional properties: +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be two. The first cell is the GPIO number and + the second cell is used to specify the GPIO polarity: + 0 = active high, + 1 = active low. + +Example: + sc16is750: sc16is750@0 { + compatible = "nxp,sc16is750"; + reg = <0>; + clocks = <&clk20m>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/dts/Bindings/serial/pl011.txt b/dts/Bindings/serial/pl011.txt index ba3ecb8cb5..cbae3d9a02 100644 --- a/dts/Bindings/serial/pl011.txt +++ b/dts/Bindings/serial/pl011.txt @@ -1,7 +1,7 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt index ae73bb0e9a..e84b13a8ed 100644 --- a/dts/Bindings/serial/renesas,sci-serial.txt +++ b/dts/Bindings/serial/renesas,sci-serial.txt @@ -29,6 +29,7 @@ Required properties: - "renesas,scifa" for generic SCIFA compatible UART. - "renesas,scifb" for generic SCIFB compatible UART. - "renesas,hscif" for generic HSCIF compatible UART. + - "renesas,sci" for generic SCI compatible UART. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first followed by the @@ -44,6 +45,11 @@ Required properties: Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node. +Optional properties: + - dmas: Must contain a list of two references to DMA specifiers, one for + transmission, and one for reception. + - dma-names: Must contain a list of two DMA names, "tx" and "rx". + Example: aliases { serial0 = &scifa0; @@ -56,4 +62,6 @@ Example: interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; }; diff --git a/dts/Bindings/serial/sirf-uart.txt b/dts/Bindings/serial/sirf-uart.txt index f0c39261c5..67e2a0aeb0 100644 --- a/dts/Bindings/serial/sirf-uart.txt +++ b/dts/Bindings/serial/sirf-uart.txt @@ -2,8 +2,7 @@ Required properties: - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", - "sirf,atlas7-uart" or "sirf,atlas7-bt-uart" which means - uart located in BT module and used for BT. + "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". - reg : Offset and length of the register set for the device - interrupts : Should contain uart interrupt - fifosize : Should define hardware rx/tx fifo size @@ -33,15 +32,3 @@ usp@b0090000 { rts-gpios = <&gpio 15 0>; cts-gpios = <&gpio 46 0>; }; - -for uart use in BT module, -uart6: uart@11000000 { - cell-index = <6>; - compatible = "sirf,atlas7-bt-uart", "sirf,atlas7-uart"; - reg = <0x11000000 0x1000>; - interrupts = <0 100 0>; - clocks = <&clks 138>, <&clks 140>, <&clks 141>; - clock-names = "uart", "general", "noc"; - fifosize = <128>; - status = "disabled"; -} diff --git a/dts/Bindings/serial/uniphier-uart.txt b/dts/Bindings/serial/uniphier-uart.txt new file mode 100644 index 0000000000..0b3892a7a5 --- /dev/null +++ b/dts/Bindings/serial/uniphier-uart.txt @@ -0,0 +1,23 @@ +UniPhier UART controller + +Required properties: +- compatible: should be "socionext,uniphier-uart". +- reg: offset and length of the register set for the device. +- interrupts: a single interrupt specifier. +- clocks: phandle to the input clock. + +Optional properties: +- fifo-size: the RX/TX FIFO size. Defaults to 64 if not specified. + +Example: + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; diff --git a/dts/Bindings/soc/fsl/qman-portals.txt b/dts/Bindings/soc/fsl/qman-portals.txt index 48c4dae5d6..47e46ccbc1 100644 --- a/dts/Bindings/soc/fsl/qman-portals.txt +++ b/dts/Bindings/soc/fsl/qman-portals.txt @@ -47,7 +47,7 @@ PROPERTIES For additional details about the PAMU/LIODN binding(s) see pamu.txt -- fsl,qman-channel-id +- cell-index Usage: Required Value type: Definition: The hardware index of the channel. This can also be @@ -136,7 +136,7 @@ The example below shows a (P4080) QMan portals container/bus node with two porta reg = <0x4000 0x4000>, <0x101000 0x1000>; interrupts = <106 2 0 0>; fsl,liodn = <3 4>; - fsl,qman-channel-id = <1>; + cell-index = <1>; fman0 { fsl,liodn = <0x22>; diff --git a/dts/Bindings/soc/sunxi/sram.txt b/dts/Bindings/soc/sunxi/sram.txt new file mode 100644 index 0000000000..067698112f --- /dev/null +++ b/dts/Bindings/soc/sunxi/sram.txt @@ -0,0 +1,72 @@ +Allwinnner SoC SRAM controllers +----------------------------------------------------- + +The SRAM controller found on most Allwinner devices is represented by +a regular node for the SRAM controller itself, with sub-nodes +reprensenting the SRAM handled by the SRAM controller. + +Controller Node +--------------- + +Required properties: +- compatible : "allwinner,sun4i-a10-sram-controller" +- reg : sram controller register offset + length + +SRAM nodes +---------- + +Each SRAM is described using the mmio-sram bindings documented in +Documentation/devicetree/bindings/misc/sram.txt + +Each SRAM will have SRAM sections that are going to be handled by the +SRAM controller as subnodes. These sections are represented following +once again the representation described in the mmio-sram binding. + +The valid sections compatible are: + - allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun4i-a10-sram-d + +Devices using SRAM sections +--------------------------- + +Some devices need to request to the SRAM controller to map an SRAM for +their exclusive use. + +The relationship between such a device and an SRAM section is +expressed through the allwinner,sram property, that will take a +phandle and an argument. + +This valid values for this argument are: + - 0: CPU + - 1: Device + +Example +------- +sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; +}; + +emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + ... + + allwinner,sram = <&emac_sram 1>; +}; diff --git a/dts/Bindings/sound/adi,adau1701.txt b/dts/Bindings/sound/adi,adau1701.txt index 547a49b56a..0d1128ce2e 100644 --- a/dts/Bindings/sound/adi,adau1701.txt +++ b/dts/Bindings/sound/adi,adau1701.txt @@ -20,6 +20,8 @@ Optional properties: pin configurations as described in the datasheet, table 53. Note that the value of this property has to be prefixed with '/bits/ 8'. + - avdd-supply: Power supply for AVDD, providing 3.3V + - dvdd-supply: Power supply for DVDD, providing 3.3V Examples: @@ -28,6 +30,8 @@ Examples: compatible = "adi,adau1701"; reg = <0x34>; reset-gpio = <&gpio 23 0>; + avdd-supply = <&vdd_3v3_reg>; + dvdd-supply = <&vdd_3v3_reg>; adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4>; diff --git a/dts/Bindings/sound/bt-sco.txt b/dts/Bindings/sound/bt-sco.txt new file mode 100644 index 0000000000..29b8e5d402 --- /dev/null +++ b/dts/Bindings/sound/bt-sco.txt @@ -0,0 +1,13 @@ +Bluetooth-SCO audio CODEC + +This device support generic Bluetooth SCO link. + +Required properties: + + - compatible : "delta,dfbmcs320" + +Example: + +codec: bt_sco { + compatible = "delta,dfbmcs320"; +}; diff --git a/dts/Bindings/sound/gtm601.txt b/dts/Bindings/sound/gtm601.txt new file mode 100644 index 0000000000..5efc8c068d --- /dev/null +++ b/dts/Bindings/sound/gtm601.txt @@ -0,0 +1,13 @@ +GTM601 UMTS modem audio interface CODEC + +This device has no configuration interface. Sample rate is fixed - 8kHz. + +Required properties: + + - compatible : "option,gtm601" + +Example: + +codec: gtm601_codec { + compatible = "option,gtm601"; +}; diff --git a/dts/Bindings/sound/max98090.txt b/dts/Bindings/sound/max98090.txt index aa802a2745..4e3be6682c 100644 --- a/dts/Bindings/sound/max98090.txt +++ b/dts/Bindings/sound/max98090.txt @@ -18,6 +18,12 @@ Optional properties: - maxim,dmic-freq: Frequency at which to clock DMIC +- maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are: + 0 - 2.2v + 1 - 2.55v + 2 - 2.4v + 3 - 2.8v + Pins on the device (for linking into audio routes): * MIC1 diff --git a/dts/Bindings/sound/mt8173-max98090.txt b/dts/Bindings/sound/mt8173-max98090.txt new file mode 100644 index 0000000000..829bd26d17 --- /dev/null +++ b/dts/Bindings/sound/mt8173-max98090.txt @@ -0,0 +1,13 @@ +MT8173 with MAX98090 CODEC + +Required properties: +- compatible : "mediatek,mt8173-max98090" +- mediatek,audio-codec: the phandle of the MAX98090 audio codec + +Example: + + sound { + compatible = "mediatek,mt8173-max98090"; + mediatek,audio-codec = <&max98090>; + }; + diff --git a/dts/Bindings/sound/mt8173-rt5650-rt5676.txt b/dts/Bindings/sound/mt8173-rt5650-rt5676.txt new file mode 100644 index 0000000000..61e98c976b --- /dev/null +++ b/dts/Bindings/sound/mt8173-rt5650-rt5676.txt @@ -0,0 +1,13 @@ +MT8173 with RT5650 RT5676 CODECS + +Required properties: +- compatible : "mediatek,mt8173-rt5650-rt5676" +- mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs + +Example: + + sound { + compatible = "mediatek,mt8173-rt5650-rt5676"; + mediatek,audio-codec = <&rt5650 &rt5676>; + }; + diff --git a/dts/Bindings/sound/mtk-afe-pcm.txt b/dts/Bindings/sound/mtk-afe-pcm.txt new file mode 100644 index 0000000000..e302c7f43b --- /dev/null +++ b/dts/Bindings/sound/mtk-afe-pcm.txt @@ -0,0 +1,45 @@ +Mediatek AFE PCM controller + +Required properties: +- compatible = "mediatek,mt8173-afe-pcm"; +- reg: register location and size +- interrupts: Should contain AFE interrupt +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + +Example: + + afe: mt8173-afe-pcm@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = ; + clocks = <&infracfg INFRA_AUDIO>, + <&topckgen TOP_AUDIO_SEL>, + <&topckgen TOP_AUD_INTBUS_SEL>, + <&topckgen TOP_APLL1_DIV0>, + <&topckgen TOP_APLL2_DIV0>, + <&topckgen TOP_I2S0_M_CK_SEL>, + <&topckgen TOP_I2S1_M_CK_SEL>, + <&topckgen TOP_I2S2_M_CK_SEL>, + <&topckgen TOP_I2S3_M_CK_SEL>, + <&topckgen TOP_I2S3_B_CK_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + }; diff --git a/dts/Bindings/sound/qcom,apq8016-sbc.txt b/dts/Bindings/sound/qcom,apq8016-sbc.txt new file mode 100644 index 0000000000..48129368d4 --- /dev/null +++ b/dts/Bindings/sound/qcom,apq8016-sbc.txt @@ -0,0 +1,60 @@ +* Qualcomm Technologies APQ8016 SBC ASoC machine driver + +This node models the Qualcomm Technologies APQ8016 SBC ASoC machine driver + +Required properties: + +- compatible : "qcom,apq8016-sbc-sndcard" + +- pinctrl-N : One property must exist for each entry in + pinctrl-names. See ../pinctrl/pinctrl-bindings.txt + for details of the property values. +- pinctrl-names : Must contain a "default" entry. +- reg : Must contain an address for each entry in reg-names. +- reg-names : A list which must include the following entries: + * "mic-iomux" + * "spkr-iomux" +- qcom,model : Name of the sound card. + +Dai-link subnode properties and subnodes: + +Required dai-link subnodes: + +- cpu : CPU sub-node +- codec : CODEC sub-node + +Required CPU/CODEC subnodes properties: + +-link-name : Name of the dai link. +-sound-dai : phandle and port of CPU/CODEC +-capture-dai : phandle and port of CPU/CODEC + +Example: + +sound: sound { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + qcom,model = "DB410c"; + + /* I2S - Internal codec */ + internal-dai-link@0 { + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&wcd_codec 0>; + }; + }; + + /* External Primary or External Secondary -ADV7533 HDMI */ + external-dai-link@0 { + link-name = "ADV7533"; + cpu { /* QUAT */ + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; +}; diff --git a/dts/Bindings/sound/qcom,lpass-cpu.txt b/dts/Bindings/sound/qcom,lpass-cpu.txt index e00732dac9..21c648328b 100644 --- a/dts/Bindings/sound/qcom,lpass-cpu.txt +++ b/dts/Bindings/sound/qcom,lpass-cpu.txt @@ -4,12 +4,21 @@ This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS). Required properties: -- compatible : "qcom,lpass-cpu" +- compatible : "qcom,lpass-cpu" or "qcom,apq8016-lpass-cpu" - clocks : Must contain an entry for each entry in clock-names. - clock-names : A list which must include the following entries: * "ahbix-clk" * "mi2s-osr-clk" * "mi2s-bit-clk" + : required clocks for "qcom,lpass-cpu-apq8016" + * "ahbix-clk" + * "mi2s-bit-clk0" + * "mi2s-bit-clk1" + * "mi2s-bit-clk2" + * "mi2s-bit-clk3" + * "pcnoc-mport-clk" + * "pcnoc-sway-clk" + - interrupts : Must contain an entry for each entry in interrupt-names. - interrupt-names : A list which must include the following entries: @@ -22,6 +31,8 @@ Required properties: - reg-names : A list which must include the following entries: * "lpass-lpaif" + + Optional properties: - qcom,adsp : Phandle for the audio DSP node diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt index f316ce1f21..b6b3a78685 100644 --- a/dts/Bindings/sound/renesas,rsnd.txt +++ b/dts/Bindings/sound/renesas,rsnd.txt @@ -5,6 +5,7 @@ Required properties: "renesas,rcar_sound-gen1" if generation1, and "renesas,rcar_sound-gen2" if generation2 Examples with soctypes are: + - "renesas,rcar_sound-r8a7778" (R-Car M1A) - "renesas,rcar_sound-r8a7790" (R-Car H2) - "renesas,rcar_sound-r8a7791" (R-Car M2-W) - reg : Should contain the register physical address. @@ -47,7 +48,7 @@ DAI subnode properties: Example: -rcar_sound: rcar_sound@ec500000 { +rcar_sound: sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; reg = <0 0xec500000 0 0x1000>, /* SCU */ diff --git a/dts/Bindings/sound/rt5645.txt b/dts/Bindings/sound/rt5645.txt new file mode 100644 index 0000000000..7cee1f518f --- /dev/null +++ b/dts/Bindings/sound/rt5645.txt @@ -0,0 +1,72 @@ +RT5650/RT5645 audio CODEC + +This device supports I2C only. + +Required properties: + +- compatible : One of "realtek,rt5645" or "realtek,rt5650". + +- reg : The I2C address of the device. + +- interrupts : The CODEC's interrupt output. + +Optional properties: + +- hp-detect-gpios: + a GPIO spec for the external headphone detect pin. If jd-mode = 0, + we will get the JD status by getting the value of hp-detect-gpios. + +- realtek,in2-differential + Boolean. Indicate MIC2 input are differential, rather than single-ended. + +- realtek,dmic1-data-pin + 0: dmic1 is not used + 1: using IN2P pin as dmic1 data pin + 2: using GPIO6 pin as dmic1 data pin + 3: using GPIO10 pin as dmic1 data pin + 4: using GPIO12 pin as dmic1 data pin + +- realtek,dmic2-data-pin + 0: dmic2 is not used + 1: using IN2N pin as dmic2 data pin + 2: using GPIO5 pin as dmic2 data pin + 3: using GPIO11 pin as dmic2 data pin + +-- realtek,jd-mode : The JD mode of rt5645/rt5650 + 0 : rt5645/rt5650 JD function is not used + 1 : Mode-0 (VDD=3.3V), two port jack detection + 2 : Mode-1 (VDD=3.3V), one port jack detection + 3 : Mode-2 (VDD=1.8V), one port jack detection + +Pins on the device (for linking into audio routes) for RT5645/RT5650: + + * DMIC L1 + * DMIC R1 + * DMIC L2 + * DMIC R2 + * IN1P + * IN1N + * IN2P + * IN2N + * Haptic Generator + * HPOL + * HPOR + * LOUTL + * LOUTR + * PDM1L + * PDM1R + * SPOL + * SPOR + +Example: + +codec: rt5650@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + hp-detect-gpios = <&gpio 19 0>; + interrupt-parent = <&gpio>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + realtek,dmic-en = "true"; + realtek,en-jd-func = "true"; + realtek,jd-mode = <3>; +}; \ No newline at end of file diff --git a/dts/Bindings/sound/rt5677.txt b/dts/Bindings/sound/rt5677.txt index 740ff771aa..f07078997f 100644 --- a/dts/Bindings/sound/rt5677.txt +++ b/dts/Bindings/sound/rt5677.txt @@ -18,6 +18,7 @@ Required properties: Optional properties: - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin. +- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. - realtek,in1-differential - realtek,in2-differential @@ -70,6 +71,7 @@ rt5677 { realtek,pow-ldo2-gpio = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; realtek,in1-differential = "true"; realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */ realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */ diff --git a/dts/Bindings/sound/simple-card.txt b/dts/Bindings/sound/simple-card.txt index 73bf314f72..cf3979eb35 100644 --- a/dts/Bindings/sound/simple-card.txt +++ b/dts/Bindings/sound/simple-card.txt @@ -16,7 +16,8 @@ Optional properties: connection's sink, the second being the connection's source. - simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec - mclk. + mclk. When defined, mclk-fs property defined in + dai-link sub nodes are ignored. - simple-audio-card,hp-det-gpio : Reference to GPIO that signals when headphones are attached. - simple-audio-card,mic-det-gpio : Reference to GPIO that signals when @@ -55,6 +56,9 @@ Optional dai-link subnode properties: dai-link uses bit clock inversion. - frame-inversion : bool property. Add this if the dai-link uses frame clock inversion. +- mclk-fs : Multiplication factor between stream + rate and codec mclk, applied only for + the dai-link. For backward compatibility the frame-master and bitclock-master properties can be used as booleans in codec subnode to indicate if the diff --git a/dts/Bindings/sound/tas2552.txt b/dts/Bindings/sound/tas2552.txt index 55e2a0af56..c49992c0b6 100644 --- a/dts/Bindings/sound/tas2552.txt +++ b/dts/Bindings/sound/tas2552.txt @@ -14,6 +14,12 @@ Required properties: Optional properties: - enable-gpio - gpio pin to enable/disable the device +tas2552 can receive it's reference clock via MCLK, BCLK, IVCLKIN pin or use the +internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM +reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. +For system integration the dt-bindings/sound/tas2552.h header file provides +defined values to selct and configure the PLL and PDM reference clocks. + Example: tas2552: tas2552@41 { diff --git a/dts/Bindings/sound/tas571x.txt b/dts/Bindings/sound/tas571x.txt new file mode 100644 index 0000000000..0ac31d8d5a --- /dev/null +++ b/dts/Bindings/sound/tas571x.txt @@ -0,0 +1,41 @@ +Texas Instruments TAS5711/TAS5717/TAS5719 stereo power amplifiers + +The codec is controlled through an I2C interface. It also has two other +signals that can be wired up to GPIOs: reset (strongly recommended), and +powerdown (optional). + +Required properties: + +- compatible: "ti,tas5711", "ti,tas5717", or "ti,tas5719" +- reg: The I2C address of the device +- #sound-dai-cells: must be equal to 0 + +Optional properties: + +- reset-gpios: GPIO specifier for the TAS571x's active low reset line +- pdn-gpios: GPIO specifier for the TAS571x's active low powerdown line +- clocks: clock phandle for the MCLK input +- clock-names: should be "mclk" +- AVDD-supply: regulator phandle for the AVDD supply (all chips) +- DVDD-supply: regulator phandle for the DVDD supply (all chips) +- HPVDD-supply: regulator phandle for the HPVDD supply (5717/5719) +- PVDD_AB-supply: regulator phandle for the PVDD_AB supply (5717/5719) +- PVDD_CD-supply: regulator phandle for the PVDD_CD supply (5717/5719) +- PVDD_A-supply: regulator phandle for the PVDD_A supply (5711) +- PVDD_B-supply: regulator phandle for the PVDD_B supply (5711) +- PVDD_C-supply: regulator phandle for the PVDD_C supply (5711) +- PVDD_D-supply: regulator phandle for the PVDD_D supply (5711) + +Example: + + tas5717: audio-codec@2a { + compatible = "ti,tas5717"; + reg = <0x2a>; + #sound-dai-cells = <0>; + + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pdn-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + + clocks = <&clk_core CLK_I2S>; + clock-names = "mclk"; + }; diff --git a/dts/Bindings/sound/wm8741.txt b/dts/Bindings/sound/wm8741.txt index 74bda58c1b..a133154087 100644 --- a/dts/Bindings/sound/wm8741.txt +++ b/dts/Bindings/sound/wm8741.txt @@ -10,9 +10,20 @@ Required properties: - reg : the I2C address of the device for I2C, the chip select number for SPI. +Optional properties: + + - diff-mode: Differential output mode configuration. Default value for field + DIFF in register R8 (MODE_CONTROL_2). If absent, the default is 0, shall be: + 0 = stereo + 1 = mono left + 2 = stereo reversed + 3 = mono right + Example: codec: wm8741@1a { compatible = "wlf,wm8741"; reg = <0x1a>; + + diff-mode = <3>; }; diff --git a/dts/Bindings/sound/zte,zx-i2s.txt b/dts/Bindings/sound/zte,zx-i2s.txt new file mode 100644 index 0000000000..7e5aa6f6b5 --- /dev/null +++ b/dts/Bindings/sound/zte,zx-i2s.txt @@ -0,0 +1,44 @@ +ZTE ZX296702 I2S controller + +Required properties: + - compatible : Must be "zte,zx296702-i2s" + - reg : Must contain I2S core's registers location and length + - clocks : Pairs of phandle and specifier referencing the controller's clocks. + - clock-names: "tx" for the clock to the I2S interface. + - dmas: Pairs of phandle and specifier for the DMA channel that is used by + the core. The core expects two dma channels for transmit. + - dma-names : Must be "tx" and "rx" + +For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties +please check: + * resource-names.txt + * clock/clock-bindings.txt + * dma/dma.txt + +Example: + i2s0: i2s0@0b005000 { + #sound-dai-cells = <0>; + compatible = "zte,zx296702-i2s"; + reg = <0x0b005000 0x1000>; + clocks = <&lsp0clk ZX296702_I2S0_DIV>; + clock-names = "tx"; + interrupts = ; + dmas = <&dma 5>, <&dma 6>; + dma-names = "tx", "rx"; + status = "okay"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "zx296702_snd"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; diff --git a/dts/Bindings/sound/zte,zx-spdif.txt b/dts/Bindings/sound/zte,zx-spdif.txt new file mode 100644 index 0000000000..989544ea6e --- /dev/null +++ b/dts/Bindings/sound/zte,zx-spdif.txt @@ -0,0 +1,28 @@ +ZTE ZX296702 SPDIF controller + +Required properties: + - compatible : Must be "zte,zx296702-spdif" + - reg : Must contain SPDIF core's registers location and length + - clocks : Pairs of phandle and specifier referencing the controller's clocks. + - clock-names: "tx" for the clock to the SPDIF interface. + - dmas: Pairs of phandle and specifier for the DMA channel that is used by + the core. The core expects one dma channel for transmit. + - dma-names : Must be "tx" + +For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties +please check: + * resource-names.txt + * clock/clock-bindings.txt + * dma/dma.txt + +Example: + spdif0: spdif0@0b004000 { + compatible = "zte,zx296702-spdif"; + reg = <0x0b004000 0x1000>; + clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; + clock-names = "tx"; + interrupts = ; + dmas = <&dma 4>; + dma-names = "tx"; + status = "okay"; + }; diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt index 4c388bb2f0..8f771441be 100644 --- a/dts/Bindings/spi/sh-msiof.txt +++ b/dts/Bindings/spi/sh-msiof.txt @@ -60,7 +60,7 @@ Example: msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; diff --git a/dts/Bindings/spi/spi-ath79.txt b/dts/Bindings/spi/spi-ath79.txt new file mode 100644 index 0000000000..f1ad9c3675 --- /dev/null +++ b/dts/Bindings/spi/spi-ath79.txt @@ -0,0 +1,24 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- clocks: phandle to the AHB clock. +- clock-names: has to be "ahb". +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1F000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1F000000 0x10>; + + clocks = <&pll 2>; + clock-names = "ahb"; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/dts/Bindings/spi/spi-fsl-dspi.txt b/dts/Bindings/spi/spi-fsl-dspi.txt index 70af78a918..fa77f874e3 100644 --- a/dts/Bindings/spi/spi-fsl-dspi.txt +++ b/dts/Bindings/spi/spi-fsl-dspi.txt @@ -1,7 +1,7 @@ ARM Freescale DSPI controller Required properties: -- compatible : "fsl,vf610-dspi" +- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", "fsl,ls2085a-dspi" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt - clocks: from common clock binding: handle to dspi clock. diff --git a/dts/Bindings/spi/spi-orion.txt b/dts/Bindings/spi/spi-orion.txt index 50c3a3de61..98bc69815e 100644 --- a/dts/Bindings/spi/spi-orion.txt +++ b/dts/Bindings/spi/spi-orion.txt @@ -1,7 +1,13 @@ Marvell Orion SPI device Required properties: -- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi". +- compatible : should be on of the following: + - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs + - "marvell,armada-370-spi", for the Armada 370 SoCs + - "marvell,armada-375-spi", for the Armada 375 SoCs + - "marvell,armada-380-spi", for the Armada 38x SoCs + - "marvell,armada-390-spi", for the Armada 39x SoCs + - "marvell,armada-xp-spi", for the Armada XP SoCs - reg : offset and length of the register set for the device - cell-index : Which of multiple SPI controllers is this. Optional properties: diff --git a/dts/Bindings/spi/spi-sirf.txt b/dts/Bindings/spi/spi-sirf.txt index 4c7adb8f77..ddd78ff68f 100644 --- a/dts/Bindings/spi/spi-sirf.txt +++ b/dts/Bindings/spi/spi-sirf.txt @@ -1,7 +1,8 @@ * CSR SiRFprimaII Serial Peripheral Interface Required properties: -- compatible : Should be "sirf,prima2-spi" +- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp" + or "sirf,atlas7-usp" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI interrupt - resets: phandle to the reset controller asserting this device in diff --git a/dts/Bindings/spi/spi-zynqmp-qspi.txt b/dts/Bindings/spi/spi-zynqmp-qspi.txt new file mode 100644 index 0000000000..c8f50e5cf7 --- /dev/null +++ b/dts/Bindings/spi/spi-zynqmp-qspi.txt @@ -0,0 +1,26 @@ +Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings +------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,zynqmp-qspi-1.0". +- reg : Physical base address and size of GQSPI registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller. +- clock-names : List of input clock names - "ref_clk", "pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). + +Optional properties: +- num-cs : Number of chip selects used. + +Example: + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + clock-names = "ref_clk", "pclk"; + clocks = <&misc_clk &misc_clk>; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>; + }; diff --git a/dts/Bindings/spi/spi_atmel.txt b/dts/Bindings/spi/spi_atmel.txt index 4f8184d069..fb588b3e6a 100644 --- a/dts/Bindings/spi/spi_atmel.txt +++ b/dts/Bindings/spi/spi_atmel.txt @@ -4,11 +4,16 @@ Required properties: - compatible : should be "atmel,at91rm9200-spi". - reg: Address and length of the register set for the device - interrupts: Should contain spi interrupt -- cs-gpios: chipselects +- cs-gpios: chipselects (optional for SPI controller version >= 2 with the + Chip Select Active After Transfer feature). - clock-names: tuple listing input clock names. Required elements: "spi_clk" - clocks: phandles to input clocks. +Optional properties: +- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO + capable SPI controllers. + Example: spi1: spi@fffcc000 { @@ -20,6 +25,7 @@ spi1: spi@fffcc000 { clocks = <&spi1_clk>; clock-names = "spi_clk"; cs-gpios = <&pioB 3 0>; + atmel,fifo-size = <32>; status = "okay"; mmc-slot@0 { diff --git a/dts/Bindings/spi/spi_pl022.txt b/dts/Bindings/spi/spi_pl022.txt index 22ed679721..4d1673ca8c 100644 --- a/dts/Bindings/spi/spi_pl022.txt +++ b/dts/Bindings/spi/spi_pl022.txt @@ -4,9 +4,9 @@ Required properties: - compatible : "arm,pl022", "arm,primecell" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt +- num-cs : total number of chipselects Optional properties: -- num-cs : total number of chipselects - cs-gpios : should specify GPIOs used for chipselects. The gpios will be referred to as reg = in the SPI child nodes. If unspecified, a single SPI device without a chip select can be used. diff --git a/dts/Bindings/thermal/hisilicon-thermal.txt b/dts/Bindings/thermal/hisilicon-thermal.txt new file mode 100644 index 0000000000..d48fc5280d --- /dev/null +++ b/dts/Bindings/thermal/hisilicon-thermal.txt @@ -0,0 +1,23 @@ +* Temperature Sensor on hisilicon SoCs + +** Required properties : + +- compatible: "hisilicon,tsensor". +- reg: physical base address of thermal sensor and length of memory mapped + region. +- interrupt: The interrupt number to the cpu. Defines the interrupt used + by /SOCTHERM/tsensor. +- clock-names: Input clock name, should be 'thermal_clk'. +- clocks: phandles for clock specified in "clock-names" property. +- #thermal-sensor-cells: Should be 1. See ./thermal.txt for a description. + +Example : + + tsensor: tsensor@0,f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0x0 0xf7030700 0x0 0x1000>; + interrupts = <0 7 0x4>; + clocks = <&sys_ctrl HI6220_TSENSOR_CLK>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + } diff --git a/dts/Bindings/thermal/qcom-spmi-temp-alarm.txt b/dts/Bindings/thermal/qcom-spmi-temp-alarm.txt new file mode 100644 index 0000000000..290ec06fa3 --- /dev/null +++ b/dts/Bindings/thermal/qcom-spmi-temp-alarm.txt @@ -0,0 +1,57 @@ +Qualcomm QPNP PMIC Temperature Alarm + +QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips +that utilize the Qualcomm SPMI implementation. These peripherals provide an +interrupt signal and status register to identify high PMIC die temperature. + +Required properties: +- compatible: Should contain "qcom,spmi-temp-alarm". +- reg: Specifies the SPMI address and length of the controller's + registers. +- interrupts: PMIC temperature alarm interrupt. +- #thermal-sensor-cells: Should be 0. See thermal.txt for a description. + +Optional properties: +- io-channels: Should contain IIO channel specifier for the ADC channel, + which report chip die temperature. +- io-channel-names: Should contain "thermal". + +Example: + + pm8941_temp: thermal-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + + io-channels = <&pm8941_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + }; + + thermal-zones { + pm8941 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8941_temp>; + + trips { + passive { + temperature = <1050000>; + hysteresis = <2000>; + type = "passive"; + }; + alert { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + diff --git a/dts/Bindings/thermal/thermal.txt b/dts/Bindings/thermal/thermal.txt index 29fe0bfae3..8a49362dea 100644 --- a/dts/Bindings/thermal/thermal.txt +++ b/dts/Bindings/thermal/thermal.txt @@ -167,6 +167,13 @@ Optional property: by means of sensor ID. Additional coefficients are interpreted as constant offset. +- sustainable-power: An estimate of the sustainable power (in mW) that the + Type: unsigned thermal zone can dissipate at the desired + Size: one cell control temperature. For reference, the + sustainable power of a 4'' phone is typically + 2000mW, while on a 10'' tablet is around + 4500mW. + Note: The delay properties are bound to the maximum dT/dt (temperature derivative over time) in two situations for a thermal zone: (i) - when passive cooling is activated (polling-delay-passive); and @@ -546,6 +553,8 @@ thermal-zones { */ coefficients = <1200 -345 890>; + sustainable-power = <2500>; + trips { /* Trips are based on resulting linear equation */ cpu_trip: cpu-trip { diff --git a/dts/Bindings/timer/cadence,ttc-timer.txt b/dts/Bindings/timer/cadence,ttc-timer.txt index 993695c659..eeee6cd51e 100644 --- a/dts/Bindings/timer/cadence,ttc-timer.txt +++ b/dts/Bindings/timer/cadence,ttc-timer.txt @@ -6,6 +6,9 @@ Required properties: - interrupts : A list of 3 interrupts; one per timer channel. - clocks: phandle to the source clock +Optional properties: +- timer-width: Bit width of the timer, necessary if not 16. + Example: ttc0: ttc0@f8001000 { @@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 { compatible = "cdns,ttc"; reg = <0xF8001000 0x1000>; clocks = <&cpu_clk 3>; + timer-width = <32>; }; diff --git a/dts/Bindings/timer/nxp,lpc3220-timer.txt b/dts/Bindings/timer/nxp,lpc3220-timer.txt new file mode 100644 index 0000000000..51b05a0e70 --- /dev/null +++ b/dts/Bindings/timer/nxp,lpc3220-timer.txt @@ -0,0 +1,26 @@ +* NXP LPC3220 timer + +The NXP LPC3220 timer is used on a wide range of NXP SoCs. This +includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts. + +Required properties: +- compatible: + Should be "nxp,lpc3220-timer". +- reg: + Address and length of the register set. +- interrupts: + Reference to the timer interrupt +- clocks: + Should contain a reference to timer clock. +- clock-names: + Should contain "timerclk". + +Example: + +timer1: timer@40085000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&ccu1 CLK_CPU_TIMER1>; + clock-names = "timerclk"; +}; diff --git a/dts/Bindings/timer/renesas,16bit-timer.txt b/dts/Bindings/timer/renesas,16bit-timer.txt new file mode 100644 index 0000000000..e8792447a1 --- /dev/null +++ b/dts/Bindings/timer/renesas,16bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 16bit timer + +The 16bit timer is a 16bit timer/counter with configurable clock inputs and +programmable compare match. + +Required Properties: + + - compatible: must contain "renesas,16bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, IMIA + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + - renesas,channel: timer channel number. + +Example: + + timer16: timer@ffff68 { + compatible = "reneas,16bit-timer"; + reg = <0xffff68 8>, <0xffff60 8>; + interrupts = <24>; + renesas,channel = <0>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; + diff --git a/dts/Bindings/timer/renesas,8bit-timer.txt b/dts/Bindings/timer/renesas,8bit-timer.txt new file mode 100644 index 0000000000..9dca3759a0 --- /dev/null +++ b/dts/Bindings/timer/renesas,8bit-timer.txt @@ -0,0 +1,25 @@ +* Renesas H8/300 8bit timer + +The 8bit timer is a 8bit timer/counter with configurable clock inputs and +programmable compare match. + +This implement only supported cascade mode. + +Required Properties: + + - compatible: must contain "renesas,8bit-timer" + - reg: base address and length of the registers block for the timer module. + - interrupts: interrupt-specifier for the timer, CMIA and TOVI + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "fck" for the functional clock. + +Example: + + timer8_0: timer@ffff80 { + compatible = "renesas,8bit-timer"; + reg = <0xffff80 10>; + interrupts = <36>; + clocks = <&fclk>; + clock-names = "fck"; + }; + diff --git a/dts/Bindings/timer/renesas,tpu.txt b/dts/Bindings/timer/renesas,tpu.txt new file mode 100644 index 0000000000..f8b25897fb --- /dev/null +++ b/dts/Bindings/timer/renesas,tpu.txt @@ -0,0 +1,21 @@ +* Renesas H8/300 Timer Pluse Unit + +The TPU is a 16bit timer/counter with configurable clock inputs and +programmable compare match. +This implementation support only cascade mode. + +Required Properties: + + - compatible: must contain "renesas,tpu" + - reg: base address and length of the registers block in 2 channel. + - clocks: a list of phandle, one for each entry in clock-names. + - clock-names: must contain "peripheral_clk" for the functional clock. + + +Example: + tpu: tpu@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&pclk>; + clock-names = "peripheral_clk"; + }; diff --git a/dts/Bindings/timer/st,stm32-timer.txt b/dts/Bindings/timer/st,stm32-timer.txt new file mode 100644 index 0000000000..8ef28e70d6 --- /dev/null +++ b/dts/Bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +}; diff --git a/dts/Bindings/usb/atmel-usb.txt b/dts/Bindings/usb/atmel-usb.txt index e180d56c75..5883b73ea1 100644 --- a/dts/Bindings/usb/atmel-usb.txt +++ b/dts/Bindings/usb/atmel-usb.txt @@ -5,6 +5,13 @@ OHCI Required properties: - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers used in host mode. + - reg: Address and length of the register set for the device + - interrupts: Should contain ehci interrupt + - clocks: Should reference the peripheral, host and system clocks + - clock-names: Should contains two strings + "ohci_clk" for the peripheral clock + "hclk" for the host clock + "uhpck" for the system clock - num-ports: Number of ports. - atmel,vbus-gpio: If present, specifies a gpio that needs to be activated for the bus to be powered. @@ -14,6 +21,8 @@ Required properties: usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; interrupts = <20 4>; num-ports = <2>; }; @@ -23,11 +32,19 @@ EHCI Required properties: - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers used in host mode. + - reg: Address and length of the register set for the device + - interrupts: Should contain ehci interrupt + - clocks: Should reference the peripheral and the UTMI clocks + - clock-names: Should contains two strings + "ehci_clk" for the peripheral clock + "usb_clk" for the UTMI clock usb1: ehci@00800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 4>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; }; AT91 USB device controller @@ -53,6 +70,8 @@ usb1: gadget@fffa4000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffa4000 0x4000>; interrupts = <10 4>; + clocks = <&udc_clk>, <&udpck>; + clock-names = "pclk", "hclk"; atmel,vbus-gpio = <&pioC 5 0>; }; @@ -60,11 +79,15 @@ Atmel High-Speed USB device controller Required properties: - compatible: Should be one of the following - "at91sam9rl-udc" - "at91sam9g45-udc" - "sama5d3-udc" + "atmel,at91sam9rl-udc" + "atmel,at91sam9g45-udc" + "atmel,sama5d3-udc" - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt + - clocks: Should reference the peripheral and host clocks + - clock-names: Should contains two strings + "pclk" for the peripheral clock + "hclk" for the host clock - ep childnode: To specify the number of endpoints and their properties. Optional properties: @@ -86,6 +109,8 @@ usb2: gadget@fff78000 { reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 4 0>; + clocks = <&utmi>, <&udphs_clk>; + clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; ep0 { diff --git a/dts/Bindings/usb/ci-hdrc-imx.txt b/dts/Bindings/usb/ci-hdrc-imx.txt deleted file mode 100644 index 38a548001e..0000000000 --- a/dts/Bindings/usb/ci-hdrc-imx.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Freescale i.MX ci13xxx usb controllers - -Required properties: -- compatible: Should be "fsl,imx27-usb" -- reg: Should contain registers location and length -- interrupts: Should contain controller interrupt -- fsl,usbphy: phandle of usb phy that connects to the port - -Recommended properies: -- phy_type: the type of the phy connected to the core. Should be one - of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this - property the PORTSC register won't be touched -- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" - -Optional properties: -- fsl,usbmisc: phandler of non-core register device, with one argument - that indicate usb controller index -- vbus-supply: regulator for vbus -- disable-over-current: disable over current detect -- external-vbus-divider: enables off-chip resistor divider for Vbus -- maximum-speed: limit the maximum connection speed to "full-speed". -- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts - -Examples: -usb@02184000 { /* USB OTG */ - compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 0x04>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - disable-over-current; - external-vbus-divider; - maximum-speed = "full-speed"; - tpl-support; -}; diff --git a/dts/Bindings/usb/ci-hdrc-qcom.txt b/dts/Bindings/usb/ci-hdrc-qcom.txt deleted file mode 100644 index f2899b5509..0000000000 --- a/dts/Bindings/usb/ci-hdrc-qcom.txt +++ /dev/null @@ -1,17 +0,0 @@ -Qualcomm CI13xxx (Chipidea) USB controllers - -Required properties: -- compatible: should contain "qcom,ci-hdrc" -- reg: offset and length of the register set in the memory map -- interrupts: interrupt-specifier for the controller interrupt. -- usb-phy: phandle for the PHY device -- dr_mode: Should be "peripheral" - -Examples: - gadget@f9a55000 { - compatible = "qcom,ci-hdrc"; - reg = <0xf9a55000 0x400>; - dr_mode = "peripheral"; - interrupts = <0 134 0>; - usb-phy = <&usbphy0>; - }; diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt index 27f8b1e5ee..553e2fae3a 100644 --- a/dts/Bindings/usb/ci-hdrc-usb2.txt +++ b/dts/Bindings/usb/ci-hdrc-usb2.txt @@ -1,15 +1,35 @@ * USB2 ChipIdea USB controller for ci13xxx Required properties: -- compatible: should be "chipidea,usb2" +- compatible: should be one of: + "fsl,imx27-usb" + "lsi,zevio-usb" + "qcom,ci-hdrc" + "chipidea,usb2" - reg: base address and length of the registers - interrupts: interrupt for the USB controller +Recommended properies: +- phy_type: the type of the phy connected to the core. Should be one + of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this + property the PORTSC register won't be touched. +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" + +Deprecated properties: +- usb-phy: phandle for the PHY device. Use "phys" instead. +- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead. + Optional properties: - clocks: reference to the USB clock - phys: reference to the USB PHY - phy-names: should be "usb-phy" - vbus-supply: reference to the VBUS regulator +- maximum-speed: limit the maximum connection speed to "full-speed". +- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts +- fsl,usbmisc: (FSL only) phandler of non-core register device, with one + argument that indicate usb controller index +- disable-over-current: (FSL only) disable over current detect +- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus Example: diff --git a/dts/Bindings/usb/ci-hdrc-zevio.txt b/dts/Bindings/usb/ci-hdrc-zevio.txt deleted file mode 100644 index abbcb2aea3..0000000000 --- a/dts/Bindings/usb/ci-hdrc-zevio.txt +++ /dev/null @@ -1,17 +0,0 @@ -* LSI Zevio USB OTG Controller - -Required properties: -- compatible: Should be "lsi,zevio-usb" -- reg: Should contain registers location and length -- interrupts: Should contain controller interrupt - -Optional properties: -- vbus-supply: regulator for vbus - -Examples: - usb0: usb@b0000000 { - reg = <0xb0000000 0x1000>; - compatible = "lsi,zevio-usb"; - interrupts = <8>; - vbus-supply = <&vbus_reg>; - }; diff --git a/dts/Bindings/usb/dwc3-st.txt b/dts/Bindings/usb/dwc3-st.txt index f9d70252bb..01c71b1258 100644 --- a/dts/Bindings/usb/dwc3-st.txt +++ b/dts/Bindings/usb/dwc3-st.txt @@ -49,8 +49,7 @@ st_dwc3: dwc3@8f94000 { st,syscfg = <&syscfg_core>; resets = <&powerdown STIH407_USB3_POWERDOWN>, <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", - "softreset"; + reset-names = "powerdown", "softreset"; #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; @@ -62,7 +61,7 @@ st_dwc3: dwc3@8f94000 { reg = <0x09900000 0x100000>; interrupts = ; dr_mode = "host"; - phys-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>; }; }; diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt index 5cc364309e..0815eac5b1 100644 --- a/dts/Bindings/usb/dwc3.txt +++ b/dts/Bindings/usb/dwc3.txt @@ -38,6 +38,8 @@ Optional properties: - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold + - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for + UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. This is usually a subnode to DWC3 glue to which it is connected. diff --git a/dts/Bindings/usb/msm-hsusb.txt b/dts/Bindings/usb/msm-hsusb.txt index 2826f2af50..bd8d9e7530 100644 --- a/dts/Bindings/usb/msm-hsusb.txt +++ b/dts/Bindings/usb/msm-hsusb.txt @@ -69,6 +69,17 @@ Optional properties: (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner. +- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy + and controller driver therefore enables pull-up explicitly + before starting controller using usbcmd run/stop bit. + +- extcon: phandles to external connector devices. First phandle + should point to external connector, which provide "USB" + cable events, the second should point to external connector + device, which provide "USB-HOST" cable events. If one of + the external connector devices is not required empty <0> + phandle should be specified. + Example HSUSB OTG controller device node: usb@f9a55000 { diff --git a/dts/Bindings/usb/renesas_usbhs.txt b/dts/Bindings/usb/renesas_usbhs.txt index ddbe304beb..64a4ca6cf9 100644 --- a/dts/Bindings/usb/renesas_usbhs.txt +++ b/dts/Bindings/usb/renesas_usbhs.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must contain one of the following: - "renesas,usbhs-r8a7790" - "renesas,usbhs-r8a7791" + - "renesas,usbhs-r8a7794" - reg: Base address and length of the register for the USBHS - interrupts: Interrupt specifier for the USBHS - clocks: A list of phandle + clock specifier pairs diff --git a/dts/Bindings/usb/twlxxxx-usb.txt b/dts/Bindings/usb/twlxxxx-usb.txt index 0aee0ad3f0..17327a2961 100644 --- a/dts/Bindings/usb/twlxxxx-usb.txt +++ b/dts/Bindings/usb/twlxxxx-usb.txt @@ -30,6 +30,9 @@ TWL4030 USB PHY AND COMPARATOR - usb_mode : The mode used by the phy to connect to the controller. "1" specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. +If a sibling node is compatible "ti,twl4030-bci", then it will find +this device and query it for USB power status. + twl4030-usb { compatible = "ti,twl4030-usb"; interrupts = < 10 4 >; diff --git a/dts/Bindings/usb/usb-ehci.txt b/dts/Bindings/usb/usb-ehci.txt index 0b04fdff9d..a12d6012a4 100644 --- a/dts/Bindings/usb/usb-ehci.txt +++ b/dts/Bindings/usb/usb-ehci.txt @@ -13,6 +13,8 @@ Optional properties: - big-endian-desc : boolean, set this for hcds with big-endian descriptors - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc - needs-reset-on-resume : boolean, set this to force EHCI reset after resume + - has-transaction-translator : boolean, set this if EHCI have a Transaction + Translator built into the root hub. - clocks : a list of phandle + clock specifier pairs - phys : phandle + phy specifier pair - phy-names : "usb" diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt index 80339192c9..d444757c4d 100644 --- a/dts/Bindings/vendor-prefixes.txt +++ b/dts/Bindings/vendor-prefixes.txt @@ -40,6 +40,7 @@ calxeda Calxeda capella Capella Microsystems, Inc cavium Cavium, Inc. cdns Cadence Design Systems Inc. +ceva Ceva, Inc. chipidea Chipidea, Inc chipone ChipOne chipspark ChipSPARK @@ -52,14 +53,17 @@ cnxt Conexant Systems, Inc. cortina Cortina Systems, Inc. cosmic Cosmic Circuits crystalfontz Crystalfontz America, Inc. +cubietech Cubietech, Ltd. dallas Maxim Integrated Products (formerly Dallas Semiconductor) davicom DAVICOM Semiconductor, Inc. +delta Delta Electronics, Inc. denx Denx Software Engineering digi Digi International Inc. digilent Diglent, Inc. dlg Dialog Semiconductor dlink D-Link Corporation dmo Data Modul AG +ea Embedded Artists AB ebv EBV Elektronik edt Emerging Display Technologies elan Elan Microelectronic Corp. @@ -90,9 +94,11 @@ gumstix Gumstix, Inc. gw Gateworks Corporation hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. +hardkernel Hardkernel Co., Ltd himax Himax Technologies, Inc. hisilicon Hisilicon Limited. hit Hitachi Ltd. +hitex Hitex Development Tools honeywell Honeywell hp Hewlett Packard i2se I2SE GmbH @@ -100,6 +106,7 @@ ibm International Business Machines (IBM) idt Integrated Device Technologies, Inc. iom Iomega Corporation img Imagination Technologies Ltd. +ingenic Ingenic Semiconductor innolux Innolux Corporation intel Intel Corporation intercontrol Inter Control Group @@ -107,6 +114,7 @@ isee ISEE 2007 S.L. isil Intersil karo Ka-Ro electronics GmbH keymile Keymile GmbH +kinetic Kinetic Technologies lacie LaCie lantiq Lantiq Semiconductor lenovo Lenovo Group Ltd. @@ -117,6 +125,7 @@ lltc Linear Technology Corporation marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products mediatek MediaTek Inc. +melexis Melexis N.V. merrii Merrii Technology Co., Ltd. micrel Micrel Inc. microchip Microchip Technology Inc. @@ -154,13 +163,16 @@ powervr PowerVR (deprecated, use img) qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc qemu QEMU, a generic and open source machine emulator and virtualizer +qi Qi Hardware qnap QNAP Systems, Inc. radxa Radxa raidsonic RaidSonic Technology GmbH ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International +raspberrypi Raspberry Pi Foundation realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation +richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. rockchip Fuzhou Rockchip Electronics Co., Ltd samsung Samsung Semiconductor @@ -181,6 +193,7 @@ skyworks Skyworks Solutions, Inc. smsc Standard Microsystems Corporation snps Synopsys, Inc. solidrun SolidRun +solomon Solomon Systech Limited sony Sony Corporation spansion Spansion Inc. sprd Spreadtrum Communications Inc. @@ -189,12 +202,14 @@ ste ST-Ericsson stericsson ST-Ericsson synology Synology, Inc. tbs TBS Technologies +tcl Toby Churchill Ltd. thine THine Electronics, Inc. ti Texas Instruments tlm Trusted Logic Mobility toradex Toradex AG toshiba Toshiba Corporation toumaz Toumaz +tplink TP-LINK Technologies Co., Ltd. truly Truly Semiconductors Limited usi Universal Scientific Industrial Co., Ltd. v3 V3 Semiconductor @@ -202,6 +217,7 @@ variscite Variscite Ltd. via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium voipac Voipac Technologies s.r.o. +wexler Wexler winbond Winbond Electronics corp. wlf Wolfson Microelectronics wm Wondermedia Technologies, Inc. @@ -211,3 +227,5 @@ xillybus Xillybus Ltd. xlnx Xilinx zyxel ZyXEL Communications Corp. zarlink Zarlink Semiconductor +zii Zodiac Inflight Innovations +zte ZTE Corp. diff --git a/dts/Bindings/video/exynos-mic.txt b/dts/Bindings/video/exynos-mic.txt new file mode 100644 index 0000000000..0fba2ee644 --- /dev/null +++ b/dts/Bindings/video/exynos-mic.txt @@ -0,0 +1,51 @@ +Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC) + +MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is +not capable to transfer high resoltuion frame data as decon can send. MIC +solves this problem by compressing the frame data by 1/2 before it is +transferred through mipi dsi. The compressed frame data must be uncompressed in +the panel PCB. + +Required properties: +- compatible: value should be "samsung,exynos5433-mic". +- reg: physical base address and length of the MIC registers set and system + register of mic. +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. +- clock-names: list of clock names sorted in the same order as the clocks + property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0". +- samsung,disp-syscon: the reference node for syscon for DISP block. +- ports: contains a port which is connected to decon node and dsi node. + address-cells and size-cells must 1 and 0, respectively. +- port: contains an endpoint node which is connected to the endpoint in the + decon node or dsi node. The reg value must be 0 and 1 respectively. + +Example: +SoC specific DT entry: +mic: mic@13930000 { + compatible = "samsung,exynos5433-mic"; + reg = <0x13930000 0x48>; + clocks = <&cmu_disp CLK_PCLK_MIC0>, + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; + clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; + samsung,disp-syscon = <&syscon_disp>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mic_to_decon: endpoint { + remote-endpoint = <&decon_to_mic>; + }; + }; + + port@1 { + reg = <1>; + mic_to_dsi: endpoint { + remote-endpoint = <&dsi_to_mic>; + }; + }; + }; +}; diff --git a/dts/Bindings/video/exynos5433-decon.txt b/dts/Bindings/video/exynos5433-decon.txt new file mode 100644 index 0000000000..377afbf512 --- /dev/null +++ b/dts/Bindings/video/exynos5433-decon.txt @@ -0,0 +1,65 @@ +Device-Tree bindings for Samsung Exynos SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be "samsung,exynos5433-decon"; +- reg: physical base address and length of the DECON registers set. +- interrupts: should contain a list of all DECON IP block interrupts in the + order: VSYNC, LCD_SYSTEM. The interrupt specifier format + depends on the interrupt controller used. +- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys" + in the same order as they were listed in the interrupts + property. +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. +- clock-names: list of clock names sorted in the same order as the clocks + property. Must contain "aclk_decon", "aclk_smmu_decon0x", + "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk", + "sclk_decon_eclk" +- ports: contains a port which is connected to mic node. address-cells and + size-cells must 1 and 0, respectively. +- port: contains an endpoint node which is connected to the endpoint in the mic + node. The reg value muset be 0. +- i80-if-timings: specify whether the panel which is connected to decon uses + i80 lcd interface or mipi video interface. This node contains + no timing information as that of fimd does. Because there is + no register in decon to specify i80 interface timing value, + it is not needed, but make it remain to use same kind of node + in fimd and exynos7 decon. + +Example: +SoC specific DT entry: +decon: decon@13800000 { + compatible = "samsung,exynos5433-decon"; + reg = <0x13800000 0x2104>; + clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_XIU_DECON0X>, + <&cmu_disp CLK_PCLK_SMMU_DECON0X>, + <&cmu_disp CLK_SCLK_DECON_VCLK>, + <&cmu_disp CLK_SCLK_DECON_ECLK>; + clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", + "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; + interrupt-names = "vsync", "lcd_sys"; + interrupts = <0 202 0>, <0 203 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + decon_to_mic: endpoint { + remote-endpoint = <&mic_to_decon>; + }; + }; + }; +}; + +Board specific DT entry: +&decon { + i80-if-timings { + }; +}; diff --git a/dts/Bindings/video/exynos_dsim.txt b/dts/Bindings/video/exynos_dsim.txt index 802aa7ef64..0be0362706 100644 --- a/dts/Bindings/video/exynos_dsim.txt +++ b/dts/Bindings/video/exynos_dsim.txt @@ -6,17 +6,19 @@ Required properties: "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */ "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ + "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required entry in clock-names - - clock-names: should include "bus_clk"and "pll_clk" entries + - clock-names: should include "bus_clk"and "sclk_mipi" entries + the use of "pll_clk" is deprecated - phys: list of phy specifiers, must contain an entry for each required entry in phy-names - phy-names: should include "dsim" entry - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) - - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock + - samsung,pll-clock-frequency: specifies frequency of the oscillator clock - #address-cells, #size-cells: should be set respectively to <1> and <0> according to DSI host bindings (see MIPI DSI bindings [1]) @@ -30,10 +32,19 @@ Video interfaces: Device node can contain video interface port nodes according to [2]. The following are properties specific to those nodes: - port node: - - reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port; + port node inbound: + - reg: (required) must be 0. + port node outbound: + - reg: (required) must be 1. - endpoint node of DSI port (reg = 1): + endpoint node connected from mic node (reg = 0): + - remote-endpoint: specifies the endpoint in mic node. This node is required + for Exynos5433 mipi dsi. So mic can access to panel node + thoughout this dsi node. + endpoint node connected to panel node (reg = 1): + - remote-endpoint: specifies the endpoint in panel node. This node is + required in all kinds of exynos mipi dsi to represent + the connection between mipi dsi and panel. - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst mode - samsung,esc-clock-frequency: specifies DSI frequency in escape mode @@ -48,7 +59,7 @@ Example: reg = <0x11C80000 0x10000>; interrupts = <0 79 0>; clocks = <&clock 286>, <&clock 143>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; phys = <&mipi_phy 1>; phy-names = "dsim"; vddcore-supply = <&vusb_reg>; @@ -72,7 +83,15 @@ Example: #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + decon_to_mic: endpoint { + remote-endpoint = <&mic_to_decon>; + }; + }; + port@1 { + reg = <1>; dsi_ep: endpoint { reg = <0>; samsung,burst-clock-frequency = <500000000>; diff --git a/dts/Bindings/video/ssd1307fb.txt b/dts/Bindings/video/ssd1307fb.txt index 7a125427ff..d1be78db63 100644 --- a/dts/Bindings/video/ssd1307fb.txt +++ b/dts/Bindings/video/ssd1307fb.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "solomon,fb-". The only supported bus for - now is i2c, and the supported chips are ssd1306 and ssd1307. + now is i2c, and the supported chips are ssd1305, ssd1306 and ssd1307. - reg: Should contain address of the controller on the I2C bus. Most likely 0x3c or 0x3d - pwm: Should contain the pwm to use according to the OF device tree PWM @@ -15,6 +15,16 @@ Required properties: Optional properties: - reset-active-low: Is the reset gpio is active on physical low? + - solomon,segment-no-remap: Display needs normal (non-inverted) data column + to segment mapping + - solomon,com-seq: Display uses sequential COM pin configuration + - solomon,com-lrremap: Display uses left-right COM pin remap + - solomon,com-invdir: Display uses inverted COM pin scan direction + - solomon,com-offset: Number of the COM pin wired to the first display line + - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles. + - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles. + This needs to be the higher, the higher the capacitance + of the OLED's pixels is [0]: Documentation/devicetree/bindings/pwm/pwm.txt @@ -26,3 +36,14 @@ ssd1307: oled@3c { reset-gpios = <&gpio2 7>; reset-active-low; }; + +ssd1306: oled@3c { + compatible = "solomon,ssd1306fb-i2c"; + reg = <0x3c>; + pwms = <&pwm 4 3000>; + reset-gpios = <&gpio2 7>; + reset-active-low; + solomon,com-lrremap; + solomon,com-invdir; + solomon,com-offset = <32>; +}; diff --git a/dts/Bindings/watchdog/digicolor-wdt.txt b/dts/Bindings/watchdog/digicolor-wdt.txt new file mode 100644 index 0000000000..a882967e17 --- /dev/null +++ b/dts/Bindings/watchdog/digicolor-wdt.txt @@ -0,0 +1,25 @@ +Conexant Digicolor SoCs Watchdog timer + +The watchdog functionality in Conexant Digicolor SoCs relies on the so called +"Agent Communication" block. This block includes the eight programmable system +timer counters. The first timer (called "Timer A") is the only one that can be +used as watchdog. + +Required properties: + +- compatible : Should be "cnxt,cx92755-wdt" +- reg : Specifies base physical address and size of the registers +- clocks : phandle; specifies the clock that drives the timer + +Optional properties: + +- timeout-sec : Contains the watchdog timeout in seconds + +Example: + + watchdog@f0000fc0 { + compatible = "cnxt,cx92755-wdt"; + reg = <0xf0000fc0 0x8>; + clocks = <&main_clk>; + timeout-sec = <15>; + }; diff --git a/dts/Bindings/watchdog/omap-wdt.txt b/dts/Bindings/watchdog/omap-wdt.txt index c227970671..1fa20e453a 100644 --- a/dts/Bindings/watchdog/omap-wdt.txt +++ b/dts/Bindings/watchdog/omap-wdt.txt @@ -1,10 +1,11 @@ TI Watchdog Timer (WDT) Controller for OMAP Required properties: -compatible: -- "ti,omap3-wdt" for OMAP3 -- "ti,omap4-wdt" for OMAP4 -- ti,hwmods: Name of the hwmod associated to the WDT +- compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4 +- ti,hwmods : Name of the hwmod associated to the WDT + +Optional properties: +- timeout-sec : default watchdog timeout in seconds Examples: diff --git a/dts/Bindings/watchdog/st_lpc_wdt.txt b/dts/Bindings/watchdog/st_lpc_wdt.txt new file mode 100644 index 0000000000..388c88a012 --- /dev/null +++ b/dts/Bindings/watchdog/st_lpc_wdt.txt @@ -0,0 +1,38 @@ +STMicroelectronics Low Power Controller (LPC) - Watchdog +======================================================== + +LPC currently supports Watchdog OR Real Time Clock functionality. + +[See: ../rtc/rtc-st-lpc.txt for RTC options] + +Required properties + +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc" + "st,stih415-lpc" "st,stid127-lpc" +- reg : LPC registers base address + size +- interrupts : LPC interrupt line number and associated flags +- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) +- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or + ST_LPC_MODE_WDT [1]. One (and only one) mode must be + selected. + +Required properties [watchdog mode] + +- st,syscfg : Phandle to syscfg node used to enable watchdog and configure + CPU reset type. +- timeout-sec : Watchdog timeout in seconds + +Optional properties [watchdog mode] + +- st,warm-reset : If present reset type will be 'warm' - if not it will be cold + +Example: + lpc@fde05000 { + compatible = "st,stih407-lpc"; + reg = <0xfde05000 0x1000>; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + st,syscfg = <&syscfg_core>; + timeout-sec = <120>; + st,lpc-mode = ; + st,warm-reset; + }; diff --git a/dts/include/dt-bindings/clock/bcm-cygnus.h b/dts/include/dt-bindings/clock/bcm-cygnus.h new file mode 100644 index 0000000000..32fbc47508 --- /dev/null +++ b/dts/include/dt-bindings/clock/bcm-cygnus.h @@ -0,0 +1,68 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_BCM_CYGNUS_H +#define _CLOCK_BCM_CYGNUS_H + +/* GENPLL clock ID */ +#define BCM_CYGNUS_GENPLL 0 +#define BCM_CYGNUS_GENPLL_AXI21_CLK 1 +#define BCM_CYGNUS_GENPLL_250MHZ_CLK 2 +#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 3 +#define BCM_CYGNUS_GENPLL_ENET_SW_CLK 4 +#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK 5 +#define BCM_CYGNUS_GENPLL_CAN_CLK 6 + +/* LCPLL0 clock ID */ +#define BCM_CYGNUS_LCPLL0 0 +#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 1 +#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 2 +#define BCM_CYGNUS_LCPLL0_SDIO_CLK 3 +#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 4 +#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 5 +#define BCM_CYGNUS_LCPLL0_CH5_UNUSED 6 + +/* MIPI PLL clock ID */ +#define BCM_CYGNUS_MIPIPLL 0 +#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED 1 +#define BCM_CYGNUS_MIPIPLL_CH1_LCD 2 +#define BCM_CYGNUS_MIPIPLL_CH2_V3D 3 +#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED 4 +#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED 5 +#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED 6 + +/* ASIU clock ID */ +#define BCM_CYGNUS_ASIU_KEYPAD_CLK 0 +#define BCM_CYGNUS_ASIU_ADC_CLK 1 +#define BCM_CYGNUS_ASIU_PWM_CLK 2 + +#endif /* _CLOCK_BCM_CYGNUS_H */ diff --git a/dts/include/dt-bindings/clock/hi6220-clock.h b/dts/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 0000000000..70ee3833a7 --- /dev/null +++ b/dts/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO 2 +#define HI6220_MMC1_PAD 3 +#define HI6220_MMC2_PAD 4 +#define HI6220_MMC0_PAD 5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR 8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M 14 +#define HI6220_150M 15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL 17 +#define HI6220_MMC1_SRC_SEL 18 +#define HI6220_MMC2_SRC_SEL 19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP 21 +#define HI6220_MMC1_SMP 22 +#define HI6220_MMC2_SMP 23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK 1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK 3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK 5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI 9 +#define HI6220_DACODEC_PCLK 10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK 13 +#define HI6220_I2C1_CLK 14 +#define HI6220_I2C2_CLK 15 +#define HI6220_I2C3_CLK 16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL 24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL 28 +#define HI6220_MMC1_SEL 29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL 32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC 34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC 36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC 38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC 40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV 52 +#define HI6220_MMC1_DIV 53 +#define HI6220_MMC2_DIV 54 +#define HI6220_HIFI_DIV 55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK 1 +#define HI6220_G3D_PCLK 2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK 4 +#define HI6220_ADE_CORE 5 +#define HI6220_MED_MMU 6 +#define HI6220_CFG_CSI4PHY 7 +#define HI6220_CFG_CSI2PHY 8 +#define HI6220_ISP_SCLK_GATE 9 +#define HI6220_ISP_SCLK_GATE1 10 +#define HI6220_ADE_CORE_GATE 11 +#define HI6220_CODEC_VPU_GATE 12 +#define HI6220_MED_SYSPLL 13 + +/* mux clocks */ +#define HI6220_1440_1200 14 +#define HI6220_1000_1200 15 +#define HI6220_1000_1440 16 + +/* divider clocks */ +#define HI6220_CODEC_JPEG 17 +#define HI6220_ISP_SCLK_SRC 18 +#define HI6220_ISP_SCLK1 19 +#define HI6220_ADE_CORE_SRC 20 +#define HI6220_ADE_PIX_SRC 21 +#define HI6220_G3D_CLK 22 +#define HI6220_CODEC_VPU_SRC 23 + +#define HI6220_MEDIA_NR_CLKS 24 + +/* clk in Hi6220 power controller */ +/* gate clocks */ +#define HI6220_PLL_GPU_GATE 1 +#define HI6220_PLL1_DDR_GATE 2 +#define HI6220_PLL_DDR_GATE 3 +#define HI6220_PLL_MEDIA_GATE 4 +#define HI6220_PLL0_BBP_GATE 5 + +/* divider clocks */ +#define HI6220_DDRC_SRC 6 +#define HI6220_DDRC_AXI1 7 + +#define HI6220_POWER_NR_CLKS 8 +#endif diff --git a/dts/include/dt-bindings/clock/imx7d-clock.h b/dts/include/dt-bindings/clock/imx7d-clock.h new file mode 100644 index 0000000000..728df28b00 --- /dev/null +++ b/dts/include/dt-bindings/clock/imx7d-clock.h @@ -0,0 +1,450 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7D_H +#define __DT_BINDINGS_CLOCK_IMX7D_H + +#define IMX7D_OSC_24M_CLK 0 +#define IMX7D_PLL_ARM_MAIN 1 +#define IMX7D_PLL_ARM_MAIN_CLK 2 +#define IMX7D_PLL_ARM_MAIN_SRC 3 +#define IMX7D_PLL_ARM_MAIN_BYPASS 4 +#define IMX7D_PLL_SYS_MAIN 5 +#define IMX7D_PLL_SYS_MAIN_CLK 6 +#define IMX7D_PLL_SYS_MAIN_SRC 7 +#define IMX7D_PLL_SYS_MAIN_BYPASS 8 +#define IMX7D_PLL_SYS_MAIN_480M 9 +#define IMX7D_PLL_SYS_MAIN_240M 10 +#define IMX7D_PLL_SYS_MAIN_120M 11 +#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 +#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 +#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 +#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 +#define IMX7D_PLL_SYS_PFD0_196M 16 +#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 +#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 +#define IMX7D_PLL_SYS_PFD1_166M 19 +#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 +#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 +#define IMX7D_PLL_SYS_PFD2_135M 22 +#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 +#define IMX7D_PLL_SYS_PFD3_CLK 24 +#define IMX7D_PLL_SYS_PFD4_CLK 25 +#define IMX7D_PLL_SYS_PFD5_CLK 26 +#define IMX7D_PLL_SYS_PFD6_CLK 27 +#define IMX7D_PLL_SYS_PFD7_CLK 28 +#define IMX7D_PLL_ENET_MAIN 29 +#define IMX7D_PLL_ENET_MAIN_CLK 30 +#define IMX7D_PLL_ENET_MAIN_SRC 31 +#define IMX7D_PLL_ENET_MAIN_BYPASS 32 +#define IMX7D_PLL_ENET_MAIN_500M 33 +#define IMX7D_PLL_ENET_MAIN_250M 34 +#define IMX7D_PLL_ENET_MAIN_125M 35 +#define IMX7D_PLL_ENET_MAIN_100M 36 +#define IMX7D_PLL_ENET_MAIN_50M 37 +#define IMX7D_PLL_ENET_MAIN_40M 38 +#define IMX7D_PLL_ENET_MAIN_25M 39 +#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 +#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 +#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 +#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 +#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 +#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 +#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 +#define IMX7D_PLL_DRAM_MAIN 47 +#define IMX7D_PLL_DRAM_MAIN_CLK 48 +#define IMX7D_PLL_DRAM_MAIN_SRC 49 +#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 +#define IMX7D_PLL_DRAM_MAIN_533M 51 +#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 +#define IMX7D_PLL_AUDIO_MAIN 53 +#define IMX7D_PLL_AUDIO_MAIN_CLK 54 +#define IMX7D_PLL_AUDIO_MAIN_SRC 55 +#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 +#define IMX7D_PLL_VIDEO_MAIN_CLK 57 +#define IMX7D_PLL_VIDEO_MAIN 58 +#define IMX7D_PLL_VIDEO_MAIN_SRC 59 +#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 +#define IMX7D_USB_MAIN_480M_CLK 61 +#define IMX7D_ARM_A7_ROOT_CLK 62 +#define IMX7D_ARM_A7_ROOT_SRC 63 +#define IMX7D_ARM_A7_ROOT_CG 64 +#define IMX7D_ARM_A7_ROOT_DIV 65 +#define IMX7D_ARM_M4_ROOT_CLK 66 +#define IMX7D_ARM_M4_ROOT_SRC 67 +#define IMX7D_ARM_M4_ROOT_CG 68 +#define IMX7D_ARM_M4_ROOT_DIV 69 +#define IMX7D_ARM_M0_ROOT_CLK 70 +#define IMX7D_ARM_M0_ROOT_SRC 71 +#define IMX7D_ARM_M0_ROOT_CG 72 +#define IMX7D_ARM_M0_ROOT_DIV 73 +#define IMX7D_MAIN_AXI_ROOT_CLK 74 +#define IMX7D_MAIN_AXI_ROOT_SRC 75 +#define IMX7D_MAIN_AXI_ROOT_CG 76 +#define IMX7D_MAIN_AXI_ROOT_DIV 77 +#define IMX7D_DISP_AXI_ROOT_CLK 78 +#define IMX7D_DISP_AXI_ROOT_SRC 79 +#define IMX7D_DISP_AXI_ROOT_CG 80 +#define IMX7D_DISP_AXI_ROOT_DIV 81 +#define IMX7D_ENET_AXI_ROOT_CLK 82 +#define IMX7D_ENET_AXI_ROOT_SRC 83 +#define IMX7D_ENET_AXI_ROOT_CG 84 +#define IMX7D_ENET_AXI_ROOT_DIV 85 +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 +#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 +#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 +#define IMX7D_AHB_CHANNEL_ROOT_CG 92 +#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 +#define IMX7D_DRAM_PHYM_ROOT_CLK 94 +#define IMX7D_DRAM_PHYM_ROOT_SRC 95 +#define IMX7D_DRAM_PHYM_ROOT_CG 96 +#define IMX7D_DRAM_PHYM_ROOT_DIV 97 +#define IMX7D_DRAM_ROOT_CLK 98 +#define IMX7D_DRAM_ROOT_SRC 99 +#define IMX7D_DRAM_ROOT_CG 100 +#define IMX7D_DRAM_ROOT_DIV 101 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 +#define IMX7D_DRAM_ALT_ROOT_CLK 106 +#define IMX7D_DRAM_ALT_ROOT_SRC 107 +#define IMX7D_DRAM_ALT_ROOT_CG 108 +#define IMX7D_DRAM_ALT_ROOT_DIV 109 +#define IMX7D_USB_HSIC_ROOT_CLK 110 +#define IMX7D_USB_HSIC_ROOT_SRC 111 +#define IMX7D_USB_HSIC_ROOT_CG 112 +#define IMX7D_USB_HSIC_ROOT_DIV 113 +#define IMX7D_PCIE_CTRL_ROOT_CLK 114 +#define IMX7D_PCIE_CTRL_ROOT_SRC 115 +#define IMX7D_PCIE_CTRL_ROOT_CG 116 +#define IMX7D_PCIE_CTRL_ROOT_DIV 117 +#define IMX7D_PCIE_PHY_ROOT_CLK 118 +#define IMX7D_PCIE_PHY_ROOT_SRC 119 +#define IMX7D_PCIE_PHY_ROOT_CG 120 +#define IMX7D_PCIE_PHY_ROOT_DIV 121 +#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 +#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 +#define IMX7D_EPDC_PIXEL_ROOT_CG 124 +#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 +#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 +#define IMX7D_MIPI_DSI_ROOT_CLK 130 +#define IMX7D_MIPI_DSI_ROOT_SRC 131 +#define IMX7D_MIPI_DSI_ROOT_CG 132 +#define IMX7D_MIPI_DSI_ROOT_DIV 133 +#define IMX7D_MIPI_CSI_ROOT_CLK 134 +#define IMX7D_MIPI_CSI_ROOT_SRC 135 +#define IMX7D_MIPI_CSI_ROOT_CG 136 +#define IMX7D_MIPI_CSI_ROOT_DIV 137 +#define IMX7D_MIPI_DPHY_ROOT_CLK 138 +#define IMX7D_MIPI_DPHY_ROOT_SRC 139 +#define IMX7D_MIPI_DPHY_ROOT_CG 140 +#define IMX7D_MIPI_DPHY_ROOT_DIV 141 +#define IMX7D_SAI1_ROOT_CLK 142 +#define IMX7D_SAI1_ROOT_SRC 143 +#define IMX7D_SAI1_ROOT_CG 144 +#define IMX7D_SAI1_ROOT_DIV 145 +#define IMX7D_SAI2_ROOT_CLK 146 +#define IMX7D_SAI2_ROOT_SRC 147 +#define IMX7D_SAI2_ROOT_CG 148 +#define IMX7D_SAI2_ROOT_DIV 149 +#define IMX7D_SAI3_ROOT_CLK 150 +#define IMX7D_SAI3_ROOT_SRC 151 +#define IMX7D_SAI3_ROOT_CG 152 +#define IMX7D_SAI3_ROOT_DIV 153 +#define IMX7D_SPDIF_ROOT_CLK 154 +#define IMX7D_SPDIF_ROOT_SRC 155 +#define IMX7D_SPDIF_ROOT_CG 156 +#define IMX7D_SPDIF_ROOT_DIV 157 +#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_REF_ROOT_SRC 159 +#define IMX7D_ENET1_REF_ROOT_CG 160 +#define IMX7D_ENET1_REF_ROOT_DIV 161 +#define IMX7D_ENET1_TIME_ROOT_CLK 162 +#define IMX7D_ENET1_TIME_ROOT_SRC 163 +#define IMX7D_ENET1_TIME_ROOT_CG 164 +#define IMX7D_ENET1_TIME_ROOT_DIV 165 +#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_REF_ROOT_SRC 167 +#define IMX7D_ENET2_REF_ROOT_CG 168 +#define IMX7D_ENET2_REF_ROOT_DIV 169 +#define IMX7D_ENET2_TIME_ROOT_CLK 170 +#define IMX7D_ENET2_TIME_ROOT_SRC 171 +#define IMX7D_ENET2_TIME_ROOT_CG 172 +#define IMX7D_ENET2_TIME_ROOT_DIV 173 +#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 +#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 +#define IMX7D_ENET_PHY_REF_ROOT_CG 176 +#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 +#define IMX7D_EIM_ROOT_CLK 178 +#define IMX7D_EIM_ROOT_SRC 179 +#define IMX7D_EIM_ROOT_CG 180 +#define IMX7D_EIM_ROOT_DIV 181 +#define IMX7D_NAND_ROOT_CLK 182 +#define IMX7D_NAND_ROOT_SRC 183 +#define IMX7D_NAND_ROOT_CG 184 +#define IMX7D_NAND_ROOT_DIV 185 +#define IMX7D_QSPI_ROOT_CLK 186 +#define IMX7D_QSPI_ROOT_SRC 187 +#define IMX7D_QSPI_ROOT_CG 188 +#define IMX7D_QSPI_ROOT_DIV 189 +#define IMX7D_USDHC1_ROOT_CLK 190 +#define IMX7D_USDHC1_ROOT_SRC 191 +#define IMX7D_USDHC1_ROOT_CG 192 +#define IMX7D_USDHC1_ROOT_DIV 193 +#define IMX7D_USDHC2_ROOT_CLK 194 +#define IMX7D_USDHC2_ROOT_SRC 195 +#define IMX7D_USDHC2_ROOT_CG 196 +#define IMX7D_USDHC2_ROOT_DIV 197 +#define IMX7D_USDHC3_ROOT_CLK 198 +#define IMX7D_USDHC3_ROOT_SRC 199 +#define IMX7D_USDHC3_ROOT_CG 200 +#define IMX7D_USDHC3_ROOT_DIV 201 +#define IMX7D_CAN1_ROOT_CLK 202 +#define IMX7D_CAN1_ROOT_SRC 203 +#define IMX7D_CAN1_ROOT_CG 204 +#define IMX7D_CAN1_ROOT_DIV 205 +#define IMX7D_CAN2_ROOT_CLK 206 +#define IMX7D_CAN2_ROOT_SRC 207 +#define IMX7D_CAN2_ROOT_CG 208 +#define IMX7D_CAN2_ROOT_DIV 209 +#define IMX7D_I2C1_ROOT_CLK 210 +#define IMX7D_I2C1_ROOT_SRC 211 +#define IMX7D_I2C1_ROOT_CG 212 +#define IMX7D_I2C1_ROOT_DIV 213 +#define IMX7D_I2C2_ROOT_CLK 214 +#define IMX7D_I2C2_ROOT_SRC 215 +#define IMX7D_I2C2_ROOT_CG 216 +#define IMX7D_I2C2_ROOT_DIV 217 +#define IMX7D_I2C3_ROOT_CLK 218 +#define IMX7D_I2C3_ROOT_SRC 219 +#define IMX7D_I2C3_ROOT_CG 220 +#define IMX7D_I2C3_ROOT_DIV 221 +#define IMX7D_I2C4_ROOT_CLK 222 +#define IMX7D_I2C4_ROOT_SRC 223 +#define IMX7D_I2C4_ROOT_CG 224 +#define IMX7D_I2C4_ROOT_DIV 225 +#define IMX7D_UART1_ROOT_CLK 226 +#define IMX7D_UART1_ROOT_SRC 227 +#define IMX7D_UART1_ROOT_CG 228 +#define IMX7D_UART1_ROOT_DIV 229 +#define IMX7D_UART2_ROOT_CLK 230 +#define IMX7D_UART2_ROOT_SRC 231 +#define IMX7D_UART2_ROOT_CG 232 +#define IMX7D_UART2_ROOT_DIV 233 +#define IMX7D_UART3_ROOT_CLK 234 +#define IMX7D_UART3_ROOT_SRC 235 +#define IMX7D_UART3_ROOT_CG 236 +#define IMX7D_UART3_ROOT_DIV 237 +#define IMX7D_UART4_ROOT_CLK 238 +#define IMX7D_UART4_ROOT_SRC 239 +#define IMX7D_UART4_ROOT_CG 240 +#define IMX7D_UART4_ROOT_DIV 241 +#define IMX7D_UART5_ROOT_CLK 242 +#define IMX7D_UART5_ROOT_SRC 243 +#define IMX7D_UART5_ROOT_CG 244 +#define IMX7D_UART5_ROOT_DIV 245 +#define IMX7D_UART6_ROOT_CLK 246 +#define IMX7D_UART6_ROOT_SRC 247 +#define IMX7D_UART6_ROOT_CG 248 +#define IMX7D_UART6_ROOT_DIV 249 +#define IMX7D_UART7_ROOT_CLK 250 +#define IMX7D_UART7_ROOT_SRC 251 +#define IMX7D_UART7_ROOT_CG 252 +#define IMX7D_UART7_ROOT_DIV 253 +#define IMX7D_ECSPI1_ROOT_CLK 254 +#define IMX7D_ECSPI1_ROOT_SRC 255 +#define IMX7D_ECSPI1_ROOT_CG 256 +#define IMX7D_ECSPI1_ROOT_DIV 257 +#define IMX7D_ECSPI2_ROOT_CLK 258 +#define IMX7D_ECSPI2_ROOT_SRC 259 +#define IMX7D_ECSPI2_ROOT_CG 260 +#define IMX7D_ECSPI2_ROOT_DIV 261 +#define IMX7D_ECSPI3_ROOT_CLK 262 +#define IMX7D_ECSPI3_ROOT_SRC 263 +#define IMX7D_ECSPI3_ROOT_CG 264 +#define IMX7D_ECSPI3_ROOT_DIV 265 +#define IMX7D_ECSPI4_ROOT_CLK 266 +#define IMX7D_ECSPI4_ROOT_SRC 267 +#define IMX7D_ECSPI4_ROOT_CG 268 +#define IMX7D_ECSPI4_ROOT_DIV 269 +#define IMX7D_PWM1_ROOT_CLK 270 +#define IMX7D_PWM1_ROOT_SRC 271 +#define IMX7D_PWM1_ROOT_CG 272 +#define IMX7D_PWM1_ROOT_DIV 273 +#define IMX7D_PWM2_ROOT_CLK 274 +#define IMX7D_PWM2_ROOT_SRC 275 +#define IMX7D_PWM2_ROOT_CG 276 +#define IMX7D_PWM2_ROOT_DIV 277 +#define IMX7D_PWM3_ROOT_CLK 278 +#define IMX7D_PWM3_ROOT_SRC 279 +#define IMX7D_PWM3_ROOT_CG 280 +#define IMX7D_PWM3_ROOT_DIV 281 +#define IMX7D_PWM4_ROOT_CLK 282 +#define IMX7D_PWM4_ROOT_SRC 283 +#define IMX7D_PWM4_ROOT_CG 284 +#define IMX7D_PWM4_ROOT_DIV 285 +#define IMX7D_FLEXTIMER1_ROOT_CLK 286 +#define IMX7D_FLEXTIMER1_ROOT_SRC 287 +#define IMX7D_FLEXTIMER1_ROOT_CG 288 +#define IMX7D_FLEXTIMER1_ROOT_DIV 289 +#define IMX7D_FLEXTIMER2_ROOT_CLK 290 +#define IMX7D_FLEXTIMER2_ROOT_SRC 291 +#define IMX7D_FLEXTIMER2_ROOT_CG 292 +#define IMX7D_FLEXTIMER2_ROOT_DIV 293 +#define IMX7D_SIM1_ROOT_CLK 294 +#define IMX7D_SIM1_ROOT_SRC 295 +#define IMX7D_SIM1_ROOT_CG 296 +#define IMX7D_SIM1_ROOT_DIV 297 +#define IMX7D_SIM2_ROOT_CLK 298 +#define IMX7D_SIM2_ROOT_SRC 299 +#define IMX7D_SIM2_ROOT_CG 300 +#define IMX7D_SIM2_ROOT_DIV 301 +#define IMX7D_GPT1_ROOT_CLK 302 +#define IMX7D_GPT1_ROOT_SRC 303 +#define IMX7D_GPT1_ROOT_CG 304 +#define IMX7D_GPT1_ROOT_DIV 305 +#define IMX7D_GPT2_ROOT_CLK 306 +#define IMX7D_GPT2_ROOT_SRC 307 +#define IMX7D_GPT2_ROOT_CG 308 +#define IMX7D_GPT2_ROOT_DIV 309 +#define IMX7D_GPT3_ROOT_CLK 310 +#define IMX7D_GPT3_ROOT_SRC 311 +#define IMX7D_GPT3_ROOT_CG 312 +#define IMX7D_GPT3_ROOT_DIV 313 +#define IMX7D_GPT4_ROOT_CLK 314 +#define IMX7D_GPT4_ROOT_SRC 315 +#define IMX7D_GPT4_ROOT_CG 316 +#define IMX7D_GPT4_ROOT_DIV 317 +#define IMX7D_TRACE_ROOT_CLK 318 +#define IMX7D_TRACE_ROOT_SRC 319 +#define IMX7D_TRACE_ROOT_CG 320 +#define IMX7D_TRACE_ROOT_DIV 321 +#define IMX7D_WDOG1_ROOT_CLK 322 +#define IMX7D_WDOG_ROOT_SRC 323 +#define IMX7D_WDOG_ROOT_CG 324 +#define IMX7D_WDOG_ROOT_DIV 325 +#define IMX7D_CSI_MCLK_ROOT_CLK 326 +#define IMX7D_CSI_MCLK_ROOT_SRC 327 +#define IMX7D_CSI_MCLK_ROOT_CG 328 +#define IMX7D_CSI_MCLK_ROOT_DIV 329 +#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 +#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 +#define IMX7D_AUDIO_MCLK_ROOT_CG 332 +#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 +#define IMX7D_WRCLK_ROOT_CLK 334 +#define IMX7D_WRCLK_ROOT_SRC 335 +#define IMX7D_WRCLK_ROOT_CG 336 +#define IMX7D_WRCLK_ROOT_DIV 337 +#define IMX7D_CLKO1_ROOT_SRC 338 +#define IMX7D_CLKO1_ROOT_CG 339 +#define IMX7D_CLKO1_ROOT_DIV 340 +#define IMX7D_CLKO2_ROOT_SRC 341 +#define IMX7D_CLKO2_ROOT_CG 342 +#define IMX7D_CLKO2_ROOT_DIV 343 +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 +#define IMX7D_SAI1_ROOT_PRE_DIV 357 +#define IMX7D_SAI2_ROOT_PRE_DIV 358 +#define IMX7D_SAI3_ROOT_PRE_DIV 359 +#define IMX7D_SPDIF_ROOT_PRE_DIV 360 +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 +#define IMX7D_EIM_ROOT_PRE_DIV 366 +#define IMX7D_NAND_ROOT_PRE_DIV 367 +#define IMX7D_QSPI_ROOT_PRE_DIV 368 +#define IMX7D_USDHC1_ROOT_PRE_DIV 369 +#define IMX7D_USDHC2_ROOT_PRE_DIV 370 +#define IMX7D_USDHC3_ROOT_PRE_DIV 371 +#define IMX7D_CAN1_ROOT_PRE_DIV 372 +#define IMX7D_CAN2_ROOT_PRE_DIV 373 +#define IMX7D_I2C1_ROOT_PRE_DIV 374 +#define IMX7D_I2C2_ROOT_PRE_DIV 375 +#define IMX7D_I2C3_ROOT_PRE_DIV 376 +#define IMX7D_I2C4_ROOT_PRE_DIV 377 +#define IMX7D_UART1_ROOT_PRE_DIV 378 +#define IMX7D_UART2_ROOT_PRE_DIV 379 +#define IMX7D_UART3_ROOT_PRE_DIV 380 +#define IMX7D_UART4_ROOT_PRE_DIV 381 +#define IMX7D_UART5_ROOT_PRE_DIV 382 +#define IMX7D_UART6_ROOT_PRE_DIV 383 +#define IMX7D_UART7_ROOT_PRE_DIV 384 +#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 +#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 +#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 +#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 +#define IMX7D_PWM1_ROOT_PRE_DIV 389 +#define IMX7D_PWM2_ROOT_PRE_DIV 390 +#define IMX7D_PWM3_ROOT_PRE_DIV 391 +#define IMX7D_PWM4_ROOT_PRE_DIV 392 +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 +#define IMX7D_SIM1_ROOT_PRE_DIV 395 +#define IMX7D_SIM2_ROOT_PRE_DIV 396 +#define IMX7D_GPT1_ROOT_PRE_DIV 397 +#define IMX7D_GPT2_ROOT_PRE_DIV 398 +#define IMX7D_GPT3_ROOT_PRE_DIV 399 +#define IMX7D_GPT4_ROOT_PRE_DIV 400 +#define IMX7D_TRACE_ROOT_PRE_DIV 401 +#define IMX7D_WDOG_ROOT_PRE_DIV 402 +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 +#define IMX7D_WRCLK_ROOT_PRE_DIV 405 +#define IMX7D_CLKO1_ROOT_PRE_DIV 406 +#define IMX7D_CLKO2_ROOT_PRE_DIV 407 +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 +#define IMX7D_LVDS1_IN_CLK 410 +#define IMX7D_LVDS1_OUT_SEL 411 +#define IMX7D_LVDS1_OUT_CLK 412 +#define IMX7D_CLK_DUMMY 413 +#define IMX7D_GPT_3M_CLK 414 +#define IMX7D_OCRAM_CLK 415 +#define IMX7D_OCRAM_S_CLK 416 +#define IMX7D_WDOG2_ROOT_CLK 417 +#define IMX7D_WDOG3_ROOT_CLK 418 +#define IMX7D_WDOG4_ROOT_CLK 419 +#define IMX7D_SDMA_CORE_CLK 420 +#define IMX7D_USB1_MAIN_480M_CLK 421 +#define IMX7D_USB_CTRL_CLK 422 +#define IMX7D_USB_PHY1_CLK 423 +#define IMX7D_USB_PHY2_CLK 424 +#define IMX7D_IPG_ROOT_CLK 425 +#define IMX7D_SAI1_IPG_CLK 426 +#define IMX7D_SAI2_IPG_CLK 427 +#define IMX7D_SAI3_IPG_CLK 428 +#define IMX7D_PLL_AUDIO_TEST_DIV 429 +#define IMX7D_PLL_AUDIO_POST_DIV 430 +#define IMX7D_PLL_VIDEO_TEST_DIV 431 +#define IMX7D_PLL_VIDEO_POST_DIV 432 +#define IMX7D_MU_ROOT_CLK 433 +#define IMX7D_SEMA4_HS_ROOT_CLK 434 +#define IMX7D_PLL_DRAM_TEST_DIV 435 +#define IMX7D_CLK_END 436 +#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/dts/include/dt-bindings/clock/jz4740-cgu.h b/dts/include/dt-bindings/clock/jz4740-cgu.h new file mode 100644 index 0000000000..43153d3e9b --- /dev/null +++ b/dts/include/dt-bindings/clock/jz4740-cgu.h @@ -0,0 +1,37 @@ +/* + * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4740 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ + +#define JZ4740_CLK_EXT 0 +#define JZ4740_CLK_RTC 1 +#define JZ4740_CLK_PLL 2 +#define JZ4740_CLK_PLL_HALF 3 +#define JZ4740_CLK_CCLK 4 +#define JZ4740_CLK_HCLK 5 +#define JZ4740_CLK_PCLK 6 +#define JZ4740_CLK_MCLK 7 +#define JZ4740_CLK_LCD 8 +#define JZ4740_CLK_LCD_PCLK 9 +#define JZ4740_CLK_I2S 10 +#define JZ4740_CLK_SPI 11 +#define JZ4740_CLK_MMC 12 +#define JZ4740_CLK_UHC 13 +#define JZ4740_CLK_UDC 14 +#define JZ4740_CLK_UART0 15 +#define JZ4740_CLK_UART1 16 +#define JZ4740_CLK_DMA 17 +#define JZ4740_CLK_IPU 18 +#define JZ4740_CLK_ADC 19 +#define JZ4740_CLK_I2C 20 +#define JZ4740_CLK_AIC 21 + +#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ diff --git a/dts/include/dt-bindings/clock/jz4780-cgu.h b/dts/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 0000000000..467165e3cf --- /dev/null +++ b/dts/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,88 @@ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/dts/include/dt-bindings/clock/lpc18xx-ccu.h b/dts/include/dt-bindings/clock/lpc18xx-ccu.h new file mode 100644 index 0000000000..bbfe00b6ab --- /dev/null +++ b/dts/include/dt-bindings/clock/lpc18xx-ccu.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/* Clock Control Unit 1 (CCU1) clock offsets */ +#define CLK_APB3_BUS 0x100 +#define CLK_APB3_I2C1 0x108 +#define CLK_APB3_DAC 0x110 +#define CLK_APB3_ADC0 0x118 +#define CLK_APB3_ADC1 0x120 +#define CLK_APB3_CAN0 0x128 +#define CLK_APB1_BUS 0x200 +#define CLK_APB1_MOTOCON_PWM 0x208 +#define CLK_APB1_I2C0 0x210 +#define CLK_APB1_I2S 0x218 +#define CLK_APB1_CAN1 0x220 +#define CLK_SPIFI 0x300 +#define CLK_CPU_BUS 0x400 +#define CLK_CPU_SPIFI 0x408 +#define CLK_CPU_GPIO 0x410 +#define CLK_CPU_LCD 0x418 +#define CLK_CPU_ETHERNET 0x420 +#define CLK_CPU_USB0 0x428 +#define CLK_CPU_EMC 0x430 +#define CLK_CPU_SDIO 0x438 +#define CLK_CPU_DMA 0x440 +#define CLK_CPU_CORE 0x448 +#define CLK_CPU_SCT 0x468 +#define CLK_CPU_USB1 0x470 +#define CLK_CPU_EMCDIV 0x478 +#define CLK_CPU_FLASHA 0x480 +#define CLK_CPU_FLASHB 0x488 +#define CLK_CPU_M0APP 0x490 +#define CLK_CPU_ADCHS 0x498 +#define CLK_CPU_EEPROM 0x4a0 +#define CLK_CPU_WWDT 0x500 +#define CLK_CPU_UART0 0x508 +#define CLK_CPU_UART1 0x510 +#define CLK_CPU_SSP0 0x518 +#define CLK_CPU_TIMER0 0x520 +#define CLK_CPU_TIMER1 0x528 +#define CLK_CPU_SCU 0x530 +#define CLK_CPU_CREG 0x538 +#define CLK_CPU_RITIMER 0x600 +#define CLK_CPU_UART2 0x608 +#define CLK_CPU_UART3 0x610 +#define CLK_CPU_TIMER2 0x618 +#define CLK_CPU_TIMER3 0x620 +#define CLK_CPU_SSP1 0x628 +#define CLK_CPU_QEI 0x630 +#define CLK_PERIPH_BUS 0x700 +#define CLK_PERIPH_CORE 0x710 +#define CLK_PERIPH_SGPIO 0x718 +#define CLK_USB0 0x800 +#define CLK_USB1 0x900 +#define CLK_SPI 0xA00 +#define CLK_ADCHS 0xB00 + +/* Clock Control Unit 2 (CCU2) clock offsets */ +#define CLK_AUDIO 0x100 +#define CLK_APB2_UART3 0x200 +#define CLK_APB2_UART2 0x300 +#define CLK_APB0_UART1 0x400 +#define CLK_APB0_UART0 0x500 +#define CLK_APB2_SSP1 0x600 +#define CLK_APB0_SSP0 0x700 +#define CLK_SDIO 0x800 diff --git a/dts/include/dt-bindings/clock/lpc18xx-cgu.h b/dts/include/dt-bindings/clock/lpc18xx-cgu.h new file mode 100644 index 0000000000..6e57c6d2ca --- /dev/null +++ b/dts/include/dt-bindings/clock/lpc18xx-cgu.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/* LPC18xx/43xx base clock ids */ +#define BASE_SAFE_CLK 0 +#define BASE_USB0_CLK 1 +#define BASE_PERIPH_CLK 2 +#define BASE_USB1_CLK 3 +#define BASE_CPU_CLK 4 +#define BASE_SPIFI_CLK 5 +#define BASE_SPI_CLK 6 +#define BASE_PHY_RX_CLK 7 +#define BASE_PHY_TX_CLK 8 +#define BASE_APB1_CLK 9 +#define BASE_APB3_CLK 10 +#define BASE_LCD_CLK 11 +#define BASE_ADCHS_CLK 12 +#define BASE_SDIO_CLK 13 +#define BASE_SSP0_CLK 14 +#define BASE_SSP1_CLK 15 +#define BASE_UART0_CLK 16 +#define BASE_UART1_CLK 17 +#define BASE_UART2_CLK 18 +#define BASE_UART3_CLK 19 +#define BASE_OUT_CLK 20 +#define BASE_RES1_CLK 21 +#define BASE_RES2_CLK 22 +#define BASE_RES3_CLK 23 +#define BASE_RES4_CLK 24 +#define BASE_AUDIO_CLK 25 +#define BASE_CGU_OUT0_CLK 26 +#define BASE_CGU_OUT1_CLK 27 +#define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1) diff --git a/dts/include/dt-bindings/clock/marvell,mmp2.h b/dts/include/dt-bindings/clock/marvell,mmp2.h index 591f7fba89..7a510384a8 100644 --- a/dts/include/dt-bindings/clock/marvell,mmp2.h +++ b/dts/include/dt-bindings/clock/marvell,mmp2.h @@ -48,6 +48,7 @@ #define MMP2_CLK_SSP1 78 #define MMP2_CLK_SSP2 79 #define MMP2_CLK_SSP3 80 +#define MMP2_CLK_TIMER 81 /* axi periphrals */ #define MMP2_CLK_SDH0 101 diff --git a/dts/include/dt-bindings/clock/marvell,pxa168.h b/dts/include/dt-bindings/clock/marvell,pxa168.h index 79630b9d74..3e45bdfe1a 100644 --- a/dts/include/dt-bindings/clock/marvell,pxa168.h +++ b/dts/include/dt-bindings/clock/marvell,pxa168.h @@ -18,7 +18,9 @@ #define PXA168_CLK_PLL1_13_1_5 18 #define PXA168_CLK_PLL1_2_1_5 19 #define PXA168_CLK_PLL1_3_16 20 +#define PXA168_CLK_PLL1_192 21 #define PXA168_CLK_UART_PLL 27 +#define PXA168_CLK_USB_PLL 28 /* apb periphrals */ #define PXA168_CLK_TWSI0 60 @@ -40,6 +42,7 @@ #define PXA168_CLK_SSP2 76 #define PXA168_CLK_SSP3 77 #define PXA168_CLK_SSP4 78 +#define PXA168_CLK_TIMER 79 /* axi periphrals */ #define PXA168_CLK_DFC 100 diff --git a/dts/include/dt-bindings/clock/marvell,pxa1928.h b/dts/include/dt-bindings/clock/marvell,pxa1928.h new file mode 100644 index 0000000000..d4f2e18919 --- /dev/null +++ b/dts/include/dt-bindings/clock/marvell,pxa1928.h @@ -0,0 +1,57 @@ +#ifndef __DTS_MARVELL_PXA1928_CLOCK_H +#define __DTS_MARVELL_PXA1928_CLOCK_H + +/* + * Clock ID values here correspond to the control register offset/4. + */ + +/* apb peripherals */ +#define PXA1928_CLK_RTC 0x00 +#define PXA1928_CLK_TWSI0 0x01 +#define PXA1928_CLK_TWSI1 0x02 +#define PXA1928_CLK_TWSI2 0x03 +#define PXA1928_CLK_TWSI3 0x04 +#define PXA1928_CLK_OWIRE 0x05 +#define PXA1928_CLK_KPC 0x06 +#define PXA1928_CLK_TB_ROTARY 0x07 +#define PXA1928_CLK_SW_JTAG 0x08 +#define PXA1928_CLK_TIMER1 0x09 +#define PXA1928_CLK_UART0 0x0b +#define PXA1928_CLK_UART1 0x0c +#define PXA1928_CLK_UART2 0x0d +#define PXA1928_CLK_GPIO 0x0e +#define PXA1928_CLK_PWM0 0x0f +#define PXA1928_CLK_PWM1 0x10 +#define PXA1928_CLK_PWM2 0x11 +#define PXA1928_CLK_PWM3 0x12 +#define PXA1928_CLK_SSP0 0x13 +#define PXA1928_CLK_SSP1 0x14 +#define PXA1928_CLK_SSP2 0x15 + +#define PXA1928_CLK_TWSI4 0x1f +#define PXA1928_CLK_TWSI5 0x20 +#define PXA1928_CLK_UART3 0x22 +#define PXA1928_CLK_THSENS_GLOB 0x24 +#define PXA1928_CLK_THSENS_CPU 0x26 +#define PXA1928_CLK_THSENS_VPU 0x27 +#define PXA1928_CLK_THSENS_GC 0x28 +#define PXA1928_APBC_NR_CLKS 0x30 + + +/* axi peripherals */ +#define PXA1928_CLK_SDH0 0x15 +#define PXA1928_CLK_SDH1 0x16 +#define PXA1928_CLK_USB 0x17 +#define PXA1928_CLK_NAND 0x18 +#define PXA1928_CLK_DMA 0x19 + +#define PXA1928_CLK_SDH2 0x3a +#define PXA1928_CLK_SDH3 0x3b +#define PXA1928_CLK_HSIC 0x3e +#define PXA1928_CLK_SDH4 0x57 +#define PXA1928_CLK_GC3D 0x5d +#define PXA1928_CLK_GC2D 0x5f + +#define PXA1928_APMU_NR_CLKS 0x60 + +#endif diff --git a/dts/include/dt-bindings/clock/marvell,pxa910.h b/dts/include/dt-bindings/clock/marvell,pxa910.h index 719cffb2be..135082a0b6 100644 --- a/dts/include/dt-bindings/clock/marvell,pxa910.h +++ b/dts/include/dt-bindings/clock/marvell,pxa910.h @@ -18,7 +18,9 @@ #define PXA910_CLK_PLL1_13_1_5 18 #define PXA910_CLK_PLL1_2_1_5 19 #define PXA910_CLK_PLL1_3_16 20 +#define PXA910_CLK_PLL1_192 21 #define PXA910_CLK_UART_PLL 27 +#define PXA910_CLK_USB_PLL 28 /* apb periphrals */ #define PXA910_CLK_TWSI0 60 @@ -37,6 +39,8 @@ #define PXA910_CLK_UART2 73 #define PXA910_CLK_SSP0 74 #define PXA910_CLK_SSP1 75 +#define PXA910_CLK_TIMER0 76 +#define PXA910_CLK_TIMER1 77 /* axi periphrals */ #define PXA910_CLK_DFC 100 diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h new file mode 100644 index 0000000000..bd2720d58e --- /dev/null +++ b/dts/include/dt-bindings/clock/meson8b-clkc.h @@ -0,0 +1,25 @@ +/* + * Meson8b clock tree IDs + */ + +#ifndef __MESON8B_CLKC_H +#define __MESON8B_CLKC_H + +#define CLKID_UNUSED 0 +#define CLKID_XTAL 1 +#define CLKID_PLL_FIXED 2 +#define CLKID_PLL_VID 3 +#define CLKID_PLL_SYS 4 +#define CLKID_FCLK_DIV2 5 +#define CLKID_FCLK_DIV3 6 +#define CLKID_FCLK_DIV4 7 +#define CLKID_FCLK_DIV5 8 +#define CLKID_FCLK_DIV7 9 +#define CLKID_CLK81 10 +#define CLKID_MALI 11 +#define CLKID_CPUCLK 12 +#define CLKID_ZERO 13 + +#define CLK_NR_CLKS (CLKID_ZERO + 1) + +#endif /* __MESON8B_CLKC_H */ diff --git a/dts/include/dt-bindings/clock/mt8135-clk.h b/dts/include/dt-bindings/clock/mt8135-clk.h new file mode 100644 index 0000000000..6dac6c091d --- /dev/null +++ b/dts/include/dt-bindings/clock/mt8135-clk.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MT8135_H +#define _DT_BINDINGS_CLK_MT8135_H + +/* TOPCKGEN */ + +#define CLK_TOP_DSI0_LNTC_DSICLK 1 +#define CLK_TOP_HDMITX_CLKDIG_CTS 2 +#define CLK_TOP_CLKPH_MCK 3 +#define CLK_TOP_CPUM_TCK_IN 4 +#define CLK_TOP_MAINPLL_806M 5 +#define CLK_TOP_MAINPLL_537P3M 6 +#define CLK_TOP_MAINPLL_322P4M 7 +#define CLK_TOP_MAINPLL_230P3M 8 +#define CLK_TOP_UNIVPLL_624M 9 +#define CLK_TOP_UNIVPLL_416M 10 +#define CLK_TOP_UNIVPLL_249P6M 11 +#define CLK_TOP_UNIVPLL_178P3M 12 +#define CLK_TOP_UNIVPLL_48M 13 +#define CLK_TOP_MMPLL_D2 14 +#define CLK_TOP_MMPLL_D3 15 +#define CLK_TOP_MMPLL_D5 16 +#define CLK_TOP_MMPLL_D7 17 +#define CLK_TOP_MMPLL_D4 18 +#define CLK_TOP_MMPLL_D6 19 +#define CLK_TOP_SYSPLL_D2 20 +#define CLK_TOP_SYSPLL_D4 21 +#define CLK_TOP_SYSPLL_D6 22 +#define CLK_TOP_SYSPLL_D8 23 +#define CLK_TOP_SYSPLL_D10 24 +#define CLK_TOP_SYSPLL_D12 25 +#define CLK_TOP_SYSPLL_D16 26 +#define CLK_TOP_SYSPLL_D24 27 +#define CLK_TOP_SYSPLL_D3 28 +#define CLK_TOP_SYSPLL_D2P5 29 +#define CLK_TOP_SYSPLL_D5 30 +#define CLK_TOP_SYSPLL_D3P5 31 +#define CLK_TOP_UNIVPLL1_D2 32 +#define CLK_TOP_UNIVPLL1_D4 33 +#define CLK_TOP_UNIVPLL1_D6 34 +#define CLK_TOP_UNIVPLL1_D8 35 +#define CLK_TOP_UNIVPLL1_D10 36 +#define CLK_TOP_UNIVPLL2_D2 37 +#define CLK_TOP_UNIVPLL2_D4 38 +#define CLK_TOP_UNIVPLL2_D6 39 +#define CLK_TOP_UNIVPLL2_D8 40 +#define CLK_TOP_UNIVPLL_D3 41 +#define CLK_TOP_UNIVPLL_D5 42 +#define CLK_TOP_UNIVPLL_D7 43 +#define CLK_TOP_UNIVPLL_D10 44 +#define CLK_TOP_UNIVPLL_D26 45 +#define CLK_TOP_APLL 46 +#define CLK_TOP_APLL_D4 47 +#define CLK_TOP_APLL_D8 48 +#define CLK_TOP_APLL_D16 49 +#define CLK_TOP_APLL_D24 50 +#define CLK_TOP_LVDSPLL_D2 51 +#define CLK_TOP_LVDSPLL_D4 52 +#define CLK_TOP_LVDSPLL_D8 53 +#define CLK_TOP_LVDSTX_CLKDIG_CT 54 +#define CLK_TOP_VPLL_DPIX 55 +#define CLK_TOP_TVHDMI_H 56 +#define CLK_TOP_HDMITX_CLKDIG_D2 57 +#define CLK_TOP_HDMITX_CLKDIG_D3 58 +#define CLK_TOP_TVHDMI_D2 59 +#define CLK_TOP_TVHDMI_D4 60 +#define CLK_TOP_MEMPLL_MCK_D4 61 +#define CLK_TOP_AXI_SEL 62 +#define CLK_TOP_SMI_SEL 63 +#define CLK_TOP_MFG_SEL 64 +#define CLK_TOP_IRDA_SEL 65 +#define CLK_TOP_CAM_SEL 66 +#define CLK_TOP_AUD_INTBUS_SEL 67 +#define CLK_TOP_JPG_SEL 68 +#define CLK_TOP_DISP_SEL 69 +#define CLK_TOP_MSDC30_1_SEL 70 +#define CLK_TOP_MSDC30_2_SEL 71 +#define CLK_TOP_MSDC30_3_SEL 72 +#define CLK_TOP_MSDC30_4_SEL 73 +#define CLK_TOP_USB20_SEL 74 +#define CLK_TOP_VENC_SEL 75 +#define CLK_TOP_SPI_SEL 76 +#define CLK_TOP_UART_SEL 77 +#define CLK_TOP_MEM_SEL 78 +#define CLK_TOP_CAMTG_SEL 79 +#define CLK_TOP_AUDIO_SEL 80 +#define CLK_TOP_FIX_SEL 81 +#define CLK_TOP_VDEC_SEL 82 +#define CLK_TOP_DDRPHYCFG_SEL 83 +#define CLK_TOP_DPILVDS_SEL 84 +#define CLK_TOP_PMICSPI_SEL 85 +#define CLK_TOP_MSDC30_0_SEL 86 +#define CLK_TOP_SMI_MFG_AS_SEL 87 +#define CLK_TOP_GCPU_SEL 88 +#define CLK_TOP_DPI1_SEL 89 +#define CLK_TOP_CCI_SEL 90 +#define CLK_TOP_APLL_SEL 91 +#define CLK_TOP_HDMIPLL_SEL 92 +#define CLK_TOP_NR_CLK 93 + +/* APMIXED_SYS */ + +#define CLK_APMIXED_ARMPLL1 1 +#define CLK_APMIXED_ARMPLL2 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MSDCPLL 6 +#define CLK_APMIXED_TVDPLL 7 +#define CLK_APMIXED_LVDSPLL 8 +#define CLK_APMIXED_AUDPLL 9 +#define CLK_APMIXED_VDECPLL 10 +#define CLK_APMIXED_NR_CLK 11 + +/* INFRA_SYS */ + +#define CLK_INFRA_PMIC_WRAP 1 +#define CLK_INFRA_PMICSPI 2 +#define CLK_INFRA_CCIF1_AP_CTRL 3 +#define CLK_INFRA_CCIF0_AP_CTRL 4 +#define CLK_INFRA_KP 5 +#define CLK_INFRA_CPUM 6 +#define CLK_INFRA_M4U 7 +#define CLK_INFRA_MFGAXI 8 +#define CLK_INFRA_DEVAPC 9 +#define CLK_INFRA_AUDIO 10 +#define CLK_INFRA_MFG_BUS 11 +#define CLK_INFRA_SMI 12 +#define CLK_INFRA_DBGCLK 13 +#define CLK_INFRA_NR_CLK 14 + +/* PERI_SYS */ + +#define CLK_PERI_I2C5 1 +#define CLK_PERI_I2C4 2 +#define CLK_PERI_I2C3 3 +#define CLK_PERI_I2C2 4 +#define CLK_PERI_I2C1 5 +#define CLK_PERI_I2C0 6 +#define CLK_PERI_UART3 7 +#define CLK_PERI_UART2 8 +#define CLK_PERI_UART1 9 +#define CLK_PERI_UART0 10 +#define CLK_PERI_IRDA 11 +#define CLK_PERI_NLI 12 +#define CLK_PERI_MD_HIF 13 +#define CLK_PERI_AP_HIF 14 +#define CLK_PERI_MSDC30_3 15 +#define CLK_PERI_MSDC30_2 16 +#define CLK_PERI_MSDC30_1 17 +#define CLK_PERI_MSDC20_2 18 +#define CLK_PERI_MSDC20_1 19 +#define CLK_PERI_AP_DMA 20 +#define CLK_PERI_USB1 21 +#define CLK_PERI_USB0 22 +#define CLK_PERI_PWM 23 +#define CLK_PERI_PWM7 24 +#define CLK_PERI_PWM6 25 +#define CLK_PERI_PWM5 26 +#define CLK_PERI_PWM4 27 +#define CLK_PERI_PWM3 28 +#define CLK_PERI_PWM2 29 +#define CLK_PERI_PWM1 30 +#define CLK_PERI_THERM 31 +#define CLK_PERI_NFI 32 +#define CLK_PERI_USBSLV 33 +#define CLK_PERI_USB1_MCU 34 +#define CLK_PERI_USB0_MCU 35 +#define CLK_PERI_GCPU 36 +#define CLK_PERI_FHCTL 37 +#define CLK_PERI_SPI1 38 +#define CLK_PERI_AUXADC 39 +#define CLK_PERI_PERI_PWRAP 40 +#define CLK_PERI_I2C6 41 +#define CLK_PERI_UART0_SEL 42 +#define CLK_PERI_UART1_SEL 43 +#define CLK_PERI_UART2_SEL 44 +#define CLK_PERI_UART3_SEL 45 +#define CLK_PERI_NR_CLK 46 + +#endif /* _DT_BINDINGS_CLK_MT8135_H */ diff --git a/dts/include/dt-bindings/clock/mt8173-clk.h b/dts/include/dt-bindings/clock/mt8173-clk.h new file mode 100644 index 0000000000..4ad76ed882 --- /dev/null +++ b/dts/include/dt-bindings/clock/mt8173-clk.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MT8173_H +#define _DT_BINDINGS_CLK_MT8173_H + +/* TOPCKGEN */ + +#define CLK_TOP_CLKPH_MCK_O 1 +#define CLK_TOP_DPI 2 +#define CLK_TOP_USB_SYSPLL_125M 3 +#define CLK_TOP_HDMITX_DIG_CTS 4 +#define CLK_TOP_ARMCA7PLL_754M 5 +#define CLK_TOP_ARMCA7PLL_502M 6 +#define CLK_TOP_MAIN_H546M 7 +#define CLK_TOP_MAIN_H364M 8 +#define CLK_TOP_MAIN_H218P4M 9 +#define CLK_TOP_MAIN_H156M 10 +#define CLK_TOP_TVDPLL_445P5M 11 +#define CLK_TOP_TVDPLL_594M 12 +#define CLK_TOP_UNIV_624M 13 +#define CLK_TOP_UNIV_416M 14 +#define CLK_TOP_UNIV_249P6M 15 +#define CLK_TOP_UNIV_178P3M 16 +#define CLK_TOP_UNIV_48M 17 +#define CLK_TOP_CLKRTC_EXT 18 +#define CLK_TOP_CLKRTC_INT 19 +#define CLK_TOP_FPC 20 +#define CLK_TOP_HDMITXPLL_D2 21 +#define CLK_TOP_HDMITXPLL_D3 22 +#define CLK_TOP_ARMCA7PLL_D2 23 +#define CLK_TOP_ARMCA7PLL_D3 24 +#define CLK_TOP_APLL1 25 +#define CLK_TOP_APLL2 26 +#define CLK_TOP_DMPLL 27 +#define CLK_TOP_DMPLL_D2 28 +#define CLK_TOP_DMPLL_D4 29 +#define CLK_TOP_DMPLL_D8 30 +#define CLK_TOP_DMPLL_D16 31 +#define CLK_TOP_LVDSPLL_D2 32 +#define CLK_TOP_LVDSPLL_D4 33 +#define CLK_TOP_LVDSPLL_D8 34 +#define CLK_TOP_MMPLL 35 +#define CLK_TOP_MMPLL_D2 36 +#define CLK_TOP_MSDCPLL 37 +#define CLK_TOP_MSDCPLL_D2 38 +#define CLK_TOP_MSDCPLL_D4 39 +#define CLK_TOP_MSDCPLL2 40 +#define CLK_TOP_MSDCPLL2_D2 41 +#define CLK_TOP_MSDCPLL2_D4 42 +#define CLK_TOP_SYSPLL_D2 43 +#define CLK_TOP_SYSPLL1_D2 44 +#define CLK_TOP_SYSPLL1_D4 45 +#define CLK_TOP_SYSPLL1_D8 46 +#define CLK_TOP_SYSPLL1_D16 47 +#define CLK_TOP_SYSPLL_D3 48 +#define CLK_TOP_SYSPLL2_D2 49 +#define CLK_TOP_SYSPLL2_D4 50 +#define CLK_TOP_SYSPLL_D5 51 +#define CLK_TOP_SYSPLL3_D2 52 +#define CLK_TOP_SYSPLL3_D4 53 +#define CLK_TOP_SYSPLL_D7 54 +#define CLK_TOP_SYSPLL4_D2 55 +#define CLK_TOP_SYSPLL4_D4 56 +#define CLK_TOP_TVDPLL 57 +#define CLK_TOP_TVDPLL_D2 58 +#define CLK_TOP_TVDPLL_D4 59 +#define CLK_TOP_TVDPLL_D8 60 +#define CLK_TOP_TVDPLL_D16 61 +#define CLK_TOP_UNIVPLL_D2 62 +#define CLK_TOP_UNIVPLL1_D2 63 +#define CLK_TOP_UNIVPLL1_D4 64 +#define CLK_TOP_UNIVPLL1_D8 65 +#define CLK_TOP_UNIVPLL_D3 66 +#define CLK_TOP_UNIVPLL2_D2 67 +#define CLK_TOP_UNIVPLL2_D4 68 +#define CLK_TOP_UNIVPLL2_D8 69 +#define CLK_TOP_UNIVPLL_D5 70 +#define CLK_TOP_UNIVPLL3_D2 71 +#define CLK_TOP_UNIVPLL3_D4 72 +#define CLK_TOP_UNIVPLL3_D8 73 +#define CLK_TOP_UNIVPLL_D7 74 +#define CLK_TOP_UNIVPLL_D26 75 +#define CLK_TOP_UNIVPLL_D52 76 +#define CLK_TOP_VCODECPLL 77 +#define CLK_TOP_VCODECPLL_370P5 78 +#define CLK_TOP_VENCPLL 79 +#define CLK_TOP_VENCPLL_D2 80 +#define CLK_TOP_VENCPLL_D4 81 +#define CLK_TOP_AXI_SEL 82 +#define CLK_TOP_MEM_SEL 83 +#define CLK_TOP_DDRPHYCFG_SEL 84 +#define CLK_TOP_MM_SEL 85 +#define CLK_TOP_PWM_SEL 86 +#define CLK_TOP_VDEC_SEL 87 +#define CLK_TOP_VENC_SEL 88 +#define CLK_TOP_MFG_SEL 89 +#define CLK_TOP_CAMTG_SEL 90 +#define CLK_TOP_UART_SEL 91 +#define CLK_TOP_SPI_SEL 92 +#define CLK_TOP_USB20_SEL 93 +#define CLK_TOP_USB30_SEL 94 +#define CLK_TOP_MSDC50_0_H_SEL 95 +#define CLK_TOP_MSDC50_0_SEL 96 +#define CLK_TOP_MSDC30_1_SEL 97 +#define CLK_TOP_MSDC30_2_SEL 98 +#define CLK_TOP_MSDC30_3_SEL 99 +#define CLK_TOP_AUDIO_SEL 100 +#define CLK_TOP_AUD_INTBUS_SEL 101 +#define CLK_TOP_PMICSPI_SEL 102 +#define CLK_TOP_SCP_SEL 103 +#define CLK_TOP_ATB_SEL 104 +#define CLK_TOP_VENC_LT_SEL 105 +#define CLK_TOP_DPI0_SEL 106 +#define CLK_TOP_IRDA_SEL 107 +#define CLK_TOP_CCI400_SEL 108 +#define CLK_TOP_AUD_1_SEL 109 +#define CLK_TOP_AUD_2_SEL 110 +#define CLK_TOP_MEM_MFG_IN_SEL 111 +#define CLK_TOP_AXI_MFG_IN_SEL 112 +#define CLK_TOP_SCAM_SEL 113 +#define CLK_TOP_SPINFI_IFR_SEL 114 +#define CLK_TOP_HDMI_SEL 115 +#define CLK_TOP_DPILVDS_SEL 116 +#define CLK_TOP_MSDC50_2_H_SEL 117 +#define CLK_TOP_HDCP_SEL 118 +#define CLK_TOP_HDCP_24M_SEL 119 +#define CLK_TOP_RTC_SEL 120 +#define CLK_TOP_APLL1_DIV0 121 +#define CLK_TOP_APLL1_DIV1 122 +#define CLK_TOP_APLL1_DIV2 123 +#define CLK_TOP_APLL1_DIV3 124 +#define CLK_TOP_APLL1_DIV4 125 +#define CLK_TOP_APLL1_DIV5 126 +#define CLK_TOP_APLL2_DIV0 127 +#define CLK_TOP_APLL2_DIV1 128 +#define CLK_TOP_APLL2_DIV2 129 +#define CLK_TOP_APLL2_DIV3 130 +#define CLK_TOP_APLL2_DIV4 131 +#define CLK_TOP_APLL2_DIV5 132 +#define CLK_TOP_I2S0_M_SEL 133 +#define CLK_TOP_I2S1_M_SEL 134 +#define CLK_TOP_I2S2_M_SEL 135 +#define CLK_TOP_I2S3_M_SEL 136 +#define CLK_TOP_I2S3_B_SEL 137 +#define CLK_TOP_NR_CLK 138 + +/* APMIXED_SYS */ + +#define CLK_APMIXED_ARMCA15PLL 1 +#define CLK_APMIXED_ARMCA7PLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MSDCPLL 6 +#define CLK_APMIXED_VENCPLL 7 +#define CLK_APMIXED_TVDPLL 8 +#define CLK_APMIXED_MPLL 9 +#define CLK_APMIXED_VCODECPLL 10 +#define CLK_APMIXED_APLL1 11 +#define CLK_APMIXED_APLL2 12 +#define CLK_APMIXED_LVDSPLL 13 +#define CLK_APMIXED_MSDCPLL2 14 +#define CLK_APMIXED_NR_CLK 15 + +/* INFRA_SYS */ + +#define CLK_INFRA_DBGCLK 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_AUDIO 3 +#define CLK_INFRA_GCE 4 +#define CLK_INFRA_L2C_SRAM 5 +#define CLK_INFRA_M4U 6 +#define CLK_INFRA_CPUM 7 +#define CLK_INFRA_KP 8 +#define CLK_INFRA_CEC 9 +#define CLK_INFRA_PMICSPI 10 +#define CLK_INFRA_PMICWRAP 11 +#define CLK_INFRA_NR_CLK 12 + +/* PERI_SYS */ + +#define CLK_PERI_NFI 1 +#define CLK_PERI_THERM 2 +#define CLK_PERI_PWM1 3 +#define CLK_PERI_PWM2 4 +#define CLK_PERI_PWM3 5 +#define CLK_PERI_PWM4 6 +#define CLK_PERI_PWM5 7 +#define CLK_PERI_PWM6 8 +#define CLK_PERI_PWM7 9 +#define CLK_PERI_PWM 10 +#define CLK_PERI_USB0 11 +#define CLK_PERI_USB1 12 +#define CLK_PERI_AP_DMA 13 +#define CLK_PERI_MSDC30_0 14 +#define CLK_PERI_MSDC30_1 15 +#define CLK_PERI_MSDC30_2 16 +#define CLK_PERI_MSDC30_3 17 +#define CLK_PERI_NLI_ARB 18 +#define CLK_PERI_IRDA 19 +#define CLK_PERI_UART0 20 +#define CLK_PERI_UART1 21 +#define CLK_PERI_UART2 22 +#define CLK_PERI_UART3 23 +#define CLK_PERI_I2C0 24 +#define CLK_PERI_I2C1 25 +#define CLK_PERI_I2C2 26 +#define CLK_PERI_I2C3 27 +#define CLK_PERI_I2C4 28 +#define CLK_PERI_AUXADC 29 +#define CLK_PERI_SPI0 30 +#define CLK_PERI_I2C5 31 +#define CLK_PERI_NFIECC 32 +#define CLK_PERI_SPI 33 +#define CLK_PERI_IRRX 34 +#define CLK_PERI_I2C6 35 +#define CLK_PERI_UART0_SEL 36 +#define CLK_PERI_UART1_SEL 37 +#define CLK_PERI_UART2_SEL 38 +#define CLK_PERI_UART3_SEL 39 +#define CLK_PERI_NR_CLK 40 + +#endif /* _DT_BINDINGS_CLK_MT8173_H */ diff --git a/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h index ebd63fd056..dc4254b8cb 100644 --- a/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ b/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h @@ -289,5 +289,7 @@ #define UBI32_CORE1_CLK 279 #define UBI32_CORE2_CLK 280 #define EBI2_AON_CLK 281 +#define NSSTCM_CLK_SRC 282 +#define NSSTCM_CLK 283 #endif diff --git a/dts/include/dt-bindings/clock/r8a73a4-clock.h b/dts/include/dt-bindings/clock/r8a73a4-clock.h index 9a4b4c9ca4..dd11ecdf83 100644 --- a/dts/include/dt-bindings/clock/r8a73a4-clock.h +++ b/dts/include/dt-bindings/clock/r8a73a4-clock.h @@ -54,6 +54,7 @@ #define R8A73A4_CLK_IIC3 11 #define R8A73A4_CLK_IIC4 10 #define R8A73A4_CLK_IIC5 9 +#define R8A73A4_CLK_IRQC 7 /* MSTP5 */ #define R8A73A4_CLK_THERMAL 22 diff --git a/dts/include/dt-bindings/clock/r8a7790-clock.h b/dts/include/dt-bindings/clock/r8a7790-clock.h index 3f2c6b198d..ff7ca3584e 100644 --- a/dts/include/dt-bindings/clock/r8a7790-clock.h +++ b/dts/include/dt-bindings/clock/r8a7790-clock.h @@ -79,6 +79,9 @@ #define R8A7790_CLK_USBDMAC0 30 #define R8A7790_CLK_USBDMAC1 31 +/* MSTP4 */ +#define R8A7790_CLK_IRQC 7 + /* MSTP5 */ #define R8A7790_CLK_AUDIO_DMAC1 1 #define R8A7790_CLK_AUDIO_DMAC0 2 diff --git a/dts/include/dt-bindings/clock/r8a7791-clock.h b/dts/include/dt-bindings/clock/r8a7791-clock.h index 8fc5dc8fae..402268384b 100644 --- a/dts/include/dt-bindings/clock/r8a7791-clock.h +++ b/dts/include/dt-bindings/clock/r8a7791-clock.h @@ -70,6 +70,9 @@ #define R8A7791_CLK_USBDMAC0 30 #define R8A7791_CLK_USBDMAC1 31 +/* MSTP4 */ +#define R8A7791_CLK_IRQC 7 + /* MSTP5 */ #define R8A7791_CLK_AUDIO_DMAC1 1 #define R8A7791_CLK_AUDIO_DMAC0 2 diff --git a/dts/include/dt-bindings/clock/r8a7794-clock.h b/dts/include/dt-bindings/clock/r8a7794-clock.h index d63323032d..09da38a587 100644 --- a/dts/include/dt-bindings/clock/r8a7794-clock.h +++ b/dts/include/dt-bindings/clock/r8a7794-clock.h @@ -60,6 +60,9 @@ #define R8A7794_CLK_USBDMAC0 30 #define R8A7794_CLK_USBDMAC1 31 +/* MSTP4 */ +#define R8A7794_CLK_IRQC 7 + /* MSTP5 */ #define R8A7794_CLK_THERMAL 22 #define R8A7794_CLK_PWM 23 diff --git a/dts/include/dt-bindings/clock/samsung,s2mps11.h b/dts/include/dt-bindings/clock/samsung,s2mps11.h new file mode 100644 index 0000000000..b903d7de27 --- /dev/null +++ b/dts/include/dt-bindings/clock/samsung,s2mps11.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Markus Reichl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H + +/* Fixed rate clocks. */ + +#define S2MPS11_CLK_AP 0 +#define S2MPS11_CLK_CP 1 +#define S2MPS11_CLK_BT 2 + +/* Total number of clocks. */ +#define S2MPS11_CLKS_NUM (S2MPS11_CLK_BT + 1) + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H */ diff --git a/dts/include/dt-bindings/clock/vf610-clock.h b/dts/include/dt-bindings/clock/vf610-clock.h index 979d24a679..d197634394 100644 --- a/dts/include/dt-bindings/clock/vf610-clock.h +++ b/dts/include/dt-bindings/clock/vf610-clock.h @@ -193,6 +193,7 @@ #define VF610_PLL6_BYPASS 180 #define VF610_PLL7_BYPASS 181 #define VF610_CLK_SNVS 182 -#define VF610_CLK_END 183 +#define VF610_CLK_DAP 183 +#define VF610_CLK_END 184 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/dts/include/dt-bindings/clock/zx296702-clock.h b/dts/include/dt-bindings/clock/zx296702-clock.h new file mode 100644 index 0000000000..e683dbb7e7 --- /dev/null +++ b/dts/include/dt-bindings/clock/zx296702-clock.h @@ -0,0 +1,170 @@ +/* + * Copyright 2014 Linaro Ltd. + * Copyright (C) 2014 ZTE Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_ZX296702_H +#define __DT_BINDINGS_CLOCK_ZX296702_H + +#define ZX296702_OSC 0 +#define ZX296702_PLL_A9 1 +#define ZX296702_PLL_A9_350M 2 +#define ZX296702_PLL_MAC_1000M 3 +#define ZX296702_PLL_MAC_333M 4 +#define ZX296702_PLL_MM0_1188M 5 +#define ZX296702_PLL_MM0_396M 6 +#define ZX296702_PLL_MM0_198M 7 +#define ZX296702_PLL_MM1_108M 8 +#define ZX296702_PLL_MM1_72M 9 +#define ZX296702_PLL_MM1_54M 10 +#define ZX296702_PLL_LSP_104M 11 +#define ZX296702_PLL_LSP_26M 12 +#define ZX296702_PLL_AUDIO_294M912 13 +#define ZX296702_PLL_DDR_266M 14 +#define ZX296702_CLK_148M5 15 +#define ZX296702_MATRIX_ACLK 16 +#define ZX296702_MAIN_HCLK 17 +#define ZX296702_MAIN_PCLK 18 +#define ZX296702_CLK_500 19 +#define ZX296702_CLK_250 20 +#define ZX296702_CLK_125 21 +#define ZX296702_CLK_74M25 22 +#define ZX296702_A9_WCLK 23 +#define ZX296702_A9_AS1_ACLK_MUX 24 +#define ZX296702_A9_TRACE_CLKIN_MUX 25 +#define ZX296702_A9_AS1_ACLK_DIV 26 +#define ZX296702_CLK_2 27 +#define ZX296702_CLK_27 28 +#define ZX296702_DECPPU_ACLK_MUX 29 +#define ZX296702_PPU_ACLK_MUX 30 +#define ZX296702_MALI400_ACLK_MUX 31 +#define ZX296702_VOU_ACLK_MUX 32 +#define ZX296702_VOU_MAIN_WCLK_MUX 33 +#define ZX296702_VOU_AUX_WCLK_MUX 34 +#define ZX296702_VOU_SCALER_WCLK_MUX 35 +#define ZX296702_R2D_ACLK_MUX 36 +#define ZX296702_R2D_WCLK_MUX 37 +#define ZX296702_CLK_50 38 +#define ZX296702_CLK_25 39 +#define ZX296702_CLK_12 40 +#define ZX296702_CLK_16M384 41 +#define ZX296702_CLK_32K768 42 +#define ZX296702_SEC_WCLK_DIV 43 +#define ZX296702_DDR_WCLK_MUX 44 +#define ZX296702_NAND_WCLK_MUX 45 +#define ZX296702_LSP_26_WCLK_MUX 46 +#define ZX296702_A9_AS0_ACLK 47 +#define ZX296702_A9_AS1_ACLK 48 +#define ZX296702_A9_TRACE_CLKIN 49 +#define ZX296702_DECPPU_AXI_M_ACLK 50 +#define ZX296702_DECPPU_AHB_S_HCLK 51 +#define ZX296702_PPU_AXI_M_ACLK 52 +#define ZX296702_PPU_AHB_S_HCLK 53 +#define ZX296702_VOU_AXI_M_ACLK 54 +#define ZX296702_VOU_APB_PCLK 55 +#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 +#define ZX296702_VOU_AUX_CHANNEL_WCLK 57 +#define ZX296702_VOU_HDMI_OSCLK_CEC 58 +#define ZX296702_VOU_SCALER_WCLK 59 +#define ZX296702_MALI400_AXI_M_ACLK 60 +#define ZX296702_MALI400_APB_PCLK 61 +#define ZX296702_R2D_WCLK 62 +#define ZX296702_R2D_AXI_M_ACLK 63 +#define ZX296702_R2D_AHB_HCLK 64 +#define ZX296702_DDR3_AXI_S0_ACLK 65 +#define ZX296702_DDR3_APB_PCLK 66 +#define ZX296702_DDR3_WCLK 67 +#define ZX296702_USB20_0_AHB_HCLK 68 +#define ZX296702_USB20_0_EXTREFCLK 69 +#define ZX296702_USB20_1_AHB_HCLK 70 +#define ZX296702_USB20_1_EXTREFCLK 71 +#define ZX296702_USB20_2_AHB_HCLK 72 +#define ZX296702_USB20_2_EXTREFCLK 73 +#define ZX296702_GMAC_AXI_M_ACLK 74 +#define ZX296702_GMAC_APB_PCLK 75 +#define ZX296702_GMAC_125_CLKIN 76 +#define ZX296702_GMAC_RMII_CLKIN 77 +#define ZX296702_GMAC_25M_CLK 78 +#define ZX296702_NANDFLASH_AHB_HCLK 79 +#define ZX296702_NANDFLASH_WCLK 80 +#define ZX296702_LSP0_APB_PCLK 81 +#define ZX296702_LSP0_AHB_HCLK 82 +#define ZX296702_LSP0_26M_WCLK 83 +#define ZX296702_LSP0_104M_WCLK 84 +#define ZX296702_LSP0_16M384_WCLK 85 +#define ZX296702_LSP1_APB_PCLK 86 +#define ZX296702_LSP1_26M_WCLK 87 +#define ZX296702_LSP1_104M_WCLK 88 +#define ZX296702_LSP1_32K_CLK 89 +#define ZX296702_AON_HCLK 90 +#define ZX296702_SYS_CTRL_PCLK 91 +#define ZX296702_DMA_PCLK 92 +#define ZX296702_DMA_ACLK 93 +#define ZX296702_SEC_HCLK 94 +#define ZX296702_AES_WCLK 95 +#define ZX296702_DES_WCLK 96 +#define ZX296702_IRAM_ACLK 97 +#define ZX296702_IROM_ACLK 98 +#define ZX296702_BOOT_CTRL_HCLK 99 +#define ZX296702_EFUSE_CLK_30 100 +#define ZX296702_VOU_MAIN_CHANNEL_DIV 101 +#define ZX296702_VOU_AUX_CHANNEL_DIV 102 +#define ZX296702_VOU_TV_ENC_HD_DIV 103 +#define ZX296702_VOU_TV_ENC_SD_DIV 104 +#define ZX296702_VL0_MUX 105 +#define ZX296702_VL1_MUX 106 +#define ZX296702_VL2_MUX 107 +#define ZX296702_GL0_MUX 108 +#define ZX296702_GL1_MUX 109 +#define ZX296702_GL2_MUX 110 +#define ZX296702_WB_MUX 111 +#define ZX296702_HDMI_MUX 112 +#define ZX296702_VOU_TV_ENC_HD_MUX 113 +#define ZX296702_VOU_TV_ENC_SD_MUX 114 +#define ZX296702_VL0_CLK 115 +#define ZX296702_VL1_CLK 116 +#define ZX296702_VL2_CLK 117 +#define ZX296702_GL0_CLK 118 +#define ZX296702_GL1_CLK 119 +#define ZX296702_GL2_CLK 120 +#define ZX296702_WB_CLK 121 +#define ZX296702_CL_CLK 122 +#define ZX296702_MAIN_MIX_CLK 123 +#define ZX296702_AUX_MIX_CLK 124 +#define ZX296702_HDMI_CLK 125 +#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 +#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 +#define ZX296702_A9_PERIPHCLK 128 +#define ZX296702_TOPCLK_END 129 + +#define ZX296702_SDMMC1_WCLK_MUX 0 +#define ZX296702_SDMMC1_WCLK_DIV 1 +#define ZX296702_SDMMC1_WCLK 2 +#define ZX296702_SDMMC1_PCLK 3 +#define ZX296702_SPDIF0_WCLK_MUX 4 +#define ZX296702_SPDIF0_WCLK 5 +#define ZX296702_SPDIF0_PCLK 6 +#define ZX296702_SPDIF0_DIV 7 +#define ZX296702_I2S0_WCLK_MUX 8 +#define ZX296702_I2S0_WCLK 9 +#define ZX296702_I2S0_PCLK 10 +#define ZX296702_I2S0_DIV 11 +#define ZX296702_LSP0CLK_END 12 + +#define ZX296702_UART0_WCLK_MUX 0 +#define ZX296702_UART0_WCLK 1 +#define ZX296702_UART0_PCLK 2 +#define ZX296702_UART1_WCLK_MUX 3 +#define ZX296702_UART1_WCLK 4 +#define ZX296702_UART1_PCLK 5 +#define ZX296702_SDMMC0_WCLK_MUX 6 +#define ZX296702_SDMMC0_WCLK_DIV 7 +#define ZX296702_SDMMC0_WCLK 8 +#define ZX296702_SDMMC0_PCLK 9 +#define ZX296702_LSP1CLK_END 10 + +#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ diff --git a/dts/include/dt-bindings/mfd/arizona.h b/dts/include/dt-bindings/mfd/arizona.h index c7af7c7ef7..7b2000cead 100644 --- a/dts/include/dt-bindings/mfd/arizona.h +++ b/dts/include/dt-bindings/mfd/arizona.h @@ -90,4 +90,22 @@ #define ARIZONA_INMODE_SE 1 #define ARIZONA_INMODE_DMIC 2 +#define ARIZONA_MICD_TIME_CONTINUOUS 0 +#define ARIZONA_MICD_TIME_250US 1 +#define ARIZONA_MICD_TIME_500US 2 +#define ARIZONA_MICD_TIME_1MS 3 +#define ARIZONA_MICD_TIME_2MS 4 +#define ARIZONA_MICD_TIME_4MS 5 +#define ARIZONA_MICD_TIME_8MS 6 +#define ARIZONA_MICD_TIME_16MS 7 +#define ARIZONA_MICD_TIME_32MS 8 +#define ARIZONA_MICD_TIME_64MS 9 +#define ARIZONA_MICD_TIME_128MS 10 +#define ARIZONA_MICD_TIME_256MS 11 +#define ARIZONA_MICD_TIME_512MS 12 + +#define ARIZONA_ACCDET_MODE_MIC 0 +#define ARIZONA_ACCDET_MODE_HPL 1 +#define ARIZONA_ACCDET_MODE_HPR 2 + #endif diff --git a/dts/include/dt-bindings/mfd/st-lpc.h b/dts/include/dt-bindings/mfd/st-lpc.h new file mode 100644 index 0000000000..e3e6c75d88 --- /dev/null +++ b/dts/include/dt-bindings/mfd/st-lpc.h @@ -0,0 +1,15 @@ +/* + * This header provides shared DT/Driver defines for ST's LPC device + * + * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved + * + * Author: Lee Jones for STMicroelectronics + */ + +#ifndef __DT_BINDINGS_ST_LPC_H__ +#define __DT_BINDINGS_ST_LPC_H__ + +#define ST_LPC_MODE_RTC 0 +#define ST_LPC_MODE_WDT 1 + +#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/dts/include/dt-bindings/net/ti-dp83867.h b/dts/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 0000000000..172744a72e --- /dev/null +++ b/dts/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,45 @@ +/* + * Device Tree constants for the Texas Instruments DP83867 PHY + * + * Author: Dan Murphy + * + * Copyright: (C) 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif diff --git a/dts/include/dt-bindings/phy/phy-pistachio-usb.h b/dts/include/dt-bindings/phy/phy-pistachio-usb.h new file mode 100644 index 0000000000..d1877aa0a3 --- /dev/null +++ b/dts/include/dt-bindings/phy/phy-pistachio-usb.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_PHY_PISTACHIO +#define _DT_BINDINGS_PHY_PISTACHIO + +#define REFCLK_XO_CRYSTAL 0x0 +#define REFCLK_X0_EXT_CLK 0x1 +#define REFCLK_CLK_CORE 0x2 + +#endif /* _DT_BINDINGS_PHY_PISTACHIO */ diff --git a/dts/include/dt-bindings/pinctrl/am43xx.h b/dts/include/dt-bindings/pinctrl/am43xx.h index 5f4d01898c..b00bbc9c60 100644 --- a/dts/include/dt-bindings/pinctrl/am43xx.h +++ b/dts/include/dt-bindings/pinctrl/am43xx.h @@ -21,6 +21,7 @@ #define SLEWCTRL_SLOW (1 << 19) #define SLEWCTRL_FAST 0 #define DS0_PULL_UP_DOWN_EN (1 << 27) +#define WAKEUP_ENABLE (1 << 29) #define PIN_OUTPUT (PULL_DISABLE) #define PIN_OUTPUT_PULLUP (PULL_UP) diff --git a/dts/include/dt-bindings/pinctrl/bcm2835.h b/dts/include/dt-bindings/pinctrl/bcm2835.h new file mode 100644 index 0000000000..6f0bc37af3 --- /dev/null +++ b/dts/include/dt-bindings/pinctrl/bcm2835.h @@ -0,0 +1,27 @@ +/* + * Header providing constants for bcm2835 pinctrl bindings. + * + * Copyright (C) 2015 Stefan Wahren + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ +#define __DT_BINDINGS_PINCTRL_BCM2835_H__ + +/* brcm,function property */ +#define BCM2835_FSEL_GPIO_IN 0 +#define BCM2835_FSEL_GPIO_OUT 1 +#define BCM2835_FSEL_ALT5 2 +#define BCM2835_FSEL_ALT4 3 +#define BCM2835_FSEL_ALT0 4 +#define BCM2835_FSEL_ALT1 5 +#define BCM2835_FSEL_ALT2 6 +#define BCM2835_FSEL_ALT3 7 + +#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ diff --git a/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h b/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h new file mode 100644 index 0000000000..85739b308c --- /dev/null +++ b/dts/include/dt-bindings/pinctrl/mt6397-pinfunc.h @@ -0,0 +1,256 @@ +#ifndef __DTS_MT6397_PINFUNC_H +#define __DTS_MT6397_PINFUNC_H + +#include + +#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) + +#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) +#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) + +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) +#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) + +#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) +#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) + +#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) + +#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) + +#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) + +#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) + +#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) + +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) +#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) + +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) +#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) + +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) +#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) + +#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) +#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) +#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) +#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) +#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) + +#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) +#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) +#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) +#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) +#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) + +#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) +#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) +#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) +#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) +#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) + +#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) +#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) +#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) +#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) +#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) + +#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) +#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) +#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) +#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) +#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) + +#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) +#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) +#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) +#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) +#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) + +#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) +#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) +#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) +#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) +#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) +#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) +#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) + +#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) +#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) +#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) +#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) +#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) +#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) +#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) + +#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) +#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) +#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) +#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) +#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) + +#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) +#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) +#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) +#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) +#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) +#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) + +#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) +#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) +#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) +#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) +#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) + +#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) +#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) +#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) +#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) +#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) + +#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) +#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) +#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) +#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) +#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) + +#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) +#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) +#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) +#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) +#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) + +#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) +#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) +#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) +#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) +#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) +#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) +#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) + +#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) +#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) +#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) +#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) +#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) +#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) +#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) + +#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) +#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) +#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) +#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) +#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) +#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) + +#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) +#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) +#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) +#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) +#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) +#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) + +#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) +#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) +#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) +#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) +#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) +#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) +#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) + +#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) +#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) +#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) +#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) +#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) + +#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) +#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) +#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) +#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) + +#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) +#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) +#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) +#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) +#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) + +#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) +#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) +#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) +#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) + +#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) +#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) +#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) +#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) +#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) + +#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) +#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) +#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) +#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) + +#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) +#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) +#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) + +#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) +#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) +#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) + +#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) +#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) +#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) + +#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) +#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) +#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) + +#endif /* __DTS_MT6397_PINFUNC_H */ diff --git a/dts/include/dt-bindings/reset-controller/mt8135-resets.h b/dts/include/dt-bindings/reset-controller/mt8135-resets.h new file mode 100644 index 0000000000..1fb629508d --- /dev/null +++ b/dts/include/dt-bindings/reset-controller/mt8135-resets.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora Fu, MediaTek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 + +/* INFRACFG resets */ +#define MT8135_INFRA_EMI_REG_RST 0 +#define MT8135_INFRA_DRAMC0_A0_RST 1 +#define MT8135_INFRA_CCIF0_RST 2 +#define MT8135_INFRA_APCIRQ_EINT_RST 3 +#define MT8135_INFRA_APXGPT_RST 4 +#define MT8135_INFRA_SCPSYS_RST 5 +#define MT8135_INFRA_CCIF1_RST 6 +#define MT8135_INFRA_PMIC_WRAP_RST 7 +#define MT8135_INFRA_KP_RST 8 +#define MT8135_INFRA_EMI_RST 32 +#define MT8135_INFRA_DRAMC0_RST 34 +#define MT8135_INFRA_SMI_RST 35 +#define MT8135_INFRA_M4U_RST 36 + +/* PERICFG resets */ +#define MT8135_PERI_UART0_SW_RST 0 +#define MT8135_PERI_UART1_SW_RST 1 +#define MT8135_PERI_UART2_SW_RST 2 +#define MT8135_PERI_UART3_SW_RST 3 +#define MT8135_PERI_IRDA_SW_RST 4 +#define MT8135_PERI_PTP_SW_RST 5 +#define MT8135_PERI_AP_HIF_SW_RST 6 +#define MT8135_PERI_GPCU_SW_RST 7 +#define MT8135_PERI_MD_HIF_SW_RST 8 +#define MT8135_PERI_NLI_SW_RST 9 +#define MT8135_PERI_AUXADC_SW_RST 10 +#define MT8135_PERI_DMA_SW_RST 11 +#define MT8135_PERI_NFI_SW_RST 14 +#define MT8135_PERI_PWM_SW_RST 15 +#define MT8135_PERI_THERM_SW_RST 16 +#define MT8135_PERI_MSDC0_SW_RST 17 +#define MT8135_PERI_MSDC1_SW_RST 18 +#define MT8135_PERI_MSDC2_SW_RST 19 +#define MT8135_PERI_MSDC3_SW_RST 20 +#define MT8135_PERI_I2C0_SW_RST 22 +#define MT8135_PERI_I2C1_SW_RST 23 +#define MT8135_PERI_I2C2_SW_RST 24 +#define MT8135_PERI_I2C3_SW_RST 25 +#define MT8135_PERI_I2C4_SW_RST 26 +#define MT8135_PERI_I2C5_SW_RST 27 +#define MT8135_PERI_I2C6_SW_RST 28 +#define MT8135_PERI_USB_SW_RST 29 +#define MT8135_PERI_SPI1_SW_RST 33 +#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ diff --git a/dts/include/dt-bindings/reset-controller/mt8173-resets.h b/dts/include/dt-bindings/reset-controller/mt8173-resets.h new file mode 100644 index 0000000000..9464b37cf6 --- /dev/null +++ b/dts/include/dt-bindings/reset-controller/mt8173-resets.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Flora Fu, MediaTek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 + +/* INFRACFG resets */ +#define MT8173_INFRA_EMI_REG_RST 0 +#define MT8173_INFRA_DRAMC0_A0_RST 1 +#define MT8173_INFRA_APCIRQ_EINT_RST 3 +#define MT8173_INFRA_APXGPT_RST 4 +#define MT8173_INFRA_SCPSYS_RST 5 +#define MT8173_INFRA_KP_RST 6 +#define MT8173_INFRA_PMIC_WRAP_RST 7 +#define MT8173_INFRA_MPIP_RST 8 +#define MT8173_INFRA_CEC_RST 9 +#define MT8173_INFRA_EMI_RST 32 +#define MT8173_INFRA_DRAMC0_RST 34 +#define MT8173_INFRA_APMIXEDSYS_RST 35 +#define MT8173_INFRA_MIPI_DSI_RST 36 +#define MT8173_INFRA_TRNG_RST 37 +#define MT8173_INFRA_SYSIRQ_RST 38 +#define MT8173_INFRA_MIPI_CSI_RST 39 +#define MT8173_INFRA_GCE_FAXI_RST 40 +#define MT8173_INFRA_MMIOMMURST 47 + + +/* PERICFG resets */ +#define MT8173_PERI_UART0_SW_RST 0 +#define MT8173_PERI_UART1_SW_RST 1 +#define MT8173_PERI_UART2_SW_RST 2 +#define MT8173_PERI_UART3_SW_RST 3 +#define MT8173_PERI_IRRX_SW_RST 4 +#define MT8173_PERI_PWM_SW_RST 8 +#define MT8173_PERI_AUXADC_SW_RST 10 +#define MT8173_PERI_DMA_SW_RST 11 +#define MT8173_PERI_I2C6_SW_RST 13 +#define MT8173_PERI_NFI_SW_RST 14 +#define MT8173_PERI_THERM_SW_RST 16 +#define MT8173_PERI_MSDC2_SW_RST 17 +#define MT8173_PERI_MSDC3_SW_RST 18 +#define MT8173_PERI_MSDC0_SW_RST 19 +#define MT8173_PERI_MSDC1_SW_RST 20 +#define MT8173_PERI_I2C0_SW_RST 22 +#define MT8173_PERI_I2C1_SW_RST 23 +#define MT8173_PERI_I2C2_SW_RST 24 +#define MT8173_PERI_I2C3_SW_RST 25 +#define MT8173_PERI_I2C4_SW_RST 26 +#define MT8173_PERI_HDMI_SW_RST 29 +#define MT8173_PERI_SPI0_SW_RST 33 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ diff --git a/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h index 0ad5ef930b..de9c814093 100644 --- a/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ b/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h @@ -129,4 +129,47 @@ #define USB30_1_PHY_RESET 112 #define NSSFB0_RESET 113 #define NSSFB1_RESET 114 +#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 +#define UBI32_CORE1_CLAMP_RESET 116 +#define UBI32_CORE1_AHB_RESET 117 +#define UBI32_CORE1_AXI_RESET 118 +#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 +#define UBI32_CORE2_CLAMP_RESET 120 +#define UBI32_CORE2_AHB_RESET 121 +#define UBI32_CORE2_AXI_RESET 122 +#define GMAC_CORE1_RESET 123 +#define GMAC_CORE2_RESET 124 +#define GMAC_CORE3_RESET 125 +#define GMAC_CORE4_RESET 126 +#define GMAC_AHB_RESET 127 +#define NSS_CH0_RST_RX_CLK_N_RESET 128 +#define NSS_CH0_RST_TX_CLK_N_RESET 129 +#define NSS_CH0_RST_RX_125M_N_RESET 130 +#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 +#define NSS_CH0_RST_TX_125M_N_RESET 132 +#define NSS_CH1_RST_RX_CLK_N_RESET 133 +#define NSS_CH1_RST_TX_CLK_N_RESET 134 +#define NSS_CH1_RST_RX_125M_N_RESET 135 +#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 +#define NSS_CH1_RST_TX_125M_N_RESET 137 +#define NSS_CH2_RST_RX_CLK_N_RESET 138 +#define NSS_CH2_RST_TX_CLK_N_RESET 139 +#define NSS_CH2_RST_RX_125M_N_RESET 140 +#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 +#define NSS_CH2_RST_TX_125M_N_RESET 142 +#define NSS_CH3_RST_RX_CLK_N_RESET 143 +#define NSS_CH3_RST_TX_CLK_N_RESET 144 +#define NSS_CH3_RST_RX_125M_N_RESET 145 +#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 +#define NSS_CH3_RST_TX_125M_N_RESET 147 +#define NSS_RST_RX_250M_125M_N_RESET 148 +#define NSS_RST_TX_250M_125M_N_RESET 149 +#define NSS_QSGMII_TXPI_RST_N_RESET 150 +#define NSS_QSGMII_CDR_RST_N_RESET 151 +#define NSS_SGMII2_CDR_RST_N_RESET 152 +#define NSS_SGMII3_CDR_RST_N_RESET 153 +#define NSS_CAL_PRBS_RST_N_RESET 154 +#define NSS_LCKDT_RST_N_RESET 155 +#define NSS_SRDS_N_RESET 156 + #endif diff --git a/dts/include/dt-bindings/sound/apq8016-lpass.h b/dts/include/dt-bindings/sound/apq8016-lpass.h new file mode 100644 index 0000000000..499076e980 --- /dev/null +++ b/dts/include/dt-bindings/sound/apq8016-lpass.h @@ -0,0 +1,9 @@ +#ifndef __DT_APQ8016_LPASS_H +#define __DT_APQ8016_LPASS_H + +#define MI2S_PRIMARY 0 +#define MI2S_SECONDARY 1 +#define MI2S_TERTIARY 2 +#define MI2S_QUATERNARY 3 + +#endif /* __DT_APQ8016_LPASS_H */ diff --git a/dts/include/dt-bindings/sound/audio-jack-events.h b/dts/include/dt-bindings/sound/audio-jack-events.h new file mode 100644 index 0000000000..378349f280 --- /dev/null +++ b/dts/include/dt-bindings/sound/audio-jack-events.h @@ -0,0 +1,9 @@ +#ifndef __AUDIO_JACK_EVENTS_H +#define __AUDIO_JACK_EVENTS_H + +#define JACK_HEADPHONE 1 +#define JACK_MICROPHONE 2 +#define JACK_LINEOUT 3 +#define JACK_LINEIN 4 + +#endif /* __AUDIO_JACK_EVENTS_H */ diff --git a/dts/include/dt-bindings/sound/tas2552.h b/dts/include/dt-bindings/sound/tas2552.h new file mode 100644 index 0000000000..a4e1a07998 --- /dev/null +++ b/dts/include/dt-bindings/sound/tas2552.h @@ -0,0 +1,18 @@ +#ifndef __DT_TAS2552_H +#define __DT_TAS2552_H + +#define TAS2552_PLL_CLKIN (0) +#define TAS2552_PDM_CLK (1) +#define TAS2552_CLK_TARGET_MASK (1) + +#define TAS2552_PLL_CLKIN_MCLK ((0 << 1) | TAS2552_PLL_CLKIN) +#define TAS2552_PLL_CLKIN_BCLK ((1 << 1) | TAS2552_PLL_CLKIN) +#define TAS2552_PLL_CLKIN_IVCLKIN ((2 << 1) | TAS2552_PLL_CLKIN) +#define TAS2552_PLL_CLKIN_1_8_FIXED ((3 << 1) | TAS2552_PLL_CLKIN) + +#define TAS2552_PDM_CLK_PLL ((0 << 1) | TAS2552_PDM_CLK) +#define TAS2552_PDM_CLK_IVCLKIN ((1 << 1) | TAS2552_PDM_CLK) +#define TAS2552_PDM_CLK_BCLK ((2 << 1) | TAS2552_PDM_CLK) +#define TAS2552_PDM_CLK_MCLK ((3 << 1) | TAS2552_PDM_CLK) + +#endif /* __DT_TAS2552_H */ diff --git a/dts/src/arc/angel4.dts b/dts/src/arc/angel4.dts deleted file mode 100644 index 3b076fbd83..0000000000 --- a/dts/src/arc/angel4.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton.dtsi" - -/ { - compatible = "snps,arc-angel4"; - clock-frequency = <80000000>; /* 80 MHZ */ - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - chosen { - bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; - }; - - aliases { - serial0 = &arcuart0; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - intc: interrupt-controller { - compatible = "snps,arc700-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - arcuart0: serial@c0fc1000 { - compatible = "snps,arc-uart"; - reg = <0xc0fc1000 0x100>; - interrupts = <5>; - clock-frequency = <80000000>; - current-speed = <115200>; - status = "okay"; - }; - - ethernet@c0fc2000 { - compatible = "snps,arc-emac"; - reg = <0xc0fc2000 0x3c>; - interrupts = <6>; - mac-address = [ 00 11 22 33 44 55 ]; - clock-frequency = <80000000>; - max-speed = <100>; - phy = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - }; - - arcpmu0: pmu { - compatible = "snps,arc700-pct"; - }; - }; -}; diff --git a/dts/src/arc/axc001.dtsi b/dts/src/arc/axc001.dtsi new file mode 100644 index 0000000000..a5e2726a06 --- /dev/null +++ b/dts/src/arc/axc001.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC001 770D/EM6/AS221 CPU card + * Note that this file only supports the 770D CPU + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <750000000>; /* 750 MHZ */ + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: arc700-intc@cpu { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&cpu_intc>; + interrupts = <15>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <19 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpmu0: pmu { + compatible = "snps,arc700-pct"; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <7>" instead of + * "interrupts = <12>" + * + * This intc actually resides on MB, but we move it here to + * avoid duplicating the MB dtsi file given that IRQ from + * this intc to cpu intc are different for axs101 and axs103 + */ + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + interrupts = < 7 >; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi new file mode 100644 index 0000000000..15c8d6226c --- /dev/null +++ b/dts/src/arc/axc003.dtsi @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: HS38x UP configuration + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <75000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&cpu_intc>; + interrupts = <25>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <2 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupt-parent = <&cpu_intc>; + interrupts = <20>; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <7>" instead of + * "interrupts = <12>" + * + * This intc actually resides on MB, but we move it here to + * avoid duplicating the MB dtsi file given that IRQ from + * this intc to cpu intc are different for axs101 and axs103 + */ + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + interrupts = < 24 >; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi new file mode 100644 index 0000000000..199d42820e --- /dev/null +++ b/dts/src/arc/axc003_idu.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <75000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* + * upstream irqs to core intc - downstream these are + * "COMMON" irq 0,1.. + */ + interrupts = <24 25>; + }; + + /* + * this GPIO block ORs all interrupts on CPU card (creg,..) + * to uplink only 1 IRQ to ARC core intc + */ + dw-apb-gpio@0x2000 { + compatible = "snps,dw-apb-gpio"; + reg = < 0x2000 0x80 >; + #address-cells = <1>; + #size-cells = <0>; + + ictl_intc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&idu_intc>; + + /* + * cmn irq 1 -> cpu irq 25 + * Distribute to cpu0 only + */ + interrupts = <1 1>; + }; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <33333000>; + interrupt-parent = <&ictl_intc>; + interrupts = <2 4>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupt-parent = <&cpu_intc>; + interrupts = <20>; + }; + }; + + /* + * This INTC is actually connected to DW APB GPIO + * which acts as a wire between MB INTC and CPU INTC. + * GPIO INTC is configured in platform init code + * and here we mimic direct connection from MB INTC to + * CPU INTC, thus we set "interrupts = <0 1>" instead of + * "interrupts = <12>" + * + * This intc actually resides on MB, but we move it here to + * avoid duplicating the MB dtsi file given that IRQ from + * this intc to cpu intc are different for axs101 and axs103 + */ + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&idu_intc>; + interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24 + distribute to cpu0 only */ + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/dts/src/arc/axs101.dts b/dts/src/arc/axs101.dts new file mode 100644 index 0000000000..3f9b0582e7 --- /dev/null +++ b/dts/src/arc/axs101.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * ARC AXS101 S/W development platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "axc001.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs101", "snps,arc-sdp"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + }; +}; diff --git a/dts/src/arc/axs103.dts b/dts/src/arc/axs103.dts new file mode 100644 index 0000000000..e6d0e31ea2 --- /dev/null +++ b/dts/src/arc/axs103.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device Tree for AXS103 SDP with AXS10X Main Board and + * AXC003 FPGA Card (with UP bitfile) + */ +/dts-v1/; + +/include/ "axc003.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103", "snps,arc-sdp"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + }; +}; diff --git a/dts/src/arc/axs103_idu.dts b/dts/src/arc/axs103_idu.dts new file mode 100644 index 0000000000..f999fef5a6 --- /dev/null +++ b/dts/src/arc/axs103_idu.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device Tree for AXS103 SDP with AXS10X Main Board and + * AXC003 FPGA Card (with SMP bitfile) + */ +/dts-v1/; + +/include/ "axc003_idu.dtsi" +/include/ "axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103", "snps,arc-sdp"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + }; +}; diff --git a/dts/src/arc/axs10x_mb.dtsi b/dts/src/arc/axs10x_mb.dtsi new file mode 100644 index 0000000000..f3db321549 --- /dev/null +++ b/dts/src/arc/axs10x_mb.dtsi @@ -0,0 +1,224 @@ +/* + * Support for peripherals on the AXS10x mainboard + * + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + axs10x_mb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0xe0000000 0x10000000>; + interrupt-parent = <&mb_intc>; + + clocks { + i2cclk: i2cclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + apbclk: apbclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + mmcclk: mmcclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + }; + + ethernet@0x18000 { + #interrupt-cells = <1>; + compatible = "snps,dwmac"; + reg = < 0x18000 0x2000 >; + interrupts = < 4 >; + interrupt-names = "macirq"; + phy-mode = "rgmii"; + snps,pbl = < 32 >; + clocks = <&apbclk>; + clock-names = "stmmaceth"; + }; + + ehci@0x40000 { + compatible = "generic-ehci"; + reg = < 0x40000 0x100 >; + interrupts = < 8 >; + }; + + ohci@0x60000 { + compatible = "generic-ohci"; + reg = < 0x60000 0x100 >; + interrupts = < 8 >; + }; + + /* + * According to DW Mobile Storage databook it is required + * to use "Hold Register" if card is enumerated in SDR12 or + * SDR25 modes. + * + * Utilization of "Hold Register" is already implemented via + * dw_mci_pltfm_prepare_command() which in its turn gets + * used through dw_mci_drv_data->prepare_command call-back. + * This call-back is used in Altera Socfpga platform and so + * we may reuse it saying that we're compatible with their + * "altr,socfpga-dw-mshc". + * + * Most probably "Hold Register" utilization is platform- + * independent requirement which means that single unified + * "snps,dw-mshc" should be enough for all users of DW MMC once + * dw_mci_pltfm_prepare_command() is used in generic platform + * code. + */ + mmc@0x15000 { + compatible = "altr,socfpga-dw-mshc"; + reg = < 0x15000 0x400 >; + num-slots = < 1 >; + fifo-depth = < 16 >; + card-detect-delay = < 200 >; + clocks = <&apbclk>, <&mmcclk>; + clock-names = "biu", "ciu"; + interrupts = < 7 >; + bus-width = < 4 >; + }; + + uart@0x20000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20000 0x100>; + clock-frequency = <33333333>; + interrupts = <17>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@0x21000 { + compatible = "snps,dw-apb-uart"; + reg = <0x21000 0x100>; + clock-frequency = <33333333>; + interrupts = <18>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + /* UART muxed with USB data port (ttyS3) */ + uart@0x22000 { + compatible = "snps,dw-apb-uart"; + reg = <0x22000 0x100>; + clock-frequency = <33333333>; + interrupts = <19>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + i2c@0x1d000 { + compatible = "snps,designware-i2c"; + reg = <0x1d000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <14>; + }; + + i2c@0x1e000 { + compatible = "snps,designware-i2c"; + reg = <0x1e000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <15>; + }; + + i2c@0x1f000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1f000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <16>; + + eeprom@0x54{ + compatible = "24c01"; + reg = <0x54>; + pagesize = <0x8>; + }; + + eeprom@0x57{ + compatible = "24c04"; + reg = <0x57>; + pagesize = <0x8>; + }; + }; + + gpio0:gpio@13000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0_banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + + gpio0_bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <1>; + }; + + gpio0_bankc: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <2>; + }; + }; + + gpio1:gpio@14000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio1_banka: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <30>; + reg = <0>; + }; + + gpio1_bankb: gpio-controller@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <10>; + reg = <1>; + }; + + gpio1_bankc: gpio-controller@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <2>; + }; + }; + }; +}; diff --git a/dts/src/arc/nsim_700.dts b/dts/src/arc/nsim_700.dts new file mode 100644 index 0000000000..105a001702 --- /dev/null +++ b/dts/src/arc/nsim_700.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + compatible = "snps,nsim"; + clock-frequency = <80000000>; /* 80 MHZ */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; + }; + + aliases { + serial0 = &arcuart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + intc: interrupt-controller { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + arcuart0: serial@c0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + interrupts = <5>; + clock-frequency = <80000000>; + current-speed = <115200>; + status = "okay"; + }; + + ethernet@c0fc2000 { + compatible = "snps,arc-emac"; + reg = <0xc0fc2000 0x3c>; + interrupts = <6>; + mac-address = [ 00 11 22 33 44 55 ]; + clock-frequency = <80000000>; + max-speed = <100>; + phy = <&phy0>; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <1>; + }; + }; + + arcpmu0: pmu { + compatible = "snps,arc700-pct"; + }; + }; +}; diff --git a/dts/src/arc/nsim_hs.dts b/dts/src/arc/nsim_hs.dts new file mode 100644 index 0000000000..911f069e05 --- /dev/null +++ b/dts/src/arc/nsim_hs.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + compatible = "snps,nsim_hs"; + interrupt-parent = <&core_intc>; + + chosen { + bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; + }; + + aliases { + serial0 = &arcuart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + arcuart0: serial@c0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + interrupts = <24>; + clock-frequency = <80000000>; + current-speed = <115200>; + status = "okay"; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/nsim_hs_idu.dts b/dts/src/arc/nsim_hs_idu.dts new file mode 100644 index 0000000000..46ab319756 --- /dev/null +++ b/dts/src/arc/nsim_hs_idu.dts @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + compatible = "snps,nsim_hs"; + interrupt-parent = <&core_intc>; + + chosen { + bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; + }; + + aliases { + serial0 = &arcuart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* + * upstream irqs to core intc - downstream these are + * "COMMON" irq 0,1.. + */ + interrupts = <24 25 26 27 28 29 30 31>; + }; + + arcuart0: serial@c0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + interrupt-parent = <&idu_intc>; + interrupts = <0 0>; + clock-frequency = <80000000>; + current-speed = <115200>; + status = "okay"; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/nsimosci_hs.dts b/dts/src/arc/nsimosci_hs.dts new file mode 100644 index 0000000000..d64a96f851 --- /dev/null +++ b/dts/src/arc/nsimosci_hs.dts @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + compatible = "snps,nsimosci_hs"; + clock-frequency = <20000000>; /* 20 MHZ */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + chosen { + /* this is for console on PGU */ + /* bootargs = "console=tty0 consoleblank=0"; */ + /* this is for console on serial */ + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@f0000000 { + compatible = "ns8250"; + reg = <0xf0000000 0x2000>; + interrupts = <24>; + clock-frequency = <3686400>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + pgu0: pgu@f9000000 { + compatible = "snps,arcpgufb"; + reg = <0xf9000000 0x400>; + }; + + ps2: ps2@f9001000 { + compatible = "snps,arc_ps2"; + reg = <0xf9000400 0x14>; + interrupts = <27>; + interrupt-names = "arc_ps2_irq"; + }; + + eth0: ethernet@f0003000 { + compatible = "snps,oscilan"; + reg = <0xf0003000 0x44>; + interrupts = <25>, <26>; + interrupt-names = "rx", "tx"; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/nsimosci_hs_idu.dts b/dts/src/arc/nsimosci_hs_idu.dts new file mode 100644 index 0000000000..f6bf0ca95a --- /dev/null +++ b/dts/src/arc/nsimosci_hs_idu.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + compatible = "snps,nsimosci_hs"; + clock-frequency = <5000000>; /* 5 MHZ */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + chosen { + /* this is for console on serial */ + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_intc: core-interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; +/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + /* + * upstream irqs to core intc - downstream these are + * "COMMON" irq 0,1.. + */ + interrupts = <24 25 26 27 28 29 30 31>; + }; + + uart0: serial@f0000000 { + compatible = "ns8250"; + reg = <0xf0000000 0x2000>; + interrupt-parent = <&idu_intc>; + interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24 + RR distribute to all cpus */ + clock-frequency = <3686400>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + pgu0: pgu@f9000000 { + compatible = "snps,arcpgufb"; + reg = <0xf9000000 0x400>; + }; + + ps2: ps2@f9001000 { + compatible = "snps,arc_ps2"; + reg = <0xf9000400 0x14>; + interrupts = <3 0>; + interrupt-parent = <&idu_intc>; + interrupt-names = "arc_ps2_irq"; + }; + + eth0: ethernet@f0003000 { + compatible = "snps,oscilan"; + reg = <0xf0003000 0x44>; + interrupt-parent = <&idu_intc>; + interrupts = <1 2>, <2 2>; + interrupt-names = "rx", "tx"; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/dts/src/arc/vdk_axc003.dtsi b/dts/src/arc/vdk_axc003.dtsi new file mode 100644 index 0000000000..9393fd902f --- /dev/null +++ b/dts/src/arc/vdk_axc003.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version) + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <2403200>; + interrupt-parent = <&cpu_intc>; + interrupts = <19>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + }; + + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + interrupts = < 18 >; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/dts/src/arc/vdk_axc003_idu.dtsi b/dts/src/arc/vdk_axc003_idu.dtsi new file mode 100644 index 0000000000..9bee8ed09e --- /dev/null +++ b/dts/src/arc/vdk_axc003_idu.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Device tree for AXC003 CPU card: + * HS38x2 (Dual Core) with IDU intc (VDK version) + */ + +/ { + compatible = "snps,arc"; + clock-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x00000000 0xf0000000 0x10000000>; + + cpu_intc: archs-intc@cpu { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&cpu_intc>; + + /* + * + * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 + */ + #interrupt-cells = <2>; + + interrupts = <24 25 26 27>; + }; + + debug_uart: dw-apb-uart@0x5000 { + compatible = "snps,dw-apb-uart"; + reg = <0x5000 0x100>; + clock-frequency = <2403200>; + interrupt-parent = <&idu_intc>; + interrupts = <2 0>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + }; + + mb_intc: dw-apb-ictl@0xe0012000 { + #interrupt-cells = <1>; + compatible = "snps,dw-apb-ictl"; + reg = < 0xe0012000 0x200 >; + interrupt-controller; + interrupt-parent = <&idu_intc>; + interrupts = < 0 0 >; + }; + + memory { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x40000000>; + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MiB */ + }; +}; diff --git a/dts/src/arc/vdk_axs10x_mb.dtsi b/dts/src/arc/vdk_axs10x_mb.dtsi new file mode 100644 index 0000000000..45cd665fca --- /dev/null +++ b/dts/src/arc/vdk_axs10x_mb.dtsi @@ -0,0 +1,93 @@ +/* + * Support for peripherals on the AXS10x mainboard (VDK version) + * + * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + axs10x_mb_vdk { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0xe0000000 0x10000000>; + interrupt-parent = <&mb_intc>; + + clocks { + apbclk: apbclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + }; + + ethernet@0x18000 { + #interrupt-cells = <1>; + compatible = "snps,dwmac"; + reg = < 0x18000 0x2000 >; + interrupts = < 4 >; + interrupt-names = "macirq"; + phy-mode = "rgmii"; + snps,phy-addr = < 0 >; // VDK model phy address is 0 + snps,pbl = < 32 >; + clocks = <&apbclk>; + clock-names = "stmmaceth"; + }; + + ehci@0x40000 { + compatible = "generic-ehci"; + reg = < 0x40000 0x100 >; + interrupts = < 8 >; + }; + + uart@0x20000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20000 0x100>; + clock-frequency = <2403200>; + interrupts = <17>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@0x21000 { + compatible = "snps,dw-apb-uart"; + reg = <0x21000 0x100>; + clock-frequency = <2403200>; + interrupts = <18>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart@0x22000 { + compatible = "snps,dw-apb-uart"; + reg = <0x22000 0x100>; + clock-frequency = <2403200>; + interrupts = <19>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + }; + +/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */ + pgu@0x17000 { + compatible = "snps,arcpgufb"; + reg = <0x17000 0x400>; + clock-frequency = <51000000>; /* PGU'clock is initated in init function */ + /* interrupts = <5>; PGU interrupts not used, this vector is used for ps2 below */ + }; + +/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */ + ps2: ps2@e0017400 { + compatible = "snps,arc_ps2"; + reg = <0x17400 0x14>; + interrupts = <5>; + interrupt-names = "arc_ps2_irq"; + }; + }; +}; diff --git a/dts/src/arc/vdk_hs38.dts b/dts/src/arc/vdk_hs38.dts new file mode 100644 index 0000000000..5d803dd2de --- /dev/null +++ b/dts/src/arc/vdk_hs38.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * ARC HS38 Virtual Development Kit (VDK) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "vdk_axc003.dtsi" +/include/ "vdk_axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + }; +}; diff --git a/dts/src/arc/vdk_hs38_smp.dts b/dts/src/arc/vdk_hs38_smp.dts new file mode 100644 index 0000000000..031a5bc79b --- /dev/null +++ b/dts/src/arc/vdk_hs38_smp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * ARC HS38 Virtual Development Kit, SMP version (VDK) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "vdk_axc003_idu.dtsi" +/include/ "vdk_axs10x_mb.dtsi" + +/ { + compatible = "snps,axs103"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + }; +}; diff --git a/dts/src/arm/am335x-baltos-ir5221.dts b/dts/src/arm/am335x-baltos-ir5221.dts new file mode 100644 index 0000000000..7d36601697 --- /dev/null +++ b/dts/src/arm/am335x-baltos-ir5221.dts @@ -0,0 +1,532 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include +#include + +/ { + model = "OnRISC Baltos iR 5221"; + compatible = "vscom,onrisc", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator@2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 8 0>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x020 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ + 0x024 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ + 0x028 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ + 0x02c (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ + 0x080 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ + 0x084 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ + 0x1e4 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + 0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ + >; + }; + + tps65910_pins: pinmux_tps65910_pins { + pinctrl-single,pins = < + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + }; + + tca6416_pins: pinmux_tca6416_pins { + pinctrl-single,pins = < + 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + >; + }; + + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + 0x168 0x0a /* uart0_ctsn.dcan1_tx_mux0, OUTPUT | MODE2 */ + 0x16c 0x2a /* uart0_rtsn.dcan1_rx_mux0, INPUT | MODE2 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x180 0x28 /* uart1_rxd, INPUT | MODE0 */ + 0x184 0x28 /* uart1_txd, INPUT | MODE0 */ + /*0x178 0x28*/ /* uart1_ctsn, INPUT | MODE0 */ + /*0x17c 0x08*/ /* uart1_rtsn, OUTPUT | MODE0 */ + 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */ + 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */ + 0x0e0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + 0x0e4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + 0x0e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + 0x0ec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x150 0x29 /* spi0_sclk.uart2_rxd_mux3, INPUT | MODE1 */ + 0x154 0x09 /* spi0_d0.uart2_txd_mux3, OUTPUT | MODE1 */ + /*0x188 0x2a*/ /* i2c0_sda.uart2_ctsn_mux0, INPUT | MODE2 */ + /*0x18c 0x2a*/ /* i2c0_scl.uart2_rtsn_mux0, INPUT | MODE2 */ + 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */ + 0x18c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */ + 0x030 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + 0x034 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + 0x038 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + 0x03c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "otg"; +}; + +&cppi41dma { + status = "okay"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + ti,non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + + status = "okay"; +}; diff --git a/dts/src/arm/am335x-bone-common.dtsi b/dts/src/arm/am335x-bone-common.dtsi index dbb3f4d2bf..fec78349c1 100644 --- a/dts/src/arm/am335x-bone-common.dtsi +++ b/dts/src/arm/am335x-bone-common.dtsi @@ -81,6 +81,13 @@ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ @@ -218,8 +225,67 @@ reg = <0x24>; }; + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; + + cape_eeprom0: cape_eeprom0@54 { + compatible = "at,24c256"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + cape0_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom1: cape_eeprom1@55 { + compatible = "at,24c256"; + reg = <0x55>; + #address-cells = <1>; + #size-cells = <1>; + cape1_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom2: cape_eeprom2@56 { + compatible = "at,24c256"; + reg = <0x56>; + #address-cells = <1>; + #size-cells = <1>; + cape2_data: cape_data@0 { + reg = <0 0x100>; + }; + }; + + cape_eeprom3: cape_eeprom3@57 { + compatible = "at,24c256"; + reg = <0x57>; + #address-cells = <1>; + #size-cells = <1>; + cape3_data: cape_data@0 { + reg = <0 0x100>; + }; + }; }; + /include/ "tps65217.dtsi" &tps { diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts index 66342515df..765be2766e 100644 --- a/dts/src/arm/am335x-evm.dts +++ b/dts/src/arm/am335x-evm.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "am33xx.dtsi" +#include / { model = "TI AM335x EVM"; @@ -38,6 +39,20 @@ regulator-boot-on; }; + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* WLAN_EN GPIO for this board - Bank1, pin16 */ + gpio = <&gpio1 16 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; + matrix_keypad: matrix_keypad@0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; @@ -176,6 +191,15 @@ >; }; + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; + clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ @@ -266,6 +290,25 @@ >; }; + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ + 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ + 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ + >; + }; + + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ + 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ + >; + }; + lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ @@ -323,6 +366,13 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -665,6 +715,37 @@ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; +&mmc3 { + /* these are on the crossbar and are outlined in the + xbar-event-map element */ + dmas = <&edma 12 + &edma 13>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins &wlan_pins>; + ti,non-removable; + ti,needs-special-hs-handling; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 12 + 2 13>; +}; + &sham { status = "okay"; }; diff --git a/dts/src/arm/am335x-sl50.dts b/dts/src/arm/am335x-sl50.dts new file mode 100644 index 0000000000..3303c28169 --- /dev/null +++ b/dts/src/arm/am335x-sl50.dts @@ -0,0 +1,482 @@ +/* + * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Toby Churchill SL50 Series"; + compatible = "tcl,am335x-sl50", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led@0 { + label = "sl50:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led@1 { + label = "sl50:red:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led@2 { + label = "sl50:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led@3 { + label = "sl50:red:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + backlight0: disp0 { + compatible = "pwm-backlight"; + pwms = <&ehrpwm1 0 500000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <6>; + }; + + backlight1: disp1 { + compatible = "pwm-backlight"; + pwms = <&ehrpwm1 1 500000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <6>; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "AM335x-SL50"; + ti,audio-codec = <&audio_codec>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1R", "Line In", + "LINE1L", "Line In"; + }; + + emmc_pwrseq: pwrseq@0 { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pwrseq_pins>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&lwb_pins>; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ + AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txdi2c1_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + audio_pins: pinmux_audio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + >; + }; + + ehrpwm1_pins: pinmux_ehrpwm1a_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ + >; + }; + + lwb_pins: pinmux_lwb_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ + AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ + AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ + /* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */ + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */ + /* PDI Bus - Battery system */ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ + AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + eeprom: eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; + + audio_codec: tlv320aic3106@1b { + status = "okay"; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + + AVDD-supply = <&ldo4_reg>; + IOVDD-supply = <&ldo4_reg>; + DRVDD-supply = <&ldo4_reg>; + DVDD-supply = <&ldo3_reg>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + vmmc-supply = <&vmmcsd_fixed>; + mmc-pwrseq = <&emmc_pwrseq>; +}; + +&mcasp0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; + + op-mode = <0>; /* MCASP_ISS_MODE */ + tdm-slots = <2>; + serial-dir = < + 2 0 1 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; + +#include "tps65217.dtsi" + +&tps { + ti,pmic-shutdown-controller; + + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + regulators { + dcdc1_reg: regulator@0 { + /* VDDS_DDR */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + /* VRTC / VIO / VDDS*/ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: regulator@4 { + /* VDD_3V3AUX */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo3_reg: regulator@5 { + /* VDD_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + /* VDD_3V3A */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; +}; diff --git a/dts/src/arm/am3517.dtsi b/dts/src/arm/am3517.dtsi index f164dce087..5e3f5e86ff 100644 --- a/dts/src/arm/am3517.dtsi +++ b/dts/src/arm/am3517.dtsi @@ -60,6 +60,17 @@ dma-names = "tx", "rx"; clock-frequency = <48000000>; }; + + omap3_pmx_core2: pinmux@480025d8 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025d8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; }; }; diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts index 26956cb508..84aa30c323 100644 --- a/dts/src/arm/am437x-gp-evm.dts +++ b/dts/src/arm/am437x-gp-evm.dts @@ -21,6 +21,7 @@ aliases { display0 = &lcd0; + serial3 = &uart3; }; vmmcsd_fixed: fixedregulator-sd { @@ -42,6 +43,15 @@ gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; }; + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; @@ -106,9 +116,21 @@ }; }; }; + + /* fixed 12MHz oscillator */ + refclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; &am43xx_pinmux { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wlan_pins_default>; + pinctrl-1 = <&wlan_pins_sleep>; + i2c0_pins: i2c0_pins { pinctrl-single,pins = < 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ @@ -340,6 +362,53 @@ 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ >; }; + + mmc3_pins_default: pinmux_mmc3_pins_default { + pinctrl-single,pins = < + 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + pinctrl-single,pins = < + 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ + >; + }; + + wlan_pins_default: pinmux_wlan_pins_default { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + >; + }; + + uart3_pins: uart3_pins { + pinctrl-single,pins = < + 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ + 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ + 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ + 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ + >; + }; }; &i2c0 { @@ -403,6 +472,21 @@ regulator-always-on; }; }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_0: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; }; &i2c1 { @@ -422,6 +506,21 @@ touchscreen-size-x = <1024>; touchscreen-size-y = <600>; }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&refclk 0>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; }; &epwmss0 { @@ -446,6 +545,10 @@ status = "okay"; }; +&gpio1 { + status = "okay"; +}; + &gpio3 { status = "okay"; }; @@ -468,6 +571,43 @@ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; +&mmc3 { + status = "okay"; + /* these are on the crossbar and are outlined in the + xbar-event-map element */ + dmas = <&edma 30 + &edma 31>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_sleep>; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 30 + 2 31>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + &usb2_phy1 { status = "okay"; }; @@ -625,7 +765,7 @@ port { vpfe0_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; @@ -642,7 +782,7 @@ port { vpfe1_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_0>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; diff --git a/dts/src/arm/am57xx-beagle-x15.dts b/dts/src/arm/am57xx-beagle-x15.dts index 7128fad991..a42cc377a8 100644 --- a/dts/src/arm/am57xx-beagle-x15.dts +++ b/dts/src/arm/am57xx-beagle-x15.dts @@ -19,6 +19,7 @@ rtc0 = &mcp_rtc; rtc1 = &tps659038_rtc; rtc2 = &rtc; + display0 = &hdmi0; }; memory { @@ -103,6 +104,51 @@ pinctrl-names = "default"; pinctrl-0 = <&extcon_usb2_pins>; }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + pinctrl-names = "default"; + pinctrl-0 = <&tpd12s015_pins>; + + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &dra7_pmx_core { @@ -122,6 +168,13 @@ >; }; + hdmi_pins: pinmux_hdmi_pins { + pinctrl-single,pins = < + 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ + >; + }; + i2c3_pins_default: i2c3_pins_default { pinctrl-single,pins = < 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ @@ -278,6 +331,14 @@ 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */ >; }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ + 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ + 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ + >; + }; }; &i2c1 { @@ -608,3 +669,23 @@ }; }; }; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo3_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/dts/src/arm/arm-realview-pb1176.dts b/dts/src/arm/arm-realview-pb1176.dts index ff26c7ed8c..1bc64cda81 100644 --- a/dts/src/arm/arm-realview-pb1176.dts +++ b/dts/src/arm/arm-realview-pb1176.dts @@ -114,7 +114,7 @@ ranges; syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon"; + compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; reg = <0x10000000 0x1000>; led@08.0 { diff --git a/dts/src/arm/armada-370-db.dts b/dts/src/arm/armada-370-db.dts index 19f3bf2719..03542f7b5b 100644 --- a/dts/src/arm/armada-370-db.dts +++ b/dts/src/arm/armada-370-db.dts @@ -162,7 +162,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mx25l25635e"; + compatible = "mx25l25635e", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <50000000>; }; diff --git a/dts/src/arm/armada-370-dlink-dns327l.dts b/dts/src/arm/armada-370-dlink-dns327l.dts new file mode 100644 index 0000000000..af4dc548c1 --- /dev/null +++ b/dts/src/arm/armada-370-dlink-dns327l.dts @@ -0,0 +1,357 @@ +/* + * Device Tree file for D-Link DNS-327L + * + * Copyright (C) 2015, Andrew Andrianov + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* Remaining unsolved: + * There's still some unknown device on i2c address 0x13 + */ + +/dts-v1/; + +#include +#include +#include "armada-370.dtsi" + +/ { + model = "D-Link DNS-327L"; + compatible = "dlink,dns327l", + "marvell,armada370", + "marvell,armada-370-xp"; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MiB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + usb@50000 { + status = "okay"; + }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partition@0 { + label = "u-boot"; + /* 1.0 MiB */ + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + /* 128 KiB */ + reg = <0x100000 0x20000>; + read-only; + }; + + partition@120000 { + label = "uImage"; + /* 7 MiB */ + reg = <0x120000 0x700000>; + }; + + partition@820000 { + label = "ubifs"; + /* ~ 84 MiB */ + reg = <0x820000 0x54e0000>; + }; + + /* Hardcoded into stock bootloader */ + partition@5d00000 { + label = "failsafe-uImage"; + /* 5 MiB */ + reg = <0x5d00000 0x500000>; + }; + + partition@6200000 { + label = "failsafe-fs"; + /* 29 MiB */ + reg = <0x6200000 0x1d00000>; + }; + + partition@7f00000 { + label = "bbt"; + /* 1 MiB for BBT */ + reg = <0x7f00000 0x100000>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = < + &backup_button_pin + &power_button_pin + &reset_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < + &sata_l_amber_pin + &sata_r_amber_pin + &backup_led_pin + /* Ensure these are managed by hardware */ + &sata_l_white_pin + &sata_r_white_pin>; + + pinctrl-names = "default"; + + sata-r-amber-pin { + label = "dns327l:amber:sata-r"; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + sata-l-amber-pin { + label = "dns327l:amber:sata-l"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + backup-led-pin { + label = "dns327l:white:usb"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-0 = <&xhci_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "USB3.0 Port Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + sata_r_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-0 = <&sata_r_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-R Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; + + sata_l_power: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-0 = <&sata_l_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-L Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata_l_white_pin: sata-l-white-pin { + marvell,pins = "mpp57"; + marvell,function = "sata0"; + }; + + sata_r_white_pin: sata-r-white-pin { + marvell,pins = "mpp55"; + marvell,function = "sata1"; + }; + + sata_r_amber_pin: sata-r-amber-pin { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + + sata_l_amber_pin: sata-l-amber-pin { + marvell,pins = "mpp53"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp61"; + marvell,function = "gpo"; + }; + + xhci_pwr_pin: xhci-pwr-pin { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + sata_r_pwr_pin: sata-r-pwr-pin { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + sata_l_pwr_pin: sata-l-pwr-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp60", "mpp61"; + marvell,function = "uart1"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; +}; + +/* Serial console */ +&uart0 { + status = "okay"; +}; + +/* Connected to Weltrend MCU */ +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + marvell,reg-init = <0x0 0x16 0x0 0x0002>, + <0x0 0x19 0x0 0x0077>, + <0x0 0x18 0x0 0x5747>; + }; +}; + +ð1 { + phy = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <100000>; + status = "okay"; +}; diff --git a/dts/src/arm/armada-370-synology-ds213j.dts b/dts/src/arm/armada-370-synology-ds213j.dts index b42b767763..4f4924362b 100644 --- a/dts/src/arm/armada-370-synology-ds213j.dts +++ b/dts/src/arm/armada-370-synology-ds213j.dts @@ -92,7 +92,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q064"; + compatible = "micron,n25q064", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <20000000>; diff --git a/dts/src/arm/armada-370-xp.dtsi b/dts/src/arm/armada-370-xp.dtsi index ec96f0b363..a718866ba5 100644 --- a/dts/src/arm/armada-370-xp.dtsi +++ b/dts/src/arm/armada-370-xp.dtsi @@ -149,7 +149,6 @@ }; spi0: spi@10600 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10600 0x28>; #address-cells = <1>; #size-cells = <0>; @@ -160,7 +159,6 @@ }; spi1: spi@10680 { - compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10680 0x28>; #address-cells = <1>; #size-cells = <0>; @@ -270,7 +268,6 @@ }; eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; @@ -286,7 +283,6 @@ }; eth1: ethernet@74000 { - compatible = "marvell,armada-370-neta"; reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi index 00b50db57c..53a1a5abe1 100644 --- a/dts/src/arm/armada-370.dtsi +++ b/dts/src/arm/armada-370.dtsi @@ -139,11 +139,15 @@ * board level if a different configuration is used. */ spi0: spi@10600 { + compatible = "marvell,armada-370-spi", + "marvell,orion-spi"; pinctrl-0 = <&spi0_pins1>; pinctrl-names = "default"; }; spi1: spi@10680 { + compatible = "marvell,armada-370-spi", + "marvell,orion-spi"; pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; }; @@ -307,6 +311,14 @@ dmacap,memset; }; }; + + ethernet@70000 { + compatible = "marvell,armada-370-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-370-neta"; + }; }; }; }; diff --git a/dts/src/arm/armada-375-db.dts b/dts/src/arm/armada-375-db.dts index 4eabc9c21f..5711b97e87 100644 --- a/dts/src/arm/armada-375-db.dts +++ b/dts/src/arm/armada-375-db.dts @@ -81,7 +81,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a13"; + compatible = "n25q128a13", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi index f076ff856d..67a0ab0f71 100644 --- a/dts/src/arm/armada-375.dtsi +++ b/dts/src/arm/armada-375.dtsi @@ -238,7 +238,8 @@ }; spi0: spi@10600 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-375-spi", + "marvell,orion-spi"; reg = <0x10600 0x50>; #address-cells = <1>; #size-cells = <0>; @@ -249,7 +250,8 @@ }; spi1: spi@10680 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-375-spi", + "marvell,orion-spi"; reg = <0x10680 0x50>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/armada-385-db-ap.dts b/dts/src/arm/armada-385-db-ap.dts index 7219ac3a3d..89f5a95954 100644 --- a/dts/src/arm/armada-385-db-ap.dts +++ b/dts/src/arm/armada-385-db-ap.dts @@ -70,7 +70,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p128"; + compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <54000000>; }; diff --git a/dts/src/arm/armada-385-linksys-caiman.dts b/dts/src/arm/armada-385-linksys-caiman.dts new file mode 100644 index 0000000000..f3cee918d2 --- /dev/null +++ b/dts/src/arm/armada-385-linksys-caiman.dts @@ -0,0 +1,114 @@ +/* + * Device Tree include for the Linksys WRT1200AC (Caiman) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1200AC"; + compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "caiman:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "caiman:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "caiman:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "caiman:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "caiman:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "caiman:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "caiman:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "caiman:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "caiman:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "caiman:white:power"; + }; + + sata { + label = "caiman:white:sata"; + }; + }; +}; diff --git a/dts/src/arm/armada-385-linksys-cobra.dts b/dts/src/arm/armada-385-linksys-cobra.dts new file mode 100644 index 0000000000..1110718605 --- /dev/null +++ b/dts/src/arm/armada-385-linksys-cobra.dts @@ -0,0 +1,114 @@ +/* + * Device Tree file for the Linksys WRT1900ACv2 (Cobra) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACv2"; + compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "cobra:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "cobra:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "cobra:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "cobra:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "cobra:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "cobra:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "cobra:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "cobra:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "cobra:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "cobra:white:power"; + }; + + sata { + label = "cobra:white:sata"; + }; + }; +}; diff --git a/dts/src/arm/armada-385-linksys.dtsi b/dts/src/arm/armada-385-linksys.dtsi new file mode 100644 index 0000000000..74a9c6b54f --- /dev/null +++ b/dts/src/arm/armada-385-linksys.dtsi @@ -0,0 +1,332 @@ +/* + * Device Tree include file for Armada 385 based Linksys boards + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Linksys boards based on Armada 385"; + compatible = "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + spi@10600 { + status = "disabled"; + }; + + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9635"; + reg = <0x68>; + }; + }; + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + status = "okay"; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MB */ + }; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Marvell 88W8864, 5GHz-only */ + status = "okay"; + }; + + pcie@2,0 { + /* Marvell 88W8864, 2GHz-only */ + status = "okay"; + }; + }; + }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin &sata_led_pin>; + pinctrl-names = "default"; + + power { + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sata { + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð2>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&pinctrl { + keys_pin: keys-pin { + marvell,pins = "mpp24", "mpp47"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + sata_led_pin: sata-led-pin { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; +}; diff --git a/dts/src/arm/armada-388-db.dts b/dts/src/arm/armada-388-db.dts index 51d1623de5..91ac8c118f 100644 --- a/dts/src/arm/armada-388-db.dts +++ b/dts/src/arm/armada-388-db.dts @@ -73,7 +73,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "w25q32"; + compatible = "w25q32", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts index 78514ab0b4..fd4f6fd8a2 100644 --- a/dts/src/arm/armada-388-gp.dts +++ b/dts/src/arm/armada-388-gp.dts @@ -69,7 +69,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p128"; + compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <50000000>; m25p,fast-read; diff --git a/dts/src/arm/armada-388-rd.dts b/dts/src/arm/armada-388-rd.dts index 1dc6e2341c..b657b1687e 100644 --- a/dts/src/arm/armada-388-rd.dts +++ b/dts/src/arm/armada-388-rd.dts @@ -74,7 +74,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p128"; + compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi index 218a2acd36..04ecfe6e2b 100644 --- a/dts/src/arm/armada-38x.dtsi +++ b/dts/src/arm/armada-38x.dtsi @@ -167,7 +167,8 @@ }; spi0: spi@10600 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; reg = <0x10600 0x50>; #address-cells = <1>; #size-cells = <0>; @@ -178,7 +179,8 @@ }; spi1: spi@10680 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; reg = <0x10680 0x50>; #address-cells = <1>; #size-cells = <0>; @@ -495,7 +497,7 @@ status = "disabled"; }; - mdio@72004 { + mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; diff --git a/dts/src/arm/armada-398-db.dts b/dts/src/arm/armada-398-db.dts index bbf83756c4..788c3badb6 100644 --- a/dts/src/arm/armada-398-db.dts +++ b/dts/src/arm/armada-398-db.dts @@ -73,7 +73,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <0>; - compatible = "n25q128a13"; + compatible = "n25q128a13", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi index ecd1318109..fc9864f85f 100644 --- a/dts/src/arm/armada-39x.dtsi +++ b/dts/src/arm/armada-39x.dtsi @@ -128,7 +128,8 @@ }; spi0: spi@10600 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; reg = <0x10600 0x50>; #address-cells = <1>; #size-cells = <0>; @@ -139,7 +140,8 @@ }; spi1: spi@10680 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; reg = <0x10680 0x50>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/armada-xp-axpwifiap.dts b/dts/src/arm/armada-xp-axpwifiap.dts index dfd782b44e..60bbfe32bb 100644 --- a/dts/src/arm/armada-xp-axpwifiap.dts +++ b/dts/src/arm/armada-xp-axpwifiap.dts @@ -140,7 +140,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a13"; + compatible = "n25q128a13", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; diff --git a/dts/src/arm/armada-xp-db.dts b/dts/src/arm/armada-xp-db.dts index 1037824076..7dd900f158 100644 --- a/dts/src/arm/armada-xp-db.dts +++ b/dts/src/arm/armada-xp-db.dts @@ -222,7 +222,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "m25p64"; + compatible = "m25p64", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <20000000>; }; diff --git a/dts/src/arm/armada-xp-gp.dts b/dts/src/arm/armada-xp-gp.dts index 565227eacf..bf724ca96a 100644 --- a/dts/src/arm/armada-xp-gp.dts +++ b/dts/src/arm/armada-xp-gp.dts @@ -227,7 +227,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a13"; + compatible = "n25q128a13", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; diff --git a/dts/src/arm/armada-xp-mv78260.dtsi b/dts/src/arm/armada-xp-mv78260.dtsi index 8479fdc9e9..c5fdc99f0d 100644 --- a/dts/src/arm/armada-xp-mv78260.dtsi +++ b/dts/src/arm/armada-xp-mv78260.dtsi @@ -318,7 +318,7 @@ }; eth3: ethernet@34000 { - compatible = "marvell,armada-370-neta"; + compatible = "marvell,armada-xp-neta"; reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; diff --git a/dts/src/arm/armada-xp-mv78460.dtsi b/dts/src/arm/armada-xp-mv78460.dtsi index 661d54c815..0e24f1a385 100644 --- a/dts/src/arm/armada-xp-mv78460.dtsi +++ b/dts/src/arm/armada-xp-mv78460.dtsi @@ -356,7 +356,7 @@ }; eth3: ethernet@34000 { - compatible = "marvell,armada-370-neta"; + compatible = "marvell,armada-xp-neta"; reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; diff --git a/dts/src/arm/armada-xp-synology-ds414.dts b/dts/src/arm/armada-xp-synology-ds414.dts index 6063428fa6..20267ad2f6 100644 --- a/dts/src/arm/armada-xp-synology-ds414.dts +++ b/dts/src/arm/armada-xp-synology-ds414.dts @@ -114,7 +114,7 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q064"; + compatible = "micron,n25q064", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <20000000>; diff --git a/dts/src/arm/armada-xp.dtsi b/dts/src/arm/armada-xp.dtsi index 013d63f69e..3de9b761cc 100644 --- a/dts/src/arm/armada-xp.dtsi +++ b/dts/src/arm/armada-xp.dtsi @@ -85,10 +85,18 @@ }; spi0: spi@10600 { + compatible = "marvell,armada-xp-spi", + "marvell,orion-spi"; pinctrl-0 = <&spi0_pins>; pinctrl-names = "default"; }; + spi1: spi@10680 { + compatible = "marvell,armada-xp-spi", + "marvell,orion-spi"; + }; + + i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; @@ -177,7 +185,7 @@ }; eth2: ethernet@30000 { - compatible = "marvell,armada-370-neta"; + compatible = "marvell,armada-xp-neta"; reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; @@ -220,6 +228,14 @@ }; }; + ethernet@70000 { + compatible = "marvell,armada-xp-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-xp-neta"; + }; + xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 @@ -289,7 +305,7 @@ spi0_pins: spi0-pins { marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; - marvell,function = "spi"; + marvell,function = "spi0"; }; uart2_pins: uart2-pins { diff --git a/dts/src/arm/armv7-m.dtsi b/dts/src/arm/armv7-m.dtsi index 5a660d0faf..b1ad7cf6ac 100644 --- a/dts/src/arm/armv7-m.dtsi +++ b/dts/src/arm/armv7-m.dtsi @@ -8,6 +8,12 @@ reg = <0xe000e100 0xc00>; }; + systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/at91-ariettag25.dts b/dts/src/arm/at91-ariettag25.dts new file mode 100644 index 0000000000..c514502081 --- /dev/null +++ b/dts/src/arm/at91-ariettag25.dts @@ -0,0 +1,79 @@ +/* + * Device Tree file for Arietta G25 + * This device tree is minimal, to activate more peripherals, see: + * http://dts.acmesystems.it/arietta/ + */ +/dts-v1/; +#include "at91sam9g25.dtsi" +/ { + model = "Acme Systems Arietta G25"; + compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9"; + + aliases { + serial0 = &dbgu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + usb2: gadget@f803c000 { + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + arietta_led { + label = "arietta_led"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/dts/src/arm/at91-kizbox.dts b/dts/src/arm/at91-kizbox.dts new file mode 100644 index 0000000000..bf18ece0c0 --- /dev/null +++ b/dts/src/arm/at91-kizbox.dts @@ -0,0 +1,159 @@ +/* + * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board + * + * Copyright (C) 2012-2014 Boris BREZILLON + * 2014-2015 Gaël PORTAY + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g20.dtsi" +#include + +/ { + model = "Overkiz Kizbox"; + compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x2000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + macb0: ethernet@fffc4000 { + phy-mode = "mii"; + pinctrl-0 = <&pinctrl_macb_rmii + &pinctrl_macb_rmii_mii_alt>; + status = "okay"; + }; + + usart3: serial@fffd0000 { + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + watchdog@fffffd40 { + timeout-sec = <15>; + atmel,max-heartbeat-sec = <16>; + atmel,min-heartbeat-sec = <0>; + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <1>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + status = "okay"; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + reset { + label = "PB_RST"; + gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + + user { + label = "PB_USER"; + gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; + linux,code = <0x101>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + + network_green { + label = "pwm:green:network"; + pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + network_red { + label = "pwm:red:network"; + pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + user_green { + label = "pwm:green:user"; + pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + user_red { + label = "pwm:red:user"; + pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; + + tcb_pwm: pwm { + compatible = "atmel,tcb-pwm"; + #pwm-cells = <3>; + tc-block = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa0 + &pinctrl_tcb1_tioa1 + &pinctrl_tcb1_tioa2 + &pinctrl_tcb1_tiob0>; + }; +}; diff --git a/dts/src/arm/at91-kizbox2.dts b/dts/src/arm/at91-kizbox2.dts new file mode 100644 index 0000000000..f0b1563cb3 --- /dev/null +++ b/dts/src/arm/at91-kizbox2.dts @@ -0,0 +1,216 @@ +/* + * at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board + * + * Copyright (C) 2014 Gaël PORTAY + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d31.dtsi" +#include + +/ { + model = "Overkiz Kizbox 2"; + compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + i2c1: i2c@f0018000 { + status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "okay"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vled_reg: LDO_REG3 { + regulator-name = "VLED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v8_rf_reg: LDO_REG4 { + regulator-name = "V3V8_RF"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-always-on; + }; + }; + }; + }; + + usart0: serial@f001c000 { + status = "okay"; + }; + + usart1: serial@f0020000 { + status = "okay"; + }; + + pwm0: pwm@f002c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_1 + &pinctrl_pwm0_pwmh1_1 + &pinctrl_pwm0_pwmh2_0>; + status = "okay"; + }; + + adc0: adc@f8018000 { + atmel,adc-vref = <3333>; + status = "okay"; + }; + + usart2: serial@f8020000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + dbgu: serial@ffffee00 { + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb1: ohci@00600000 { + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + prog { + label = "PB_PROG"; + gpios = <&pioE 27 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + gpio-key,wakeup; + }; + + reset { + label = "PB_RST"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + + user { + label = "PB_USER"; + gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; + linux,code = <0x101>; + gpio-key,wakeup; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + + blue { + label = "pwm:blue:user"; + pwms = <&pwm0 2 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + green { + label = "pwm:green:user"; + pwms = <&pwm0 1 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + red { + label = "pwm:red:user"; + pwms = <&pwm0 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; +}; diff --git a/dts/src/arm/at91-kizboxmini.dts b/dts/src/arm/at91-kizboxmini.dts new file mode 100644 index 0000000000..9f72b49326 --- /dev/null +++ b/dts/src/arm/at91-kizboxmini.dts @@ -0,0 +1,129 @@ +/* + * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board + * + * Copyright (C) 2014 Gaël PORTAY + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g25.dtsi" +#include + +/ { + model = "Overkiz Kizbox mini"; + compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=ubi"; + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + usart0: serial@f801c000 { + status = "okay"; + }; + + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + pwm0: pwm@f8034000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm0_1 + &pinctrl_pwm0_pwm1_1>; + status = "okay"; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + num-ports = <1>; + status = "okay"; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x20000>; + }; + + ubi@20000 { + label = "ubi"; + reg = <0x20000 0x7fe0000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + prog { + label = "PB_PROG"; + gpios = <&pioC 17 GPIO_ACTIVE_LOW>; + linux,code = <0x102>; + gpio-key,wakeup; + }; + + reset { + label = "PB_RST"; + gpios = <&pioC 16 GPIO_ACTIVE_LOW>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + + green { + label = "pwm:green:user"; + pwms = <&pwm0 0 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + + red { + label = "pwm:red:user"; + pwms = <&pwm0 1 10000000 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; +}; diff --git a/dts/src/arm/at91-sama5d3_xplained.dts b/dts/src/arm/at91-sama5d3_xplained.dts index 9991240b74..d81474e0bc 100644 --- a/dts/src/arm/at91-sama5d3_xplained.dts +++ b/dts/src/arm/at91-sama5d3_xplained.dts @@ -14,7 +14,7 @@ compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; chosen { - bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; memory { @@ -35,6 +35,8 @@ apb { mmc0: mmc@f0000000 { pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; status = "okay"; slot@0 { reg = <0>; @@ -43,6 +45,17 @@ }; }; + mmc1: mmc@f8000000 { + vmmc-supply = <&vcc_3v3_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "disabled"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; + }; + }; + spi0: spi@f0004000 { cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; status = "okay"; @@ -105,7 +118,13 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; }; pwm0: pwm@f002c000 { @@ -215,12 +234,6 @@ }; }; }; - - pmc: pmc@fffffc00 { - main: mainck { - clock-frequency = <12000000>; - }; - }; }; nand0: nand@60000000 { @@ -284,6 +297,14 @@ }; }; + vcc_mmc0_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + gpio_keys { compatible = "gpio-keys"; diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts index c740e1a2a3..22ad7c9591 100644 --- a/dts/src/arm/at91-sama5d4_xplained.dts +++ b/dts/src/arm/at91-sama5d4_xplained.dts @@ -50,7 +50,8 @@ compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; chosen { - bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk"; + bootargs = "ignore_loglevel earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -106,6 +107,8 @@ mmc1: mmc@fc000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; status = "okay"; slot@0 { reg = <0>; @@ -122,6 +125,11 @@ status = "okay"; }; + spi1: spi@fc018000 { + cs-gpios = <&pioB 21 0>; + status = "okay"; + }; + adc0: adc@fc034000 { atmel,adc-vref = <3300>; status = "okay"; @@ -238,4 +246,22 @@ linux,default-trigger = "heartbeat"; }; }; + + vcc_3v3_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_mmc1_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + gpio = <&pioE 4 GPIO_ACTIVE_LOW>; + regulator-name = "VDD MCI1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + }; }; diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts index 89ef4a540d..d782f2926b 100644 --- a/dts/src/arm/at91-sama5d4ek.dts +++ b/dts/src/arm/at91-sama5d4ek.dts @@ -50,7 +50,8 @@ compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; chosen { - bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk"; + bootargs = "ignore_loglevel earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -108,8 +109,8 @@ mmc0: mmc@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; - slot@1 { - reg = <1>; + slot@0 { + reg = <0>; bus-width = <4>; cd-gpios = <&pioE 5 0>; }; diff --git a/dts/src/arm/at91rm9200.dtsi b/dts/src/arm/at91rm9200.dtsi index 4fb333bd1f..e3cfb9972f 100644 --- a/dts/src/arm/at91rm9200.dtsi +++ b/dts/src/arm/at91rm9200.dtsi @@ -92,7 +92,7 @@ }; ramc0: ramc@ffffff00 { - compatible = "atmel,at91rm9200-sdramc"; + compatible = "atmel,at91rm9200-sdramc", "syscon"; reg = <0xffffff00 0x100>; }; @@ -940,8 +940,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91rm9200ek.dts b/dts/src/arm/at91rm9200ek.dts index 2a5d21247d..8dab4b75ca 100644 --- a/dts/src/arm/at91rm9200ek.dts +++ b/dts/src/arm/at91rm9200ek.dts @@ -12,6 +12,10 @@ model = "Atmel AT91RM9200 evaluation kit"; compatible = "atmel,at91rm9200ek", "atmel,at91rm9200"; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x20000000 0x4000000>; }; diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi index d88fe62a2b..4bc3475491 100644 --- a/dts/src/arm/at91sam9260.dtsi +++ b/dts/src/arm/at91sam9260.dtsi @@ -1008,8 +1008,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91sam9261.dtsi b/dts/src/arm/at91sam9261.dtsi index bf8d1856a5..b2c44a07a3 100644 --- a/dts/src/arm/at91sam9261.dtsi +++ b/dts/src/arm/at91sam9261.dtsi @@ -75,8 +75,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&ohci_clk>, <&hclk0>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; diff --git a/dts/src/arm/at91sam9261ek.dts b/dts/src/arm/at91sam9261ek.dts index f4a765729c..2e92ac020f 100644 --- a/dts/src/arm/at91sam9261ek.dts +++ b/dts/src/arm/at91sam9261ek.dts @@ -13,7 +13,8 @@ compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; chosen { - bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi index 111889b556..e36d966ef5 100644 --- a/dts/src/arm/at91sam9263.dtsi +++ b/dts/src/arm/at91sam9263.dtsi @@ -1010,8 +1010,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91sam9263ek.dts b/dts/src/arm/at91sam9263ek.dts index 5cf93eecd8..23381276ff 100644 --- a/dts/src/arm/at91sam9263ek.dts +++ b/dts/src/arm/at91sam9263ek.dts @@ -13,7 +13,8 @@ compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/dts/src/arm/at91sam9g20ek_common.dtsi b/dts/src/arm/at91sam9g20ek_common.dtsi index dfaacb113f..57548a2c5a 100644 --- a/dts/src/arm/at91sam9g20ek_common.dtsi +++ b/dts/src/arm/at91sam9g20ek_common.dtsi @@ -10,7 +10,8 @@ / { chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi index 70e59c5ceb..18177f5a74 100644 --- a/dts/src/arm/at91sam9g45.dtsi +++ b/dts/src/arm/at91sam9g45.dtsi @@ -1148,7 +1148,7 @@ usb2: gadget@fff78000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; + compatible = "atmel,at91sam9g45-udc"; reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1291,8 +1291,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1300,8 +1300,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts index 33ce7ca2c4..1375d33626 100644 --- a/dts/src/arm/at91sam9m10g45ek.dts +++ b/dts/src/arm/at91sam9m10g45ek.dts @@ -15,7 +15,8 @@ compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; + bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi index a9e35dfc12..5c2a8c8c8b 100644 --- a/dts/src/arm/at91sam9n12.dtsi +++ b/dts/src/arm/at91sam9n12.dtsi @@ -949,9 +949,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, - <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts index 6e067c8a35..eab17fcace 100644 --- a/dts/src/arm/at91sam9n12ek.dts +++ b/dts/src/arm/at91sam9n12ek.dts @@ -14,7 +14,8 @@ compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; + bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi index ebfd5ce9cb..c9920c6479 100644 --- a/dts/src/arm/at91sam9rl.dtsi +++ b/dts/src/arm/at91sam9rl.dtsi @@ -1065,13 +1065,6 @@ }; }; - rtc@fffffeb0 { - compatible = "atmel,at91rm9200-rtc"; - reg = <0xfffffeb0 0x40>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - status = "disabled"; - }; - rtc@fffffd20 { compatible = "atmel,at91sam9260-rtt"; reg = <0xfffffd20 0x10>; @@ -1085,6 +1078,14 @@ reg = <0xfffffd60 0x10>; status = "disabled"; }; + + rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + }; }; diff --git a/dts/src/arm/at91sam9rlek.dts b/dts/src/arm/at91sam9rlek.dts index 9be5b540ee..558c9f220b 100644 --- a/dts/src/arm/at91sam9rlek.dts +++ b/dts/src/arm/at91sam9rlek.dts @@ -13,7 +13,8 @@ compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; chosen { - bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; + bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; + stdout-path = "serial0:115200n8"; }; memory { @@ -181,13 +182,11 @@ }; }; - pmc: pmc@fffffc00 { - main: mainck { - clock-frequency = <12000000>; - }; + watchdog@fffffd40 { + status = "okay"; }; - watchdog@fffffd40 { + rtc@fffffe00 { status = "okay"; }; }; diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi index 3aa56ae341..b6c8df8d38 100644 --- a/dts/src/arm/at91sam9x5.dtsi +++ b/dts/src/arm/at91sam9x5.dtsi @@ -505,7 +505,7 @@ pinctrl_usart1_sck: usart1_sck-0 { atmel,pins = - ; /* PC29 periph C */ + ; /* PC29 periph C */ }; }; @@ -694,6 +694,52 @@ }; }; + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = + ; + }; + }; + tcb0 { pinctrl_tcb0_tclk0: tcb0_tclk0-0 { atmel,pins = ; @@ -1062,7 +1108,7 @@ usb2: gadget@f803c000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; + compatible = "atmel,at91sam9g45-udc"; reg = <0x00500000 0x80000 0xf803c000 0x400>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1176,8 +1222,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1185,8 +1231,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ehci_clk", "uhpck"; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; }; diff --git a/dts/src/arm/at91sam9x5ek.dtsi b/dts/src/arm/at91sam9x5ek.dtsi index cc83a37a73..d237c462df 100644 --- a/dts/src/arm/at91sam9x5ek.dtsi +++ b/dts/src/arm/at91sam9x5ek.dtsi @@ -13,7 +13,8 @@ compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; }; ahb { diff --git a/dts/src/arm/atlas7.dtsi b/dts/src/arm/atlas7.dtsi index a753178abc..5dfd3a44bf 100644 --- a/dts/src/arm/atlas7.dtsi +++ b/dts/src/arm/atlas7.dtsi @@ -38,6 +38,21 @@ }; }; + clocks { + xinw { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xinw"; + }; + xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "xin"; + }; + }; + noc { compatible = "simple-bus"; #address-cells = <1>; diff --git a/dts/src/arm/axp209.dtsi b/dts/src/arm/axp209.dtsi index c20cf537f5..24c935c72e 100644 --- a/dts/src/arm/axp209.dtsi +++ b/dts/src/arm/axp209.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi index 7b52c33ea6..e1ac07a16f 100644 --- a/dts/src/arm/bcm-cygnus.dtsi +++ b/dts/src/arm/bcm-cygnus.dtsi @@ -212,6 +212,18 @@ status = "disabled"; }; + nand: nand@18046000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + gic: interrupt-controller@19021000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; diff --git a/dts/src/arm/bcm2835-rpi-b-plus.dts b/dts/src/arm/bcm2835-rpi-b-plus.dts index e479515099..668442b1bd 100644 --- a/dts/src/arm/bcm2835-rpi-b-plus.dts +++ b/dts/src/arm/bcm2835-rpi-b-plus.dts @@ -1,5 +1,5 @@ /dts-v1/; -/include/ "bcm2835-rpi.dtsi" +#include "bcm2835-rpi.dtsi" / { compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; @@ -25,6 +25,6 @@ /* I2S interface */ i2s_alt0: i2s_alt0 { brcm,pins = <18 19 20 21>; - brcm,function = <4>; /* alt0 */ + brcm,function = ; }; }; diff --git a/dts/src/arm/bcm2835-rpi-b.dts b/dts/src/arm/bcm2835-rpi-b.dts index bafa46fc22..ee89b79426 100644 --- a/dts/src/arm/bcm2835-rpi-b.dts +++ b/dts/src/arm/bcm2835-rpi-b.dts @@ -1,5 +1,5 @@ /dts-v1/; -/include/ "bcm2835-rpi.dtsi" +#include "bcm2835-rpi.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; @@ -18,6 +18,6 @@ /* I2S interface */ i2s_alt2: i2s_alt2 { brcm,pins = <28 29 30 31>; - brcm,function = <6>; /* alt2 */ + brcm,function = ; }; }; diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi index c706448701..46780bb48b 100644 --- a/dts/src/arm/bcm2835-rpi.dtsi +++ b/dts/src/arm/bcm2835-rpi.dtsi @@ -1,4 +1,4 @@ -/include/ "bcm2835.dtsi" +#include "bcm2835.dtsi" / { memory { @@ -21,17 +21,17 @@ gpioout: gpioout { brcm,pins = <6>; - brcm,function = <1>; /* GPIO out */ + brcm,function = ; }; alt0: alt0 { brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; - brcm,function = <4>; /* alt0 */ + brcm,function = ; }; alt3: alt3 { brcm,pins = <48 49 50 51 52 53>; - brcm,function = <7>; /* alt3 */ + brcm,function = ; }; }; diff --git a/dts/src/arm/bcm2835.dtsi b/dts/src/arm/bcm2835.dtsi index 3342cb1407..301c73f4ca 100644 --- a/dts/src/arm/bcm2835.dtsi +++ b/dts/src/arm/bcm2835.dtsi @@ -1,4 +1,5 @@ -/include/ "skeleton.dtsi" +#include +#include "skeleton.dtsi" / { compatible = "brcm,bcm2835"; @@ -14,6 +15,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x7e000000 0x20000000 0x02000000>; + dma-ranges = <0x40000000 0x00000000 0x20000000>; timer@7e003000 { compatible = "brcm,bcm2835-system-timer"; @@ -60,6 +62,13 @@ reg = <0x7e104000 0x10>; }; + mailbox: mailbox@7e00b800 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; + #mbox-cells = <0>; + }; + gpio: gpio@7e200000 { compatible = "brcm,bcm2835-gpio"; reg = <0x7e200000 0xb4>; @@ -112,7 +121,7 @@ status = "disabled"; }; - i2c0: i2c@20205000 { + i2c0: i2c@7e205000 { compatible = "brcm,bcm2835-i2c"; reg = <0x7e205000 0x1000>; interrupts = <2 21>; diff --git a/dts/src/arm/bcm4708-asus-rt-ac56u.dts b/dts/src/arm/bcm4708-asus-rt-ac56u.dts new file mode 100644 index 0000000000..112a5a834d --- /dev/null +++ b/dts/src/arm/bcm4708-asus-rt-ac56u.dts @@ -0,0 +1,97 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC56U + * + * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac56u", "brcm,bcm4708"; + model = "Asus RT-AC56U (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + all { + label = "bcm53xx:blue:all"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/arm/bcm4708-asus-rt-ac68u.dts b/dts/src/arm/bcm4708-asus-rt-ac68u.dts new file mode 100644 index 0000000000..3600f56f46 --- /dev/null +++ b/dts/src/arm/bcm4708-asus-rt-ac68u.dts @@ -0,0 +1,84 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC68U + * + * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "asus,rt-ac68u", "brcm,bcm4708"; + model = "Asus RT-AC68U (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts index b359c1e617..24f0ab59bf 100644 --- a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts +++ b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; @@ -47,6 +48,12 @@ leds { compatible = "gpio-leds"; + usb { + label = "bcm53xx:blue:usb"; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + power0 { label = "bcm53xx:red:power"; gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; diff --git a/dts/src/arm/bcm4708-luxul-xwc-1000.dts b/dts/src/arm/bcm4708-luxul-xwc-1000.dts index 946c728c4e..f039393117 100644 --- a/dts/src/arm/bcm4708-luxul-xwc-1000.dts +++ b/dts/src/arm/bcm4708-luxul-xwc-1000.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "luxul,xwc-1000", "brcm,bcm4708"; @@ -23,12 +24,8 @@ reg = <0x00000000 0x08000000>; }; - axi@18000000 { - nand@28000 { - reg = <0x00028000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - + nand: nand@18028000 { + nandcs@0 { partition@0 { label = "ubi"; reg = <0x00000000 0x08000000>; diff --git a/dts/src/arm/bcm4708-netgear-r6250.dts b/dts/src/arm/bcm4708-netgear-r6250.dts index 2ed9e57947..326ce8f4e4 100644 --- a/dts/src/arm/bcm4708-netgear-r6250.dts +++ b/dts/src/arm/bcm4708-netgear-r6250.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "netgear,r6250v1", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm4708-netgear-r6300-v2.dts b/dts/src/arm/bcm4708-netgear-r6300-v2.dts index 3991042824..3a94606d04 100644 --- a/dts/src/arm/bcm4708-netgear-r6300-v2.dts +++ b/dts/src/arm/bcm4708-netgear-r6300-v2.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "netgear,r6300v2", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm4708-smartrg-sr400ac.dts b/dts/src/arm/bcm4708-smartrg-sr400ac.dts new file mode 100644 index 0000000000..d6a033b97c --- /dev/null +++ b/dts/src/arm/bcm4708-smartrg-sr400ac.dts @@ -0,0 +1,120 @@ +/* + * Broadcom BCM470X / BCM5301X arm platform code. + * DTS for SmartRG SR400ac + * + * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "smartrg,sr400ac", "brcm,bcm4708"; + model = "SmartRG SR400ac"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb3-green { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + status-red { + label = "bcm53xx:red:status"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + status-green { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + status-blue { + label = "bcm53xx:blue:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-red { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/arm/bcm47081-asus-rt-n18u.dts b/dts/src/arm/bcm47081-asus-rt-n18u.dts index 0ee85ea10b..71b98cfaf9 100644 --- a/dts/src/arm/bcm47081-asus-rt-n18u.dts +++ b/dts/src/arm/bcm47081-asus-rt-n18u.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts index db9131e032..bb0cb0bfaf 100644 --- a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts +++ b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts b/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts index 7d6868acb1..184fd92141 100644 --- a/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts +++ b/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm47081.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm4709-asus-rt-ac87u.dts b/dts/src/arm/bcm4709-asus-rt-ac87u.dts new file mode 100644 index 0000000000..aedf3c426e --- /dev/null +++ b/dts/src/arm/bcm4709-asus-rt-ac87u.dts @@ -0,0 +1,65 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-AC87U + * + * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; + model = "Asus RT-AC87U"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + wan { + label = "bcm53xx:red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts new file mode 100644 index 0000000000..2a92e8d5ab --- /dev/null +++ b/dts/src/arm/bcm4709-buffalo-wxr-1900dhp.dts @@ -0,0 +1,128 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WXR-1900DHP + * + * Copyright (C) 2015 Felix Fietkau + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; + model = "Buffalo WXR-1900DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "bcm53xx:green:usb"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router-amber { + label = "bcm53xx:amber:router"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + router-white { + label = "bcm53xx:white:router"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wireless-amber { + label = "bcm53xx:amber:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wireless-white { + label = "bcm53xx:white:wireless"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + power { + label = "Power"; + linux,code = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + + aoss { + label = "AOSS"; + linux,code = ; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + mode { + label = "Mode"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + sw_ap { + label = "AP"; + linux,code = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + + eject { + label = "USB eject"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/arm/bcm4709-netgear-r8000.dts b/dts/src/arm/bcm4709-netgear-r8000.dts index ea26dd3ec0..446c586cd4 100644 --- a/dts/src/arm/bcm4709-netgear-r8000.dts +++ b/dts/src/arm/bcm4709-netgear-r8000.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" / { compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; diff --git a/dts/src/arm/bcm5301x-nand-cs0-bch8.dtsi b/dts/src/arm/bcm5301x-nand-cs0-bch8.dtsi new file mode 100644 index 0000000000..d10781e36f --- /dev/null +++ b/dts/src/arm/bcm5301x-nand-cs0-bch8.dtsi @@ -0,0 +1,24 @@ +/* + * Broadcom BCM470X / BCM5301X Nand chip defaults. + * + * This should be included if the NAND controller is on chip select 0 + * and uses 8 bit ECC. + * + * Copyright (C) 2015 Hauke Mehrtens + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/ { + nand@18028000 { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; + }; +}; diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi index 78aec6270c..21fefd4cdc 100644 --- a/dts/src/arm/bcm5301x.dtsi +++ b/dts/src/arm/bcm5301x.dtsi @@ -108,6 +108,30 @@ /* ChipCommon */ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + /* USB 2.0 Controller */ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, @@ -143,4 +167,16 @@ #gpio-cells = <2>; }; }; + + nand: nand@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; diff --git a/dts/src/arm/bcm63138.dtsi b/dts/src/arm/bcm63138.dtsi index f46329c8ad..34cd640512 100644 --- a/dts/src/arm/bcm63138.dtsi +++ b/dts/src/arm/bcm63138.dtsi @@ -26,6 +26,7 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0>; + enable-method = "brcm,bcm63138"; }; cpu@1 { @@ -33,6 +34,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <1>; + enable-method = "brcm,bcm63138"; + resets = <&pmb0 4 1>; }; }; @@ -105,6 +108,18 @@ reg = <0x1e620 0x20>; interrupts = ; }; + + pmb0: reset-controller@4800c0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800c0 0x10>; + #reset-cells = <2>; + }; + + pmb1: reset-controller@4800e0 { + compatible = "brcm,bcm63138-pmb"; + reg = <0x4800e0 0x10>; + #reset-cells = <2>; + }; }; /* Legacy UBUS base */ @@ -114,6 +129,11 @@ #size-cells = <1>; ranges = <0 0xfffe8000 0x8100>; + timer: timer@80 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x80 0x3c>; + }; + serial0: serial@600 { compatible = "brcm,bcm6345-uart"; reg = <0x600 0x1b>; @@ -131,5 +151,28 @@ clock-names = "periph"; status = "disabled"; }; + + nand: nand@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; + reg = <0x2000 0x600>, <0xf0 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + interrupts = ; + interrupt-names = "nand"; + }; + + bootlut: bootlut@8000 { + compatible = "brcm,bcm63138-bootlut"; + reg = <0x8000 0x50>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <1>; + }; }; }; diff --git a/dts/src/arm/bcm7445-bcm97445svmb.dts b/dts/src/arm/bcm7445-bcm97445svmb.dts index 9eec2ac111..0bb8d17e4c 100644 --- a/dts/src/arm/bcm7445-bcm97445svmb.dts +++ b/dts/src/arm/bcm7445-bcm97445svmb.dts @@ -12,3 +12,26 @@ <0x00 0x80000000 0x00 0x40000000>; }; }; + +&nand { + status = "okay"; + + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <1>; + nand-ecc-step-size = <512>; + nand-ecc-strength = <8>; + nand-on-flash-bbt; + + #size-cells = <2>; + #address-cells = <2>; + + flash1.rootfs0@0 { + reg = <0x0 0x0 0x0 0x80000000>; + }; + + flash1.rootfs1@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + }; +}; diff --git a/dts/src/arm/bcm7445.dtsi b/dts/src/arm/bcm7445.dtsi index 39ac7840d7..58dcd66625 100644 --- a/dts/src/arm/bcm7445.dtsi +++ b/dts/src/arm/bcm7445.dtsi @@ -108,6 +108,65 @@ brcm,int-map-mask = <0x25c>, <0x7000000>; brcm,int-fwd-mask = <0x70000>; }; + + hif_intr2_intc: interrupt-controller@3e1000 { + compatible = "brcm,l2-intc"; + reg = <0x3e1000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-names = "hif"; + }; + + nand: nand@3e2800 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg-names = "nand", "flash-dma"; + reg = <0x3e2800 0x600>, <0x3e3000 0x2c>; + interrupt-parent = <&hif_intr2_intc>; + interrupts = <24>, <4>; + interrupt-names = "nand_ctlrdy", "flash_dma_done"; + }; + + sata@45a000 { + compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x45a000 0xa9c>, <0x458040 0x24>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + }; + }; + + sata_phy: sata-phy@458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0x458100 0x1f00>; + reg-names = "phy"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; }; smpboot { diff --git a/dts/src/arm/bcm958300k.dts b/dts/src/arm/bcm958300k.dts index c9eb8565ea..2f63052f9d 100644 --- a/dts/src/arm/bcm958300k.dts +++ b/dts/src/arm/bcm958300k.dts @@ -58,4 +58,20 @@ uart3: serial@18023000 { status = "okay"; }; + + nand: nand@18046000 { + nandcs@1 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + }; + }; }; diff --git a/dts/src/arm/bcm963138dvt.dts b/dts/src/arm/bcm963138dvt.dts index 69c93395ec..370aa2cfdd 100644 --- a/dts/src/arm/bcm963138dvt.dts +++ b/dts/src/arm/bcm963138dvt.dts @@ -28,3 +28,15 @@ &serial1 { status = "okay"; }; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sectors-size = <16>; + }; +}; diff --git a/dts/src/arm/berlin2-sony-nsz-gs7.dts b/dts/src/arm/berlin2-sony-nsz-gs7.dts index 86d85d8896..5c99fb3a4d 100644 --- a/dts/src/arm/berlin2-sony-nsz-gs7.dts +++ b/dts/src/arm/berlin2-sony-nsz-gs7.dts @@ -3,9 +3,37 @@ * * Sebastian Hesselbarth * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/berlin2.dtsi b/dts/src/arm/berlin2.dtsi index 63d00a63cf..ef811de099 100644 --- a/dts/src/arm/berlin2.dtsi +++ b/dts/src/arm/berlin2.dtsi @@ -6,9 +6,37 @@ * based on GPL'ed 2.6 kernel sources * (c) Marvell International Ltd. * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" @@ -56,7 +84,7 @@ sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; - clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; clock-names = "io", "core"; interrupts = ; status = "disabled"; @@ -65,7 +93,7 @@ sdhci1: sdhci@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; - clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; clock-names = "io", "core"; interrupts = ; status = "disabled"; @@ -75,7 +103,7 @@ compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; - clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; clock-names = "io", "core"; pinctrl-0 = <&emmc_pmux>; pinctrl-names = "default"; @@ -105,13 +133,13 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = ; - clocks = <&chip CLKID_TWD>; + clocks = <&chip_clk CLKID_TWD>; }; eth1: ethernet@b90000 { compatible = "marvell,pxa168-eth"; reg = <0xb90000 0x10000>; - clocks = <&chip CLKID_GETH1>; + clocks = <&chip_clk CLKID_GETH1>; interrupts = ; /* set by bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -134,7 +162,7 @@ eth0: ethernet@e50000 { compatible = "marvell,pxa168-eth"; reg = <0xe50000 0x10000>; - clocks = <&chip CLKID_GETH0>; + clocks = <&chip_clk CLKID_GETH0>; interrupts = ; /* set by bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -233,7 +261,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -242,7 +270,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -251,7 +279,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -260,7 +288,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -269,7 +297,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -278,7 +306,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -287,7 +315,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -296,7 +324,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -315,7 +343,7 @@ compatible = "marvell,berlin2-ahci", "generic-ahci"; reg = <0xe90000 0x1000>; interrupts = ; - clocks = <&chip CLKID_SATA>; + clocks = <&chip_clk CLKID_SATA>; #address-cells = <1>; #size-cells = <0>; @@ -335,7 +363,7 @@ sata_phy: phy@e900a0 { compatible = "marvell,berlin2-sata-phy"; reg = <0xe900a0 0x200>; - clocks = <&chip CLKID_SATA>; + clocks = <&chip_clk CLKID_SATA>; #address-cells = <1>; #size-cells = <0>; #phy-cells = <1>; @@ -351,16 +379,28 @@ }; chip: chip-control@ea0000 { - compatible = "marvell,berlin2-chip-ctrl"; - #clock-cells = <1>; - #reset-cells = <2>; + compatible = "simple-mfd", "syscon"; reg = <0xea0000 0x400>; - clocks = <&refclk>; - clock-names = "refclk"; - emmc_pmux: emmc-pmux { - groups = "G26"; - function = "emmc"; + chip_clk: clock { + compatible = "marvell,berlin2-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2-soc-pinctrl"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; + }; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; }; }; @@ -442,22 +482,24 @@ }; sysctrl: system-controller@d000 { - compatible = "marvell,berlin2-system-ctrl"; + compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; - uart0_pmux: uart0-pmux { - groups = "GSM4"; - function = "uart0"; - }; - - uart1_pmux: uart1-pmux { - groups = "GSM5"; - function = "uart1"; - }; - - uart2_pmux: uart2-pmux { - groups = "GSM3"; - function = "uart2"; + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2-system-pinctrl"; + uart0_pmux: uart0-pmux { + groups = "GSM4"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM5"; + function = "uart1"; + }; + uart2_pmux: uart2-pmux { + groups = "GSM3"; + function = "uart2"; + }; }; }; diff --git a/dts/src/arm/berlin2cd-google-chromecast.dts b/dts/src/arm/berlin2cd-google-chromecast.dts index 30270be4d0..772165ad0a 100644 --- a/dts/src/arm/berlin2cd-google-chromecast.dts +++ b/dts/src/arm/berlin2cd-google-chromecast.dts @@ -3,9 +3,37 @@ * * Sebastian Hesselbarth * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/berlin2cd.dtsi b/dts/src/arm/berlin2cd.dtsi index 81b670ac49..900213d78a 100644 --- a/dts/src/arm/berlin2cd.dtsi +++ b/dts/src/arm/berlin2cd.dtsi @@ -6,9 +6,37 @@ * based on GPL'ed 2.6 kernel sources * (c) Marvell International Ltd. * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" @@ -53,7 +81,7 @@ sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; - clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; clock-names = "io", "core"; interrupts = ; status = "disabled"; @@ -77,14 +105,14 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = ; - clocks = <&chip CLKID_TWD>; + clocks = <&chip_clk CLKID_TWD>; }; usb_phy0: usb-phy@b74000 { compatible = "marvell,berlin2cd-usb-phy"; reg = <0xb74000 0x128>; #phy-cells = <0>; - resets = <&chip 0x178 23>; + resets = <&chip_rst 0x178 23>; status = "disabled"; }; @@ -92,14 +120,14 @@ compatible = "marvell,berlin2cd-usb-phy"; reg = <0xb78000 0x128>; #phy-cells = <0>; - resets = <&chip 0x178 24>; + resets = <&chip_rst 0x178 24>; status = "disabled"; }; eth1: ethernet@b90000 { compatible = "marvell,pxa168-eth"; reg = <0xb90000 0x10000>; - clocks = <&chip CLKID_GETH1>; + clocks = <&chip_clk CLKID_GETH1>; interrupts = ; /* set by bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -117,7 +145,7 @@ eth0: ethernet@e50000 { compatible = "marvell,pxa168-eth"; reg = <0xe50000 0x10000>; - clocks = <&chip CLKID_GETH0>; + clocks = <&chip_clk CLKID_GETH0>; interrupts = ; /* set by bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -216,7 +244,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -225,7 +253,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -234,7 +262,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -243,7 +271,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -252,7 +280,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -261,7 +289,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -270,7 +298,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -279,7 +307,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -295,16 +323,28 @@ }; chip: chip-control@ea0000 { - compatible = "marvell,berlin2cd-chip-ctrl"; - #clock-cells = <1>; - #reset-cells = <2>; + compatible = "simple-mfd", "syscon"; reg = <0xea0000 0x400>; - clocks = <&refclk>; - clock-names = "refclk"; - uart0_pmux: uart0-pmux { - groups = "G6"; - function = "uart0"; + chip_clk: clock { + compatible = "marvell,berlin2-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2cd-soc-pinctrl"; + + uart0_pmux: uart0-pmux { + groups = "G6"; + function = "uart0"; + }; + }; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; }; }; @@ -312,7 +352,7 @@ compatible = "chipidea,usb2"; reg = <0xed0000 0x200>; interrupts = ; - clocks = <&chip CLKID_USB0>; + clocks = <&chip_clk CLKID_USB0>; phys = <&usb_phy0>; phy-names = "usb-phy"; status = "disabled"; @@ -322,7 +362,7 @@ compatible = "chipidea,usb2"; reg = <0xee0000 0x200>; interrupts = ; - clocks = <&chip CLKID_USB1>; + clocks = <&chip_clk CLKID_USB1>; phys = <&usb_phy1>; phy-names = "usb-phy"; status = "disabled"; @@ -389,8 +429,12 @@ }; sysctrl: system-controller@d000 { - compatible = "marvell,berlin2cd-system-ctrl"; + compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; + + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2cd-system-pinctrl"; + }; }; sic: interrupt-controller@e000 { diff --git a/dts/src/arm/berlin2q-marvell-dmp.dts b/dts/src/arm/berlin2q-marvell-dmp.dts index a98ac1bd8f..4a749e5b3b 100644 --- a/dts/src/arm/berlin2q-marvell-dmp.dts +++ b/dts/src/arm/berlin2q-marvell-dmp.dts @@ -1,9 +1,37 @@ /* * Copyright (C) 2014 Antoine Ténart * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/berlin2q.dtsi b/dts/src/arm/berlin2q.dtsi index be5397288d..63a48490e2 100644 --- a/dts/src/arm/berlin2q.dtsi +++ b/dts/src/arm/berlin2q.dtsi @@ -1,9 +1,37 @@ /* * Copyright (C) 2014 Antoine Ténart * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include @@ -74,7 +102,7 @@ sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; - clocks = <&chip CLKID_SDIO1XIN>; + clocks = <&chip_clk CLKID_SDIO1XIN>; interrupts = ; status = "disabled"; }; @@ -82,7 +110,7 @@ sdhci1: sdhci@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; - clocks = <&chip CLKID_SDIO1XIN>; + clocks = <&chip_clk CLKID_SDIO1XIN>; interrupts = ; status = "disabled"; }; @@ -91,7 +119,7 @@ compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; - clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; clock-names = "io", "core"; status = "disabled"; }; @@ -112,7 +140,7 @@ local-timer@ad0600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; - clocks = <&chip CLKID_TWD>; + clocks = <&chip_clk CLKID_TWD>; interrupts = ; }; @@ -127,7 +155,7 @@ compatible = "marvell,berlin2-usb-phy"; reg = <0xa2f400 0x128>; #phy-cells = <0>; - resets = <&chip 0x104 14>; + resets = <&chip_rst 0x104 14>; status = "disabled"; }; @@ -135,7 +163,7 @@ compatible = "chipidea,usb2"; reg = <0xa30000 0x10000>; interrupts = ; - clocks = <&chip CLKID_USB2>; + clocks = <&chip_clk CLKID_USB2>; phys = <&usb_phy2>; phy-names = "usb-phy"; status = "disabled"; @@ -145,7 +173,7 @@ compatible = "marvell,berlin2-usb-phy"; reg = <0xb74000 0x128>; #phy-cells = <0>; - resets = <&chip 0x104 12>; + resets = <&chip_rst 0x104 12>; status = "disabled"; }; @@ -153,14 +181,14 @@ compatible = "marvell,berlin2-usb-phy"; reg = <0xb78000 0x128>; #phy-cells = <0>; - resets = <&chip 0x104 13>; + resets = <&chip_rst 0x104 13>; status = "disabled"; }; eth0: ethernet@b90000 { compatible = "marvell,pxa168-eth"; reg = <0xb90000 0x10000>; - clocks = <&chip CLKID_GETH0>; + clocks = <&chip_clk CLKID_GETH0>; interrupts = ; /* set by bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -267,7 +295,7 @@ reg = <0x1400 0x100>; interrupt-parent = <&aic>; interrupts = <4>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; pinctrl-0 = <&twsi0_pmux>; pinctrl-names = "default"; status = "disabled"; @@ -280,7 +308,7 @@ reg = <0x1800 0x100>; interrupt-parent = <&aic>; interrupts = <5>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; pinctrl-0 = <&twsi1_pmux>; pinctrl-names = "default"; status = "disabled"; @@ -289,7 +317,7 @@ timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; interrupts = <8>; }; @@ -297,14 +325,14 @@ timer1: timer@2c14 { compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; }; timer2: timer@2c28 { compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -312,7 +340,7 @@ timer3: timer@2c3c { compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -320,7 +348,7 @@ timer4: timer@2c50 { compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -328,7 +356,7 @@ timer5: timer@2c64 { compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -336,7 +364,7 @@ timer6: timer@2c78 { compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -344,7 +372,7 @@ timer7: timer@2c8c { compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; - clocks = <&chip CLKID_CFG>; + clocks = <&chip_clk CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -360,21 +388,33 @@ }; chip: chip-control@ea0000 { - compatible = "marvell,berlin2q-chip-ctrl"; - #clock-cells = <1>; - #reset-cells = <2>; + compatible = "simple-mfd", "syscon"; reg = <0xea0000 0x400>, <0xdd0170 0x10>; - clocks = <&refclk>; - clock-names = "refclk"; - twsi0_pmux: twsi0-pmux { - groups = "G6"; - function = "twsi0"; + chip_clk: clock { + compatible = "marvell,berlin2q-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + soc_pinctrl: pin-controller { + compatible = "marvell,berlin2q-soc-pinctrl"; + + twsi0_pmux: twsi0-pmux { + groups = "G6"; + function = "twsi0"; + }; + + twsi1_pmux: twsi1-pmux { + groups = "G7"; + function = "twsi1"; + }; }; - twsi1_pmux: twsi1-pmux { - groups = "G7"; - function = "twsi1"; + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; }; }; @@ -382,7 +422,7 @@ compatible = "marvell,berlin2q-ahci", "generic-ahci"; reg = <0xe90000 0x1000>; interrupts = ; - clocks = <&chip CLKID_SATA>; + clocks = <&chip_clk CLKID_SATA>; #address-cells = <1>; #size-cells = <0>; @@ -402,7 +442,7 @@ sata_phy: phy@e900a0 { compatible = "marvell,berlin2q-sata-phy"; reg = <0xe900a0 0x200>; - clocks = <&chip CLKID_SATA>; + clocks = <&chip_clk CLKID_SATA>; #address-cells = <1>; #size-cells = <0>; #phy-cells = <1>; @@ -421,7 +461,7 @@ compatible = "chipidea,usb2"; reg = <0xed0000 0x10000>; interrupts = ; - clocks = <&chip CLKID_USB0>; + clocks = <&chip_clk CLKID_USB0>; phys = <&usb_phy0>; phy-names = "usb-phy"; status = "disabled"; @@ -431,7 +471,7 @@ compatible = "chipidea,usb2"; reg = <0xee0000 0x10000>; interrupts = ; - clocks = <&chip CLKID_USB1>; + clocks = <&chip_clk CLKID_USB1>; phys = <&usb_phy1>; phy-names = "usb-phy"; status = "disabled"; @@ -526,27 +566,37 @@ }; sysctrl: pin-controller@d000 { - compatible = "marvell,berlin2q-system-ctrl"; + compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; + sys_pinctrl: pin-controller { + compatible = "marvell,berlin2q-system-pinctrl"; - uart1_pmux: uart1-pmux { - groups = "GSM14"; - function = "uart1"; - }; + uart0_pmux: uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM14"; + function = "uart1"; + }; + + twsi2_pmux: twsi2-pmux { + groups = "GSM13"; + function = "twsi2"; + }; - twsi2_pmux: twsi2-pmux { - groups = "GSM13"; - function = "twsi2"; + twsi3_pmux: twsi3-pmux { + groups = "GSM14"; + function = "twsi3"; + }; }; - twsi3_pmux: twsi3-pmux { - groups = "GSM14"; - function = "twsi3"; + adc: adc { + compatible = "marvell,berlin2-adc"; + interrupts = <12>, <14>; + interrupt-names = "adc", "tsen"; }; }; diff --git a/dts/src/arm/cx92755.dtsi b/dts/src/arm/cx92755.dtsi index 490c08075e..af333261d0 100644 --- a/dts/src/arm/cx92755.dtsi +++ b/dts/src/arm/cx92755.dtsi @@ -82,6 +82,12 @@ clocks = <&main_clk>; }; + rtc@f0000c30 { + compatible = "cnxt,cx92755-rtc"; + reg = <0xf0000c30 0x18>; + interrupts = <25>; + }; + uc_regs: syscon@f00003a0 { compatible = "cnxt,cx92755-uc", "syscon"; reg = <0xf00003a0 0x10>; @@ -110,4 +116,15 @@ interrupts = <46>; status = "disabled"; }; + + i2c: i2c@f0000120 { + compatible = "cnxt,cx92755-i2c"; + reg = <0xf0000120 0x10>; + interrupts = <28>; + clocks = <&main_clk>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/dts/src/arm/cx92755_equinox.dts b/dts/src/arm/cx92755_equinox.dts index f33bf5635d..90d52cc416 100644 --- a/dts/src/arm/cx92755_equinox.dts +++ b/dts/src/arm/cx92755_equinox.dts @@ -72,3 +72,7 @@ &uart0 { status = "okay"; }; + +&i2c { + status = "okay"; +}; diff --git a/dts/src/arm/dove-cm-a510.dts b/dts/src/arm/dove-cm-a510.dts deleted file mode 100644 index 50c0d69044..0000000000 --- a/dts/src/arm/dove-cm-a510.dts +++ /dev/null @@ -1,38 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Compulab CM-A510"; - compatible = "compulab,cm-a510", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; -}; - -&uart0 { status = "okay"; }; -&uart1 { status = "okay"; }; -&sdio0 { status = "okay"; }; -&sdio1 { status = "okay"; }; -&sata0 { status = "okay"; }; - -&spi0 { - status = "okay"; - - /* spi0.0: 4M Flash Winbond W25Q32BV */ - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/dts/src/arm/dove-cm-a510.dtsi b/dts/src/arm/dove-cm-a510.dtsi new file mode 100644 index 0000000000..59b4056b47 --- /dev/null +++ b/dts/src/arm/dove-cm-a510.dtsi @@ -0,0 +1,195 @@ +/* + * Device Tree include for Compulab CM-A510 System-on-Module + * + * Copyright (C) 2015, Sebastian Hesselbarth + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The CM-A510 comes with several optional components: + * + * Memory options: + * D512: 512M + * D1024: 1G + * + * NAND options: + * N512: 512M NAND + * + * Ethernet options: + * E1: PHY RTL8211D on internal GbE (SMI address 0x03) + * E2: Additional ethernet NIC RTL8111D on PCIe1 + * + * Audio options: + * A: TI TLV320AIC23b audio codec (I2C address 0x1a) + * + * Touchscreen options: + * I: TI TSC2046 touchscreen controller (on SPI1) + * + * USB options: + * U2: 2 dual-role USB2.0 ports + * U4: 2 additional USB2.0 host ports (via USB1) + * + * WiFi options: + * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1) + * + * GPIOs used on CM-A510: + * 1 GbE PHY reset (active low) + * 3 WakeUp + * 8 PowerOff (active low) + * 13 Touchscreen pen irq (active low) + * 65 System LED (active high) + * 69 USB Hub reset (active low) + * 70 WLAN reset (active low) + * 71 WLAN regulator (active high) + */ + +#include "dove.dtsi" + +/ { + model = "Compulab CM-A510"; + compatible = "compulab,cm-a510", "marvell,dove"; + + /* + * Set the minimum memory size here and let the + * bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + /* Set upper NAND data bit to GPO */ + pinctrl-0 = <&pmx_nand_gpo>; + pinctrl-names = "default"; + + system { + label = "cm-a510:system:green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wifi_power: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "WiFi Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Optional RTL8211D GbE PHY on SMI address 0x03 */ +ðphy { + reg = <3>; + status = "disabled"; +}; + +&i2c0 { + /* Optional TI TLV320AIC23b audio codec */ + opt_audio: audio@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + status = "disabled"; + }; +}; + +/* Optional RTL8111D GbE NIC on PCIe1 */ +&pcie { status = "disabled"; }; + +&pcie1 { + pinctrl-0 = <&pmx_pcie1_clkreq>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&pinctrl { + pmx_uart2: pmx-uart2 { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "uart2"; + }; +}; + +/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */ +&sdio1 { + non-removable; + vmmc-supply = <&wifi_power>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&spi0 { + status = "okay"; + + /* 1M Flash Winbond W25Q80BL */ + flash@0 { + compatible = "winbond,w25q80"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&spi1 { + pinctrl-0 = <&pmx_spi1_20_23>; + pinctrl-names = "default"; + status = "disabled"; + + /* Optional TI TSC2046 touchscreen controller */ + opt_touch: touchscreen@0 { + compatible = "ti,tsc2046"; + spi-max-frequency = <2500000>; + reg = <0>; + pinctrl-0 = <&pmx_gpio_13>; + pinctrl-names = "default"; + interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&uart2 { + pinctrl-0 = <&pmx_uart2>; + pinctrl-names = "default"; +}; diff --git a/dts/src/arm/dove-sbc-a510.dts b/dts/src/arm/dove-sbc-a510.dts new file mode 100644 index 0000000000..288e707dea --- /dev/null +++ b/dts/src/arm/dove-sbc-a510.dts @@ -0,0 +1,182 @@ +/* + * Device Tree file for Compulab SBC-A510 Single Board Computer + * + * Copyright (C) 2015, Sebastian Hesselbarth + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to + * + * 0.0 USB0 VBUS_EN (active high) + * 0.1 USB0 VBUS_GOOD + * 0.2 DVI transmitter TI TFP410 MSEN + * 0.3 DVI transmitter TI TFP410 PD# (active low power down) + * 0.4 LVDS transmitter DS90C365 PD# (active low power down) + * 0.5 LCD nRST (active low reset) + * 0.6 PCIe0 nRST (active low reset) + * 0.7 mini-PCIe slot W_DISABLE# + * + * 1.0 MMC WP + * 1.1 Camera Input FPC FLASH_STB and P21.5 + * 1.2 Camera Input FPC WE and P21.22 + * 1.3 MMC VCC_EN (active high) and P21.7 + * 1.4 Camera Input FPC AFTR_RST and P21.17 + * 1.5 Camera Input FPC OE and P21.19 + * 1.6 Camera Input FPC SNPSHT and P21.6 + * 1.7 Camera Input FPC SHTR and P21.10 + */ + +/dts-v1/; + +#include "dove-cm-a510.dtsi" + +/ { + model = "Compulab SBC-A510"; + compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove"; + + chosen { + stdout-path = &uart0; + }; + + regulators { + usb0_power: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; + }; + + mmc_power: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "MMC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Ethernet0 depends on CM-A510 option E1 */ +&mdio { status = "disabled"; }; +ð { status = "disabled"; }; +ðphy { status = "disabled"; }; + +/* + * USB port 0 can be powered and monitored by I2C GPIO expander: + * VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1 + */ +&ehci0 { + status = "okay"; + vbus-supply = <&usb0_power>; +}; + +/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */ +&ehci1 { status = "okay"; }; + +/* + * I2C bus layout: + * i2c0: + * - Audio Codec, 0x1a (option from CM-A510) + * - DVI transmitter TI TFP410, 0x39 + * - HDMI/DVI DDC channel + * i2c1: + * - GPIO expander, NXP PCA9555, 0x20 + * - VGA DDC channel + */ +&i2c { + pinctrl-0 = <&pmx_i2c1>; + pinctrl-names = "default"; +}; + +&i2c0 { + /* TI TFP410 DVI transmitter */ + dvi: video@39 { + compatible = "ti,tfp410"; + reg = <0x39>; + powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + /* NXP PCA9555 GPIO expander */ + gpio_ext: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + }; +}; + +&pcie { status = "okay"; }; + +/* + * PCIe0 can be configured by Jumper E1 to be either connected to + * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge. + */ +&pcie0 { + status = "okay"; + pinctrl-0 = <&pmx_pcie0_clkreq>; + pinctrl-names = "default"; + reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>; +}; + +/* Ethernet1 depends on CM-A510 option E2 */ +&pcie1 { status = "disabled"; }; + +/* SATA connector */ +&sata0 { status = "okay"; }; + +/* + * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has + * VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10 + */ +&sdio0 { + vmmc-supply = <&mmc_power>; + wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* UART0 on RS232 mini-connector */ +&uart0 { status = "okay"; }; +/* UART2 on pin headers */ +&uart2 { status = "okay"; }; diff --git a/dts/src/arm/dove.dtsi b/dts/src/arm/dove.dtsi index 9ad829523a..38b1f7e600 100644 --- a/dts/src/arm/dove.dtsi +++ b/dts/src/arm/dove.dtsi @@ -33,6 +33,42 @@ marvell,tauros2-cache-features = <0>; }; + i2c-mux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c>; + + pinctrl-names = "i2c0", "i2c1", "i2c2"; + pinctrl-0 = <&pmx_i2cmux_0>; + pinctrl-1 = <&pmx_i2cmux_1>; + pinctrl-2 = <&pmx_i2cmux_2>; + + i2c0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + i2c1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + /* Requires pmx_i2c1 on i2c controller node */ + status = "disabled"; + }; + + i2c2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + /* Requires pmx_i2c2 on i2c controller node */ + status = "disabled"; + }; + }; + mbus { compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; #address-cells = <2>; @@ -123,7 +159,7 @@ status = "disabled"; }; - i2c0: i2c-ctrl@11000 { + i2c: i2c-ctrl@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; @@ -132,7 +168,7 @@ clock-frequency = <400000>; timeout-ms = <1000>; clocks = <&core_clk 0>; - status = "disabled"; + status = "okay"; }; uart0: serial@12000 { diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi index f03a091cd0..8f1e25bcec 100644 --- a/dts/src/arm/dra7.dtsi +++ b/dts/src/arm/dra7.dtsi @@ -131,6 +131,11 @@ regulator-max-microvolt = <3000000>; }; }; + + scm_conf_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; }; dra7_pmx_core: pinmux@1400 { @@ -1469,6 +1474,44 @@ clocks = <&sys_clkin1>; status = "disabled"; }; + + dss: dss@58000000 { + compatible = "ti,dra7-dss"; + /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ + /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ + status = "disabled"; + ti,hwmods = "dss_core"; + /* CTRL_CORE_DSS_PLL_CONTROL */ + syscon-pll-ctrl = <&scm_conf 0x538>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@58001000 { + compatible = "ti,dra7-dispc"; + reg = <0x58001000 0x1000>; + interrupts = ; + ti,hwmods = "dss_dispc"; + clocks = <&dss_dss_clk>; + clock-names = "fck"; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + }; + + hdmi: encoder@58060000 { + compatible = "ti,dra7-hdmi"; + reg = <0x58040000 0x200>, + <0x58040200 0x80>, + <0x58040300 0x80>, + <0x58060000 0x19000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = ; + status = "disabled"; + ti,hwmods = "dss_hdmi"; + clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; + clock-names = "fck", "sys_clk"; + }; + }; }; thermal_zones: thermal-zones { diff --git a/dts/src/arm/dra72-evm.dts b/dts/src/arm/dra72-evm.dts index ce0390f081..4e1b605817 100644 --- a/dts/src/arm/dra72-evm.dts +++ b/dts/src/arm/dra72-evm.dts @@ -19,6 +19,10 @@ reg = <0x80000000 0x40000000>; /* 1024 MB */ }; + aliases { + display0 = &hdmi0; + }; + evm_3v3: fixedregulator-evm_3v3 { compatible = "regulator-fixed"; regulator-name = "evm_3v3"; @@ -35,6 +39,51 @@ compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + pinctrl-names = "default"; + pinctrl-0 = <&tpd12s015_pins>; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &dra7_pmx_core { @@ -45,6 +94,13 @@ >; }; + i2c5_pins: pinmux_i2c5_pins { + pinctrl-single,pins = < + 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ + 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ + >; + }; + nand_default: nand_default { pinctrl-single,pins = < 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ @@ -142,6 +198,19 @@ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ >; }; + + hdmi_pins: pinmux_hdmi_pins { + pinctrl-single,pins = < + 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ + >; + }; }; &i2c1 { @@ -277,6 +346,27 @@ }; }; +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + }; +}; + &uart1 { status = "okay"; }; @@ -566,3 +656,23 @@ }; }; }; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo3_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/dts/src/arm/dra72x.dtsi b/dts/src/arm/dra72x.dtsi index 03d742f8d5..eaca143faa 100644 --- a/dts/src/arm/dra72x.dtsi +++ b/dts/src/arm/dra72x.dtsi @@ -34,3 +34,14 @@ interrupts = ; }; }; + +&dss { + reg = <0x58000000 0x80>, + <0x58004054 0x4>, + <0x58004300 0x20>; + reg-names = "dss", "pll1_clkctrl", "pll1"; + + clocks = <&dss_dss_clk>, + <&dss_video1_clk>; + clock-names = "fck", "video1_clk"; +}; diff --git a/dts/src/arm/dra74x.dtsi b/dts/src/arm/dra74x.dtsi index cc560a7092..fa995d0ca1 100644 --- a/dts/src/arm/dra74x.dtsi +++ b/dts/src/arm/dra74x.dtsi @@ -73,3 +73,18 @@ }; }; }; + +&dss { + reg = <0x58000000 0x80>, + <0x58004054 0x4>, + <0x58004300 0x20>, + <0x58005054 0x4>, + <0x58005300 0x20>; + reg-names = "dss", "pll1_clkctrl", "pll1", + "pll2_clkctrl", "pll2"; + + clocks = <&dss_dss_clk>, + <&dss_video1_clk>, + <&dss_video2_clk>; + clock-names = "fck", "video1_clk", "video2_clk"; +}; diff --git a/dts/src/arm/dra7xx-clocks.dtsi b/dts/src/arm/dra7xx-clocks.dtsi index 3b933f74d0..357bedeebf 100644 --- a/dts/src/arm/dra7xx-clocks.dtsi +++ b/dts/src/arm/dra7xx-clocks.dtsi @@ -1531,6 +1531,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1120>; + ti,set-rate-parent; }; dss_hdmi_clk: dss_hdmi_clk { @@ -2136,3 +2137,13 @@ clocks = <&dpll_usb_ck>; }; }; + +&scm_conf_clocks { + dss_deshdcp_clk: dss_deshdcp_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_iclk_div>; + ti,bit-shift = <0>; + reg = <0x558>; + }; +}; diff --git a/dts/src/arm/emev2-kzm9d.dts b/dts/src/arm/emev2-kzm9d.dts index 19446273e4..1dee0aa4f4 100644 --- a/dts/src/arm/emev2-kzm9d.dts +++ b/dts/src/arm/emev2-kzm9d.dts @@ -81,7 +81,7 @@ regulator-boot-on; }; - lan9220@20000000 { + ethernet@20000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x20000000 0x10000>; phy-mode = "mii"; @@ -96,7 +96,7 @@ }; &pfc { - uart1_pins: uart@e1030000 { + uart1_pins: serial@e1030000 { renesas,groups = "uart1_ctrl", "uart1_data"; renesas,function = "uart1"; }; diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts index 1d483c1c8b..a5863acc5f 100644 --- a/dts/src/arm/exynos3250-monk.dts +++ b/dts/src/arm/exynos3250-monk.dts @@ -16,6 +16,7 @@ #include "exynos3250.dtsi" #include #include +#include / { model = "Samsung Monk board"; @@ -432,7 +433,7 @@ }; &rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; status = "okay"; }; diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts index 0b9906880c..031853b755 100644 --- a/dts/src/arm/exynos3250-rinato.dts +++ b/dts/src/arm/exynos3250-rinato.dts @@ -16,6 +16,7 @@ #include "exynos3250.dtsi" #include #include +#include / { model = "Samsung Rinato board"; @@ -567,6 +568,10 @@ status = "okay"; }; +&jpeg { + status = "okay"; +}; + &mshc_0 { #address-cells = <1>; #size-cells = <0>; @@ -605,7 +610,7 @@ }; &rtc { - clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; status = "okay"; }; diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi index e3bfb11c6e..d7201333e3 100644 --- a/dts/src/arm/exynos3250.dtsi +++ b/dts/src/arm/exynos3250.dtsi @@ -189,7 +189,7 @@ }; rtc: rtc@10070000 { - compatible = "samsung,exynos3250-rtc"; + compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; interrupt-parent = <&pmu_system_controller>; @@ -243,6 +243,30 @@ interrupts = <0 240 0>; }; + jpeg: codec@11830000 { + compatible = "samsung,exynos3250-jpeg"; + reg = <0x11830000 0x1000>; + interrupts = <0 171 0>; + clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; + clock-names = "jpeg", "sclk"; + power-domains = <&pd_cam>; + assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; + assigned-clock-rates = <0>, <150000000>; + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; + iommus = <&sysmmu_jpeg>; + status = "disabled"; + }; + + sysmmu_jpeg: sysmmu@11A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a60000 0x1000>; + interrupts = <0 156 0>, <0 161 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + fimd: fimd@11c00000 { compatible = "samsung,exynos3250-fimd"; reg = <0x11c00000 0x30000>; @@ -251,6 +275,7 @@ clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -270,6 +295,16 @@ status = "disabled"; }; + sysmmu_fimd0: sysmmu@11E20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11e20000 0x1000>; + interrupts = <0 80 0>, <0 81 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + hsotg: hsotg@12480000 { compatible = "snps,dwc2"; reg = <0x12480000 0x20000>; @@ -364,9 +399,20 @@ clock-names = "mfc", "sclk_mfc"; clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; power-domains = <&pd_mfc>; + iommus = <&sysmmu_mfc>; status = "disabled"; }; + sysmmu_mfc: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupts = <0 96 0>, <0 98 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi index e20cdc24c3..b0d52b1a64 100644 --- a/dts/src/arm/exynos4.dtsi +++ b/dts/src/arm/exynos4.dtsi @@ -78,7 +78,6 @@ mipi_phy: video-phy@10020710 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10020710 8>; #phy-cells = <1>; syscon = <&pmu_system_controller>; }; @@ -167,7 +166,7 @@ phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -190,6 +189,7 @@ clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc0>; status = "disabled"; }; @@ -201,6 +201,7 @@ clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc1>; status = "disabled"; }; @@ -212,6 +213,7 @@ clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc2>; status = "disabled"; }; @@ -223,6 +225,7 @@ clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; + iommus = <&sysmmu_fimc3>; status = "disabled"; }; @@ -257,7 +260,7 @@ }; }; - watchdog@10060000 { + watchdog: watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; interrupts = <0 43 0>; @@ -266,7 +269,7 @@ status = "disabled"; }; - rtc@10070000 { + rtc: rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupt-parent = <&pmu_system_controller>; @@ -276,7 +279,7 @@ status = "disabled"; }; - keypad@100A0000 { + keypad: keypad@100A0000 { compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <0 109 0>; @@ -285,7 +288,7 @@ status = "disabled"; }; - sdhci@12510000 { + sdhci_0: sdhci@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <0 73 0>; @@ -294,7 +297,7 @@ status = "disabled"; }; - sdhci@12520000 { + sdhci_1: sdhci@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <0 74 0>; @@ -303,7 +306,7 @@ status = "disabled"; }; - sdhci@12530000 { + sdhci_2: sdhci@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <0 75 0>; @@ -312,7 +315,7 @@ status = "disabled"; }; - sdhci@12540000 { + sdhci_3: sdhci@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <0 76 0>; @@ -331,7 +334,7 @@ status = "disabled"; }; - hsotg@12480000 { + hsotg: hsotg@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = <0 71 0>; @@ -342,7 +345,7 @@ status = "disabled"; }; - ehci@12580000 { + ehci: ehci@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = <0 70 0>; @@ -368,7 +371,7 @@ }; }; - ohci@12590000 { + ohci: ohci@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = <0 70 0>; @@ -417,6 +420,8 @@ power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; status = "disabled"; }; @@ -621,7 +626,7 @@ status = "disabled"; }; - pwm@139D0000 { + pwm: pwm@139D0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; @@ -681,6 +686,7 @@ clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -689,6 +695,15 @@ #include "exynos4412-tmu-sensor-conf.dtsi" }; + jpeg_codec: jpeg-codec@11840000 { + compatible = "samsung,exynos4210-jpeg"; + reg = <0x11840000 0x1000>; + interrupts = <0 88 0>; + clocks = <&clock CLK_JPEG>; + clock-names = "jpeg"; + power-domains = <&pd_cam>; + }; + hdmi: hdmi@12D00000 { compatible = "samsung,exynos4210-hdmi"; reg = <0x12D00000 0x70000>; @@ -709,6 +724,7 @@ interrupts = <0 91 0>; reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; power-domains = <&pd_tv>; + iommus = <&sysmmu_tv>; status = "disabled"; }; @@ -819,4 +835,114 @@ clock-names = "ppmu"; status = "disabled"; }; + + sysmmu_mfc_l: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@13630000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13630000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@12E20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12E20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + power-domains = <&pd_tv>; + #iommu-cells = <0>; + }; + + sysmmu_fimc0: sysmmu@11A20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc1: sysmmu@11A30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc2: sysmmu@11A40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_fimc3: sysmmu@11A50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg: sysmmu@11A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@12A30000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12A30000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + + sysmmu_fimd0: sysmmu@11E20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11E20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; }; diff --git a/dts/src/arm/exynos4210-origen.dts b/dts/src/arm/exynos4210-origen.dts index b811461414..e0abfc3324 100644 --- a/dts/src/arm/exynos4210-origen.dts +++ b/dts/src/arm/exynos4210-origen.dts @@ -50,209 +50,6 @@ }; }; - watchdog@10060000 { - status = "okay"; - }; - - rtc@10070000 { - status = "okay"; - }; - - tmu@100C0000 { - status = "okay"; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; - }; - - sdhci@12510000 { - bus-width = <4>; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; - }; - - g2d@12800000 { - status = "okay"; - }; - - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - - i2c@13860000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <4 0>, <3 0>; - - max8997,pmic-buck1-dvs-voltage = <1350000>; - max8997,pmic-buck2-dvs-voltage = <1100000>; - max8997,pmic-buck5-dvs-voltage = <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "VMIPI_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_RTC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_AUD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VADC_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "DVDD_SWB_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_PLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_AUD_3V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "AVDD18_SWB_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDD_SWB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD_MIF_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_INT_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_G3D_1.1V"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_LCD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - }; - gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -314,12 +111,6 @@ }; }; - fimd@11c00000 { - pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; - pinctrl-names = "default"; - status = "okay"; - }; - display-timings { native-mode = <&timing0>; timing0: timing { @@ -335,3 +126,212 @@ }; }; }; + +&fimd { + pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&g2d { + status = "okay"; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <4 0>, <3 0>; + + max8997,pmic-buck1-dvs-voltage = <1350000>; + max8997,pmic-buck2-dvs-voltage = <1100000>; + max8997,pmic-buck5-dvs-voltage = <1200000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ABB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_ALIVE_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VMIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_RTC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_AUD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "DVDD_SWB_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD_PLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_AUD_3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "AVDD18_SWB_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_SWB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_MIF_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + /* + * HACK: The real name is VDD_ARM_1.2V, + * but exynos-cpufreq does not support + * DT-based regulator lookup yet. + */ + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_INT_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VDD_LCD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + status = "okay"; +}; + +&sdhci_0 { + bus-width = <4>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/dts/src/arm/exynos4210-smdkv310.dts b/dts/src/arm/exynos4210-smdkv310.dts index 86216fff1b..043b03caff 100644 --- a/dts/src/arm/exynos4210-smdkv310.dts +++ b/dts/src/arm/exynos4210-smdkv310.dts @@ -30,181 +30,181 @@ stdout-path = &serial_1; }; - sdhci@12530000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - status = "okay"; - }; + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <12000000>; + }; - g2d@12800000 { - status = "okay"; + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; }; +}; - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; - }; +&g2d { + status = "okay"; +}; - serial@13800000 { - status = "okay"; - }; +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; - serial@13810000 { - status = "okay"; + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; }; - serial@13820000 { - status = "okay"; + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; }; +}; - serial@13830000 { - status = "okay"; +&keypad { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_rows &keypad_cols>; + status = "okay"; + + key_1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; }; - pinctrl@11000000 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + key_2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; }; - keypad@100A0000 { - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - linux,keypad-wakeup; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_cols>; - status = "okay"; + key_3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; + key_4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; + key_5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; + key_a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; - key_4 { - keypad,row = <0>; - keypad,column = <6>; - linux,code = <5>; - }; + key_b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; - key_5 { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <6>; - }; + key_c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; - key_a { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <30>; - }; + key_d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; - key_b { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <48>; - }; + key_e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; +}; - key_c { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <46>; - }; +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + status = "okay"; +}; - key_d { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <32>; - }; +&pinctrl_1 { + keypad_rows: keypad-rows { + samsung,pins = "gpx2-0", "gpx2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; - key_e { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <18>; - }; + keypad_cols: keypad-cols { + samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", + "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; +}; - i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,24ad0xd1"; - reg = <0x50>; - }; +&sdhci_2 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + status = "okay"; +}; - eeprom@52 { - compatible = "samsung,24ad0xd1"; - reg = <0x52>; - }; - }; +&serial_0 { + status = "okay"; +}; - spi_2: spi@13940000 { - cs-gpios = <&gpc1 2 0>; - status = "okay"; +&serial_1 { + status = "okay"; +}; - w25x80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; +&serial_2 { + status = "okay"; +}; - controller-data { - samsung,spi-feedback-delay = <0>; - }; +&serial_3 { + status = "okay"; +}; - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; - }; +&spi_2 { + cs-gpios = <&gpc1 2 0>; + status = "okay"; - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; - }; + w25x80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + samsung,spi-feedback-delay = <0>; }; - }; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <12000000>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; }; - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; }; }; }; diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts index 32c5fd8f62..98f3ce65cb 100644 --- a/dts/src/arm/exynos4210-trats.dts +++ b/dts/src/arm/exynos4210-trats.dts @@ -89,42 +89,6 @@ }; }; - hsotg@12480000 { - vusb_d-supply = <&vusb_reg>; - vusb_a-supply = <&vusbdac_reg>; - dr_mode = "peripheral"; - status = "okay"; - }; - - sdhci_emmc: sdhci@12510000 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&vemmc_reg>; - status = "okay"; - }; - - exynos-usbphy@125B0000 { - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; @@ -158,201 +122,6 @@ }; }; - i2c@13890000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpx0>; - interrupts = <4 2>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&tsp_reg>; - vdd-supply = <&tsp_reg>; - }; - }; - - i2c@138B0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c5_bus>; - pinctrl-names = "default"; - status = "okay"; - - max8997_pmic@66 { - compatible = "maxim,max8997-pmic"; - - reg = <0x66>; - - max8997,pmic-buck1-uses-gpio-dvs; - max8997,pmic-buck2-uses-gpio-dvs; - max8997,pmic-buck5-uses-gpio-dvs; - - max8997,pmic-ignore-gpiodvs-side-effect; - max8997,pmic-buck125-default-dvs-idx = <0>; - - max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>, - <&gpx0 6 0>, - <&gpl0 0 0>; - - max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; - - max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, - <950000>, <900000>, - <1100000>, <1000000>, - <950000>, <900000>; - - max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vusbdac_reg: LDO8 { - regulator-name = "VUSB/VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-always-on; - }; - - safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; - }; - }; - }; - }; - fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -365,71 +134,6 @@ }; }; - dsi_0: dsi@11C80000 { - vddcore-supply = <&vusb_reg>; - vddio-supply = <&vmipi_reg>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&dsi_in>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - }; - }; - }; - - panel@0 { - reg = <0>; - compatible = "samsung,s6e8aa0"; - vdd3-supply = <&vcclcd_reg>; - vci-supply = <&vlcd_reg>; - reset-gpios = <&gpy4 5 0>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - - port { - dsi_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; - }; - - fimd@11c00000 { - status = "okay"; - }; - - tmu@100C0000 { - status = "okay"; - }; - thermal-zones { cpu_thermal: cpu-thermal { cooling-maps { @@ -483,3 +187,299 @@ }; }; }; + +&dsi_0 { + vddcore-supply = <&vusb_reg>; + vddio-supply = <&vmipi_reg>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + }; + }; + }; + + panel@0 { + reg = <0>; + compatible = "samsung,s6e8aa0"; + vdd3-supply = <&vcclcd_reg>; + vci-supply = <&vlcd_reg>; + reset-gpios = <&gpy4 5 0>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + + port { + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + mms114-touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpx0>; + interrupts = <4 2>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&tsp_reg>; + vdd-supply = <&tsp_reg>; + }; +}; + +&i2c_5 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + status = "okay"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + + reg = <0x66>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>, + <&gpx0 6 0>, + <&gpl0 0 0>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + regulators { + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB/VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.3V_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vlcd_reg: LDO15 { + regulator-name = "VLCD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + /* + * HACK: The real name is VARM_1.2V_C210, + * but exynos-cpufreq does not support + * DT-based regulator lookup yet. + */ + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V_C210"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-always-on; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; +}; + +&sdhci_0 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/dts/src/arm/exynos4210.dtsi b/dts/src/arm/exynos4210.dtsi index be89f83f70..10d3c17339 100644 --- a/dts/src/arm/exynos4210.dtsi +++ b/dts/src/arm/exynos4210.dtsi @@ -52,17 +52,7 @@ }; }; - pmu_system_controller: system-controller@10020000 { - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, - <&clock CLK_XUSBXTI>; - #clock-cells = <1>; - }; - - sysram@02020000 { + sysram: sysram@02020000 { compatible = "mmio-sram"; reg = <0x02020000 0x20000>; #address-cells = <1>; @@ -95,19 +85,7 @@ arm,data-latency = <2 2 1>; }; - gic: interrupt-controller@10490000 { - cpu-offset = <0x8000>; - }; - - combiner: interrupt-controller@10440000 { - samsung,combiner-nr = <16>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; - }; - - mct@10050000 { + mct: mct@10050000 { compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupt-parent = <&mct_map>; @@ -189,12 +167,13 @@ }; }; - g2d@12800000 { + g2d: g2d@12800000 { compatible = "samsung,s5pv210-g2d"; reg = <0x12800000 0x1000>; interrupts = <0 89 0>; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; status = "disabled"; }; @@ -244,4 +223,47 @@ clock-names = "ppmu"; status = "disabled"; }; + + sysmmu_g2d: sysmmu@12A20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12A20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1: sysmmu@12220000 { + compatible = "samsung,exynos-sysmmu"; + interrupt-parent = <&combiner>; + reg = <0x12220000 0x1000>; + interrupts = <5 3>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + power-domains = <&pd_lcd1>; + #iommu-cells = <0>; + }; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&combiner { + samsung,combiner-nr = <16>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; +}; + +&pmu_system_controller { + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; }; diff --git a/dts/src/arm/exynos4212.dtsi b/dts/src/arm/exynos4212.dtsi index 5be03288f1..d9c8efeef2 100644 --- a/dts/src/arm/exynos4212.dtsi +++ b/dts/src/arm/exynos4212.dtsi @@ -41,12 +41,12 @@ reg = <0xA01>; }; }; +}; - combiner: interrupt-controller@10440000 { - samsung,combiner-nr = <18>; - }; +&combiner { + samsung,combiner-nr = <18>; +}; - gic: interrupt-controller@10490000 { - cpu-offset = <0x8000>; - }; +&gic { + cpu-offset = <0x8000>; }; diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi index d6b49e5b32..ca7d168d1d 100644 --- a/dts/src/arm/exynos4412-odroid-common.dtsi +++ b/dts/src/arm/exynos4412-odroid-common.dtsi @@ -38,16 +38,6 @@ }; }; - i2s0: i2s@03830000 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - }; - sound: sound { compatible = "simple-audio-card"; assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, @@ -83,427 +73,437 @@ reset-gpios = <&gpk1 2 1>; }; - mmc@12550000 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - vmmc-supply = <&ldo20_reg &buck8_reg>; - mmc-pwrseq = <&emmc_pwrseq>; - status = "okay"; - - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; - }; - - watchdog@10060000 { - status = "okay"; - }; - - rtc@10070000 { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; - }; - - g2d@10800000 { - status = "okay"; - }; - camera { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <>; + }; - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; }; - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; }; + }; - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>; + }; + }; }; }; +}; - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo4_reg &ldo21_reg>; - cd-gpios = <&gpk2 2 0>; - cd-inverted; - status = "okay"; - }; +/* RSTN signal for eMMC */ +&sd1_cd { + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; +}; - serial@13800000 { - status = "okay"; +&pinctrl_1 { + gpio_power_key: power_key { + samsung,pins = "gpx1-3"; + samsung,pin-pud = <0>; }; - serial@13810000 { - status = "okay"; + max77686_irq: max77686-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; + hdmi_hpd: hdmi-hpd { + samsung,pins = "gpx3-7"; + samsung,pin-pud = <1>; }; +}; - i2c@13860000 { - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; - status = "okay"; +&ehci { + status = "okay"; +}; - usb3503: usb3503@08 { - compatible = "smsc,usb3503"; - reg = <0x08>; +&exynos_usbphy { + status = "okay"; +}; - intn-gpios = <&gpx3 0 0>; - connect-gpios = <&gpx3 4 0>; - reset-gpios = <&gpx3 5 0>; - initial-mode = <1>; - }; +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; - max77686: pmic@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M1_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; - ldo3_reg: LDO3 { - regulator-name = "VDDQ_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; - ldo4_reg: LDO4 { - regulator-name = "VDDQ_MMC2_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; +&g2d { + status = "okay"; +}; - ldo5_reg: LDO5 { - regulator-name = "VDDQ_MMC1_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; +&hdmi { + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + ddc = <&i2c_2>; + status = "okay"; +}; - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; +&hsotg { + dr_mode = "peripheral"; + status = "okay"; + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; +}; - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; +&i2c_0 { + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + usb3503: usb3503@08 { + compatible = "smsc,usb3503"; + reg = <0x08>; + + intn-gpios = <&gpx3 0 0>; + connect-gpios = <&gpx3 4 0>; + reset-gpios = <&gpx3 5 0>; + initial-mode = <1>; + }; - ldo8_reg: ldo@8 { - regulator-compatible = "LDO8"; - regulator-name = "VDD10_HDMI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; + max77686: pmic@09 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx3>; + interrupts = <2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - ldo10_reg: ldo@10 { - regulator-compatible = "LDO10"; - regulator-name = "VDDQ_MIPIHSI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M1_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + ldo3_reg: LDO3 { + regulator-name = "VDDQ_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - ldo12_reg: LDO12 { - regulator-name = "VDD33_USB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; + ldo4_reg: LDO4 { + regulator-name = "VDDQ_MMC2_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; + ldo5_reg: LDO5 { + regulator-name = "VDDQ_MMC1_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - ldo15_reg: LDO15 { - regulator-name = "VDD10_HSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; + ldo8_reg: ldo@8 { + regulator-compatible = "LDO8"; + regulator-name = "VDD10_HDMI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; - ldo20_reg: LDO20 { - regulator-name = "LDO20_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; + ldo10_reg: ldo@10 { + regulator-compatible = "LDO10"; + regulator-name = "VDDQ_MIPIHSI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - ldo21_reg: LDO21 { - regulator-name = "LDO21_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - ldo25_reg: LDO25 { - regulator-name = "VDDQ_LCD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; + ldo12_reg: LDO12 { + regulator-name = "VDD33_USB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; + ldo15_reg: LDO15 { + regulator-name = "VDD10_HSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-microvolt-offset = <50000>; - }; + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - buck5_reg: BUCK5 { - regulator-name = "VDDQ_CKEM1_2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; + ldo20_reg: LDO20 { + regulator-name = "LDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; - buck6_reg: BUCK6 { - regulator-name = "BUCK6_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; + ldo21_reg: LDO21 { + regulator-name = "LDO21_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; - buck7_reg: BUCK7 { - regulator-name = "BUCK7_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; + ldo25_reg: LDO25 { + regulator-name = "VDDQ_LCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - buck8_reg: BUCK8 { - regulator-name = "BUCK8_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; }; - }; - }; - i2c@13870000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "okay"; - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupt-parent = <&gpx0>; - interrupts = <0 0>; - clocks = <&i2s0 CLK_I2S_CDCLK>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - }; + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; - exynos-usbphy@125B0000 { - status = "okay"; - }; + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; - hsotg@12480000 { - dr_mode = "peripheral"; - status = "okay"; - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - }; + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-microvolt-offset = <50000>; + }; - ehci: ehci@12580000 { - status = "okay"; - }; + buck5_reg: BUCK5 { + regulator-name = "VDDQ_CKEM1_2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; - tmu@100C0000 { - vtmu-supply = <&ldo10_reg>; - status = "okay"; - }; + buck6_reg: BUCK6 { + regulator-name = "BUCK6_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; - }; - }; + buck7_reg: BUCK7 { + regulator-name = "BUCK7_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "BUCK8_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; }; }; +}; - mixer: mixer@12C10000 { - status = "okay"; +&i2c_1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "okay"; + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx0>; + interrupts = <0 0>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; }; +}; - hdmi@12D00000 { - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - ddc = <&hdmi_ddc>; - status = "okay"; - }; +&i2c_2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; +}; - hdmi_ddc: i2c@13880000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - }; +&i2c_8 { + status = "okay"; +}; - i2c@138E0000 { - status = "okay"; - }; +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; }; -/* RSTN signal for eMMC */ -&sd1_cd { - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; +&mixer { + status = "okay"; }; -&pinctrl_1 { - gpio_power_key: power_key { - samsung,pins = "gpx1-3"; - samsung,pin-pud = <0>; - }; +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&ldo20_reg &buck8_reg>; + mmc-pwrseq = <&emmc_pwrseq>; + status = "okay"; + + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; - hdmi_hpd: hdmi-hpd { - samsung,pins = "gpx3-7"; - samsung,pin-pud = <1>; - }; +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo4_reg &ldo21_reg>; + cd-gpios = <&gpk2 2 0>; + cd-inverted; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +}; + +&watchdog { + status = "okay"; }; diff --git a/dts/src/arm/exynos4412-odroidx.dts b/dts/src/arm/exynos4412-odroidx.dts index cb1cfe7239..679ac103eb 100644 --- a/dts/src/arm/exynos4412-odroidx.dts +++ b/dts/src/arm/exynos4412-odroidx.dts @@ -38,14 +38,6 @@ }; }; - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - gpio_keys { pinctrl-0 = <&gpio_power_key &gpio_home_key>; @@ -83,3 +75,11 @@ samsung,pin-pud = <0>; }; }; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts index bd8b73077d..84c76310b3 100644 --- a/dts/src/arm/exynos4412-origen.dts +++ b/dts/src/arm/exynos4412-origen.dts @@ -50,485 +50,485 @@ }; }; - watchdog@10060000 { - status = "okay"; - }; - - rtc@10070000 { - status = "okay"; + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <47500000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <64>; + hback-porch = <16>; + hsync-len = <48>; + vback-porch = <64>; + vfront-porch = <16>; + vsync-len = <3>; + }; }; - pinctrl@11000000 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; }; - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; }; }; +}; - keypad@100A0000 { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <2>; - linux,keypad-no-autorepeat; - linux,keypad-wakeup; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_home { - keypad,row = <0>; - keypad,column = <0>; - linux,code = ; - }; +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; +}; - key_down { - keypad,row = <0>; - keypad,column = <1>; - linux,code = ; - }; +&g2d { + status = "okay"; +}; - key_up { - keypad,row = <1>; - keypad,column = <0>; - linux,code = ; - }; +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767_pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + + s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>, + <&gpx2 4 0>, + <&gpx2 5 0>; + + s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>, + <&gpm3 6 0>, + <&gpm3 7 0>; + + s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; - key_menu { - keypad,row = <1>; - keypad,column = <1>; - linux,code = ; - }; + ldo2_reg: LDO2 { + regulator-name = "VDDQ_M12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; - key_back { - keypad,row = <2>; - keypad,column = <0>; - linux,code = ; - }; + ldo3_reg: LDO3 { + regulator-name = "VDDIOAP_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo4_reg: LDO4 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD18_2M"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD10_XPLL"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD10_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD33_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD18_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD18_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD33_UOTG"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDIOPERI_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB02"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_USH"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDIOAP_MMC012_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo18_reg: LDO18 { + regulator-name = "VDDIOPERI_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo19_reg: LDO19 { + regulator-name = "DVDD25"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD28_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD28_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo22_reg: LDO22 { + regulator-name = "VDDA28_2M"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; - key_enter { - keypad,row = <2>; - keypad,column = <1>; - linux,code = ; + ldo23_reg: LDO23 { + regulator-name = "VDD28_TF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD33_A31"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD18_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD18_A31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo27_reg: LDO27 { + regulator-name = "GPS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + ldo28_reg: LDO28 { + regulator-name = "DVDD12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_m12"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd12_5m"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + buck9_reg: BUCK9 { + regulator-name = "vddf28_emmc"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; }; }; +}; - g2d@10800000 { - status = "okay"; +&keypad { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <2>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; + status = "okay"; + + key_home { + keypad,row = <0>; + keypad,column = <0>; + linux,code = ; }; - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; + key_down { + keypad,row = <0>; + keypad,column = <1>; + linux,code = ; }; - mmc@12550000 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - bus-width = <8>; - cap-mmc-highspeed; + key_up { + keypad,row = <1>; + keypad,column = <0>; + linux,code = ; }; - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; + key_menu { + keypad,row = <1>; + keypad,column = <1>; + linux,code = ; }; - fimd@11c00000 { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; + key_back { + keypad,row = <2>; + keypad,column = <0>; + linux,code = ; }; - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <47500000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; + key_enter { + keypad,row = <2>; + keypad,column = <1>; + linux,code = ; }; +}; - serial@13800000 { - status = "okay"; - }; +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + status = "okay"; +}; - serial@13810000 { - status = "okay"; - }; +&mshc_0 { + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-width = <8>; + cap-mmc-highspeed; +}; - serial@13820000 { - status = "okay"; +&pinctrl_1 { + keypad_rows: keypad-rows { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; }; - serial@13830000 { - status = "okay"; + keypad_cols: keypad-cols { + samsung,pins = "gpx1-0", "gpx1-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; +}; - i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>, - <&gpx2 4 0>, - <&gpx2 5 0>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>, - <&gpm3 6 0>, - <&gpm3 7 0>; - - s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD18_2M"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "DVDD25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - }; - }; - }; +&rtc { + status = "okay"; +}; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&mmc_reg>; + status = "okay"; +}; - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&watchdog { + status = "okay"; }; diff --git a/dts/src/arm/exynos4412-smdk4412.dts b/dts/src/arm/exynos4412-smdk4412.dts index b9256afbcc..c2421df1fa 100644 --- a/dts/src/arm/exynos4412-smdk4412.dts +++ b/dts/src/arm/exynos4412-smdk4412.dts @@ -28,135 +28,135 @@ stdout-path = &serial_1; }; - g2d@10800000 { - status = "okay"; - }; - - pinctrl@11000000 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; }; - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; }; }; +}; - keypad@100A0000 { - samsung,keypad-num-rows = <3>; - samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; - linux,keypad-wakeup; - pinctrl-0 = <&keypad_rows &keypad_cols>; - pinctrl-names = "default"; - status = "okay"; - - key_1 { - keypad,row = <1>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <1>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <1>; - keypad,column = <5>; - linux,code = <4>; - }; - - key_4 { - keypad,row = <1>; - keypad,column = <6>; - linux,code = <5>; - }; +&g2d { + status = "okay"; +}; - key_5 { - keypad,row = <1>; - keypad,column = <7>; - linux,code = <6>; - }; +&keypad { + samsung,keypad-num-rows = <3>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + pinctrl-0 = <&keypad_rows &keypad_cols>; + pinctrl-names = "default"; + status = "okay"; + + key_1 { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <2>; + }; - key_A { - keypad,row = <2>; - keypad,column = <6>; - linux,code = <30>; - }; + key_2 { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <3>; + }; - key_B { - keypad,row = <2>; - keypad,column = <7>; - linux,code = <48>; - }; + key_3 { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <4>; + }; - key_C { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <46>; - }; + key_4 { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <5>; + }; - key_D { - keypad,row = <2>; - keypad,column = <5>; - linux,code = <32>; - }; + key_5 { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <6>; + }; - key_E { - keypad,row = <0>; - keypad,column = <7>; - linux,code = <18>; - }; + key_A { + keypad,row = <2>; + keypad,column = <6>; + linux,code = <30>; }; - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - status = "okay"; + key_B { + keypad,row = <2>; + keypad,column = <7>; + linux,code = <48>; }; - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; + key_C { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <46>; }; - serial@13800000 { - status = "okay"; + key_D { + keypad,row = <2>; + keypad,column = <5>; + linux,code = <32>; }; - serial@13810000 { - status = "okay"; + key_E { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <18>; }; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + status = "okay"; +}; - serial@13820000 { - status = "okay"; +&pinctrl_1 { + keypad_rows: keypad-rows { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; }; - serial@13830000 { - status = "okay"; + keypad_cols: keypad-cols { + samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", + "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; +}; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + status = "okay"; +}; - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; }; diff --git a/dts/src/arm/exynos4412-tiny4412.dts b/dts/src/arm/exynos4412-tiny4412.dts index d46fd4c2ae..525684ca8d 100644 --- a/dts/src/arm/exynos4412-tiny4412.dts +++ b/dts/src/arm/exynos4412-tiny4412.dts @@ -56,33 +56,6 @@ }; }; - rtc@10070000 { - status = "okay"; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -95,3 +68,30 @@ }; }; }; + +&rtc { + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; diff --git a/dts/src/arm/exynos4412-trats2.dts b/dts/src/arm/exynos4412-trats2.dts index 792394dd0f..afc199d78c 100644 --- a/dts/src/arm/exynos4412-trats2.dts +++ b/dts/src/arm/exynos4412-trats2.dts @@ -16,6 +16,7 @@ #include "exynos4412.dtsi" #include #include +#include / { model = "Samsung Trats 2 based on Exynos4412"; @@ -130,411 +131,6 @@ }; }; - adc: adc@126C0000 { - vdd-supply = <&ldo3_reg>; - status = "okay"; - }; - - i2c@13890000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c3_bus>; - pinctrl-names = "default"; - status = "okay"; - - mms114-touchscreen@48 { - compatible = "melfas,mms114"; - reg = <0x48>; - interrupt-parent = <&gpm2>; - interrupts = <3 2>; - x-size = <720>; - y-size = <1280>; - avdd-supply = <&ldo23_reg>; - vdd-supply = <&ldo24_reg>; - }; - }; - - i2c_0: i2c@13860000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <400000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5c73m3@3c { - compatible = "samsung,s5c73m3"; - reg = <0x3c>; - standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */ - xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */ - vdd-int-supply = <&buck9_reg>; - vddio-cis-supply = <&ldo9_reg>; - vdda-supply = <&ldo17_reg>; - vddio-host-supply = <&ldo18_reg>; - vdd-af-supply = <&cam_af_reg>; - vdd-reg-supply = <&cam_io_reg>; - clock-frequency = <24000000>; - /* CAM_A_CLKOUT */ - clocks = <&camera 0>; - clock-names = "cis_extclk"; - port { - s5c73m3_ep: endpoint { - remote-endpoint = <&csis0_ep>; - data-lanes = <1 2 3 4>; - }; - }; - }; - }; - - i2c@138A0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c4_bus>; - pinctrl-names = "default"; - status = "okay"; - - wm1811: wm1811@1a { - compatible = "wlf,wm1811"; - reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; - DBVDD1-supply = <&ldo3_reg>; - wlf,ldo1ena = <&gpj0 4 0>; - }; - }; - - i2c@138D0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-slave-addr = <0x10>; - samsung,i2c-max-bus-freq = <100000>; - pinctrl-0 = <&i2c7_bus>; - pinctrl-names = "default"; - status = "okay"; - - max77686_pmic@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx0>; - interrupts = <7 0>; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: ldo1 { - regulator-compatible = "LDO1"; - regulator-name = "VALIVE_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-compatible = "LDO2"; - regulator-name = "VM1M2_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo3_reg: ldo3 { - regulator-compatible = "LDO3"; - regulator-name = "VCC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-compatible = "LDO4"; - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - regulator-compatible = "LDO5"; - regulator-name = "VCC_1.8V_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: ldo6 { - regulator-compatible = "LDO6"; - regulator-name = "VMPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo7_reg: ldo7 { - regulator-compatible = "LDO7"; - regulator-name = "VPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo8_reg: ldo8 { - regulator-compatible = "LDO8"; - regulator-name = "VMIPI_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: ldo9 { - regulator-compatible = "LDO9"; - regulator-name = "CAM_ISP_MIPI_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo10_reg: ldo10 { - regulator-compatible = "LDO10"; - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: ldo11 { - regulator-compatible = "LDO11"; - regulator-name = "VABB1_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: ldo12 { - regulator-compatible = "LDO12"; - regulator-name = "VUOTG_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: ldo13 { - regulator-compatible = "LDO13"; - regulator-name = "NFC_AVDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: ldo14 { - regulator-compatible = "LDO14"; - regulator-name = "VABB2_1.95V"; - regulator-min-microvolt = <1950000>; - regulator-max-microvolt = <1950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: ldo15 { - regulator-compatible = "LDO15"; - regulator-name = "VHSIC_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo16_reg: ldo16 { - regulator-compatible = "LDO16"; - regulator-name = "VHSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo17_reg: ldo17 { - regulator-compatible = "LDO17"; - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo18_reg: ldo18 { - regulator-compatible = "LDO18"; - regulator-name = "CAM_ISP_SEN_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: ldo19 { - regulator-compatible = "LDO19"; - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: ldo20 { - regulator-compatible = "LDO20"; - regulator-name = "VDDQ_PRE_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: ldo21 { - regulator-compatible = "LDO21"; - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; - }; - - ldo22_reg: ldo22 { - regulator-compatible = "LDO22"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - ldo23_reg: ldo23 { - regulator-compatible = "LDO23"; - regulator-name = "TSP_AVDD_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: ldo24 { - regulator-compatible = "LDO24"; - regulator-name = "TSP_VDD_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo25_reg: ldo25 { - regulator-compatible = "LDO25"; - regulator-name = "LCD_VCC_3.3V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: ldo26 { - regulator-compatible = "LDO26"; - regulator-name = "MOTOR_VCC_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: buck1 { - regulator-compatible = "BUCK1"; - regulator-name = "vdd_mif"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: buck2 { - regulator-compatible = "BUCK2"; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck3_reg: buck3 { - regulator-compatible = "BUCK3"; - regulator-name = "vdd_int"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: buck4 { - regulator-compatible = "BUCK4"; - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: buck5 { - regulator-compatible = "BUCK5"; - regulator-name = "VMEM_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: buck6 { - regulator-compatible = "BUCK6"; - regulator-name = "VCC_SUB_1.35V"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: buck7 { - regulator-compatible = "BUCK7"; - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: buck8 { - regulator-compatible = "BUCK8"; - regulator-name = "VMEM_VDDF_3.0V"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; - }; - - buck9_reg: buck9 { - regulator-compatible = "BUCK9"; - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; - }; - }; - }; - }; - i2c_max77693: i2c-gpio-1 { compatible = "i2c-gpio"; gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; @@ -597,54 +193,6 @@ }; }; - mmc@12550000 { - num-slots = <1>; - broken-cd; - non-removable; - card-detect-delay = <200>; - vmmc-supply = <&ldo22_reg>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <0>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - bus-width = <8>; - cap-mmc-highspeed; - }; - - sdhci@12530000 { - bus-width = <4>; - cd-gpios = <&gpx3 4 0>; - cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&ldo21_reg>; - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - - tmu@100C0000 { - vtmu-supply = <&ldo10_reg>; - status = "okay"; - }; - i2c_ak8975: i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&gpy2 4 0>, <&gpy2 5 0>; @@ -676,90 +224,6 @@ }; }; - spi_1: spi@13930000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - cs-gpios = <&gpb 5 0>; - status = "okay"; - - s5c73m3_spi: s5c73m3 { - compatible = "samsung,s5c73m3"; - spi-max-frequency = <50000000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <2>; - }; - }; - }; - - pwm: pwm@139D0000 { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - samsung,pwm-outputs = <0>; - status = "okay"; - }; - - dsi_0: dsi@11C80000 { - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - samsung,pll-clock-frequency = <24000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&dsi_in>; - samsung,burst-clock-frequency = <500000000>; - samsung,esc-clock-frequency = <20000000>; - }; - }; - }; - - panel@0 { - compatible = "samsung,s6e8aa0"; - reg = <0>; - vdd3-supply = <&lcd_vdd3_reg>; - vci-supply = <&ldo25_reg>; - reset-gpios = <&gpy4 5 0>; - power-on-delay= <50>; - reset-delay = <100>; - init-delay = <100>; - flip-horizontal; - flip-vertical; - panel-width-mm = <58>; - panel-height-mm = <103>; - - display-timings { - timing-0 { - clock-frequency = <57153600>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <5>; - hback-porch = <5>; - hsync-len = <5>; - vfront-porch = <13>; - vback-porch = <1>; - vsync-len = <2>; - }; - }; - - port { - dsi_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; - }; - - fimd@11c00000 { - status = "okay"; - }; - camera: camera { pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; @@ -769,124 +233,7 @@ assigned-clock-parents = <&clock CLK_XUSBXTI>, <&clock CLK_XUSBXTI>; - fimc_0: fimc@11800000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC0>, - <&clock CLK_SCLK_FIMC0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - }; - - fimc_1: fimc@11810000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC1>, - <&clock CLK_SCLK_FIMC1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - }; - - fimc_2: fimc@11820000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC2>, - <&clock CLK_SCLK_FIMC2>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - }; - - fimc_3: fimc@11830000 { - status = "okay"; - assigned-clocks = <&clock CLK_MOUT_FIMC3>, - <&clock CLK_SCLK_FIMC3>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - }; - - csis_0: csis@11880000 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS0>, - <&clock CLK_SCLK_CSIS0>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera C (3) MIPI CSI-2 (CSIS0) */ - port@3 { - reg = <3>; - csis0_ep: endpoint { - remote-endpoint = <&s5c73m3_ep>; - data-lanes = <1 2 3 4>; - samsung,csis-hs-settle = <12>; - }; - }; - }; - - csis_1: csis@11890000 { - status = "okay"; - vddcore-supply = <&ldo8_reg>; - vddio-supply = <&ldo10_reg>; - assigned-clocks = <&clock CLK_MOUT_CSIS1>, - <&clock CLK_SCLK_CSIS1>; - assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; - assigned-clock-rates = <0>, <176000000>; - - /* Camera D (4) MIPI CSI-2 (CSIS1) */ - port@4 { - reg = <4>; - csis1_ep: endpoint { - remote-endpoint = <&is_s5k6a3_ep>; - data-lanes = <1>; - samsung,csis-hs-settle = <18>; - samsung,csis-wclk; - }; - }; - }; - - fimc_lite_0: fimc-lite@12390000 { - status = "okay"; - }; - - fimc_lite_1: fimc-lite@123A0000 { - status = "okay"; - }; - fimc-is@12000000 { - pinctrl-0 = <&fimc_is_uart>; - pinctrl-names = "default"; - status = "okay"; - - i2c1_isp: i2c-isp@12140000 { - pinctrl-0 = <&fimc_is_i2c1>; - pinctrl-names = "default"; - - s5k6a3@10 { - compatible = "samsung,s5k6a3"; - reg = <0x10>; - svdda-supply = <&cam_io_reg>; - svddio-supply = <&ldo19_reg>; - afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; - /* CAM_B_CLKOUT */ - clocks = <&camera 1>; - clock-names = "extclk"; - samsung,camclk-out = <1>; - gpios = <&gpm1 6 0>; - - port { - is_s5k6a3_ep: endpoint { - remote-endpoint = <&csis1_ep>; - data-lanes = <1>; - }; - }; - }; - }; - }; - }; - - i2s0: i2s@03830000 { - pinctrl-0 = <&i2s0_bus>; - pinctrl-names = "default"; - status = "okay"; }; sound { @@ -901,17 +248,6 @@ "SPK", "SPKOUTRP"; }; - exynos-usbphy@125B0000 { - status = "okay"; - }; - - hsotg@12480000 { - vusb_d-supply = <&ldo15_reg>; - vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; - status = "okay"; - }; - thermistor-ap@0 { compatible = "ntc,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ @@ -944,6 +280,619 @@ }; }; +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + +&csis_0 { + status = "okay"; + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + assigned-clocks = <&clock CLK_MOUT_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; + + /* Camera C (3) MIPI CSI-2 (CSIS0) */ + port@3 { + reg = <3>; + csis0_ep: endpoint { + remote-endpoint = <&s5c73m3_ep>; + data-lanes = <1 2 3 4>; + samsung,csis-hs-settle = <12>; + }; + }; +}; + +&csis_1 { + status = "okay"; + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + assigned-clocks = <&clock CLK_MOUT_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; + + /* Camera D (4) MIPI CSI-2 (CSIS1) */ + port@4 { + reg = <4>; + csis1_ep: endpoint { + remote-endpoint = <&is_s5k6a3_ep>; + data-lanes = <1>; + samsung,csis-hs-settle = <18>; + samsung,csis-wclk; + }; + }; +}; + +&dsi_0 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + }; + }; + }; + + panel@0 { + compatible = "samsung,s6e8aa0"; + reg = <0>; + vdd3-supply = <&lcd_vdd3_reg>; + vci-supply = <&ldo25_reg>; + reset-gpios = <&gpy4 5 0>; + power-on-delay= <50>; + reset-delay = <100>; + init-delay = <100>; + flip-horizontal; + flip-vertical; + panel-width-mm = <58>; + panel-height-mm = <103>; + + display-timings { + timing-0 { + clock-frequency = <57153600>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <5>; + hback-porch = <5>; + hsync-len = <5>; + vfront-porch = <13>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; + + port { + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimc_0 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_1 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_2 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_3 { + status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; +}; + +&fimc_is { + pinctrl-0 = <&fimc_is_uart>; + pinctrl-names = "default"; + status = "okay"; + + i2c1_isp: i2c-isp@12140000 { + pinctrl-0 = <&fimc_is_i2c1>; + pinctrl-names = "default"; + + s5k6a3@10 { + compatible = "samsung,s5k6a3"; + reg = <0x10>; + svdda-supply = <&cam_io_reg>; + svddio-supply = <&ldo19_reg>; + afvdd-supply = <&ldo19_reg>; + clock-frequency = <24000000>; + /* CAM_B_CLKOUT */ + clocks = <&camera 1>; + clock-names = "extclk"; + samsung,camclk-out = <1>; + gpios = <&gpm1 6 0>; + + port { + is_s5k6a3_ep: endpoint { + remote-endpoint = <&csis1_ep>; + data-lanes = <1>; + }; + }; + }; + }; +}; + +&fimc_lite_0 { + status = "okay"; +}; + +&fimc_lite_1 { + status = "okay"; +}; + +&fimd { + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_0 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5c73m3@3c { + compatible = "samsung,s5c73m3"; + reg = <0x3c>; + standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */ + xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */ + vdd-int-supply = <&buck9_reg>; + vddio-cis-supply = <&ldo9_reg>; + vdda-supply = <&ldo17_reg>; + vddio-host-supply = <&ldo18_reg>; + vdd-af-supply = <&cam_af_reg>; + vdd-reg-supply = <&cam_io_reg>; + clock-frequency = <24000000>; + /* CAM_A_CLKOUT */ + clocks = <&camera 0>; + clock-names = "cis_extclk"; + port { + s5c73m3_ep: endpoint { + remote-endpoint = <&csis0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + mms114-touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 2>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + wm1811: wm1811@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>; + clock-names = "MCLK1"; + DCVDD-supply = <&ldo3_reg>; + DBVDD1-supply = <&ldo3_reg>; + wlf,ldo1ena = <&gpj0 4 0>; + }; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: max77686_pmic@09 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 0>; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mshc_0 { + num-slots = <1>; + broken-cd; + non-removable; + card-detect-delay = <200>; + vmmc-supply = <&ldo22_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; +}; + &pmu_system_controller { assigned-clocks = <&pmu_system_controller 0>; assigned-clock-parents = <&clock CLK_XUSBXTI>; @@ -1304,3 +1253,63 @@ PIN_SLP(gpv4-0, INPUT, DOWN); }; }; + +&pwm { + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 0>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; +}; + +&serial_0 { + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&spi_1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + cs-gpios = <&gpb 5 0>; + status = "okay"; + + s5c73m3_spi: s5c73m3 { + compatible = "samsung,s5c73m3"; + spi-max-frequency = <50000000>; + reg = <0>; + controller-data { + samsung,spi-feedback-delay = <2>; + }; + }; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +}; diff --git a/dts/src/arm/exynos4412.dtsi b/dts/src/arm/exynos4412.dtsi index 68ad43b391..b78ada70bd 100644 --- a/dts/src/arm/exynos4412.dtsi +++ b/dts/src/arm/exynos4412.dtsi @@ -54,19 +54,19 @@ }; }; - combiner: interrupt-controller@10440000 { - samsung,combiner-nr = <20>; - }; - pmu { interrupts = <2 2>, <3 2>, <18 2>, <19 2>; }; +}; - gic: interrupt-controller@10490000 { - cpu-offset = <0x4000>; - }; +&pmu_system_controller { + compatible = "samsung,exynos4412-pmu", "syscon"; +}; - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4412-pmu", "syscon"; - }; +&combiner { + samsung,combiner-nr = <20>; +}; + +&gic { + cpu-offset = <0x4000>; }; diff --git a/dts/src/arm/exynos4415.dtsi b/dts/src/arm/exynos4415.dtsi index 5caea996e0..ad764842ff 100644 --- a/dts/src/arm/exynos4415.dtsi +++ b/dts/src/arm/exynos4415.dtsi @@ -124,8 +124,8 @@ mipi_phy: video-phy@10020710 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10020710 8>; #phy-cells = <1>; + syscon = <&pmu_system_controller>; }; pd_cam: cam-power-domain@10024000 { @@ -177,7 +177,7 @@ }; rtc: rtc@10070000 { - compatible = "samsung,exynos3250-rtc"; + compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; status = "disabled"; @@ -249,6 +249,7 @@ clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; samsung,power-domain = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; samsung,sysreg = <&sysreg_system_controller>; status = "disabled"; }; @@ -268,6 +269,16 @@ status = "disabled"; }; + sysmmu_fimd0: sysmmu@11E20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11e20000 0x1000>; + interrupts = <0 80 0>, <0 81 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + hsotg: hsotg@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; diff --git a/dts/src/arm/exynos4x12-pinctrl.dtsi b/dts/src/arm/exynos4x12-pinctrl.dtsi index c141931378..bac25c6727 100644 --- a/dts/src/arm/exynos4x12-pinctrl.dtsi +++ b/dts/src/arm/exynos4x12-pinctrl.dtsi @@ -29,7 +29,7 @@ } / { - pinctrl@11400000 { + pinctrl_0: pinctrl@11400000 { gpa0: gpa0 { gpio-controller; #gpio-cells = <2>; @@ -441,7 +441,7 @@ }; }; - pinctrl@11000000 { + pinctrl_1: pinctrl@11000000 { gpk0: gpk0 { gpio-controller; #gpio-cells = <2>; @@ -887,7 +887,7 @@ }; }; - pinctrl@03860000 { + pinctrl_2: pinctrl@03860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; @@ -913,7 +913,7 @@ }; }; - pinctrl@106E0000 { + pinctrl_3: pinctrl@106E0000 { gpv0: gpv0 { gpio-controller; #gpio-cells = <2>; diff --git a/dts/src/arm/exynos4x12.dtsi b/dts/src/arm/exynos4x12.dtsi index 6a6abe14fd..b77dac61ff 100644 --- a/dts/src/arm/exynos4x12.dtsi +++ b/dts/src/arm/exynos4x12.dtsi @@ -96,32 +96,6 @@ }; }; - combiner: interrupt-controller@10440000 { - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0>; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - adc: adc@126C0000 { compatible = "samsung,exynos-adc-v1"; reg = <0x126C0000 0x100>; @@ -135,36 +109,13 @@ status = "disabled"; }; - pinctrl_2: pinctrl@03860000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; - }; - - pinctrl_3: pinctrl@106E0000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; - interrupts = <0 72 0>; - }; - - pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4212-pmu", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, - <&clock CLK_XUSBXTI>; - #clock-cells = <1>; - }; - - g2d@10800000 { + g2d: g2d@10800000 { compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; interrupts = <0 89 0>; clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; status = "disabled"; }; @@ -173,40 +124,7 @@ <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - fimc_0: fimc@11800000 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; - }; - - fimc_1: fimc@11810000 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; - }; - - fimc_2: fimc@11820000 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; - }; - - fimc_3: fimc@11830000 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - }; - + /* fimc_[0-3] are configured outside, under phandles */ fimc_lite_0: fimc-lite@12390000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0x12390000 0x1000>; @@ -214,6 +132,7 @@ power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>; clock-names = "flite"; + iommus = <&sysmmu_fimc_lite0>; status = "disabled"; }; @@ -224,6 +143,7 @@ power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE1>; clock-names = "flite"; + iommus = <&sysmmu_fimc_lite1>; status = "disabled"; }; @@ -252,6 +172,9 @@ "mcuispdiv1", "uart", "aclk200", "div_aclk200", "aclk400mcuisp", "div_aclk400mcuisp"; + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; + iommu-names = "isp", "drc", "fd", "mcuctl"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -284,29 +207,192 @@ status = "disabled"; }; - exynos-usbphy@125B0000 { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; + sysmmu_g2d: sysmmu@10A40000{ + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; }; - tmu@100C0000 { - compatible = "samsung,exynos4412-tmu"; + sysmmu_fimc_isp: sysmmu@12260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12260000 0x1000>; interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100C0000 0x100>; - clocks = <&clock 383>; - clock-names = "tmu_apbif"; - status = "disabled"; + interrupts = <16 2>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_ISP>; + #iommu-cells = <0>; }; - hdmi: hdmi@12D00000 { - compatible = "samsung,exynos4212-hdmi"; + sysmmu_fimc_drc: sysmmu@12270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 3>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_DRC>; + #iommu-cells = <0>; }; - mixer: mixer@12C10000 { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + sysmmu_fimc_fd: sysmmu@122A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122A0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 4>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@122B0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 5>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_ISPCX>; + #iommu-cells = <0>; }; + + sysmmu_fimc_lite0: sysmmu@123B0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@123C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 1>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; + #iommu-cells = <0>; + }; +}; + +&combiner { + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; +}; + +&exynos_usbphy { + compatible = "samsung,exynos4x12-usb2-phy"; + samsung,sysreg-phandle = <&sys_reg>; +}; + +&fimc_0 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_1 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_2 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + samsung,cam-if; +}; + +&fimc_3 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; +}; + +&hdmi { + compatible = "samsung,exynos4212-hdmi"; +}; + +&jpeg_codec { + compatible = "samsung,exynos4212-jpeg"; +}; + +&mixer { + compatible = "samsung,exynos4212-mixer"; + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; +}; + +&pinctrl_0 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; +}; + +&pinctrl_1 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; +}; + +&pinctrl_2 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; +}; + +&pinctrl_3 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106E0000 0x1000>; + interrupts = <0 72 0>; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4212-pmu", "syscon"; + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; +}; + +&tmu { + compatible = "samsung,exynos4412-tmu"; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + reg = <0x100C0000 0x100>; + clocks = <&clock 383>; + clock-names = "tmu_apbif"; + status = "disabled"; }; diff --git a/dts/src/arm/exynos5.dtsi b/dts/src/arm/exynos5.dtsi index a0cc0b6f8f..110dbd4fb8 100644 --- a/dts/src/arm/exynos5.dtsi +++ b/dts/src/arm/exynos5.dtsi @@ -81,14 +81,14 @@ interrupts = <0 54 0>; }; - rtc@101E0000 { + rtc: rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; interrupts = <0 43 0>, <0 44 0>; status = "disabled"; }; - fimd@14400000 { + fimd: fimd@14400000 { compatible = "samsung,exynos5250-fimd"; interrupt-parent = <&combiner>; reg = <0x14400000 0x40000>; @@ -98,7 +98,7 @@ status = "disabled"; }; - dp-controller@145B0000 { + dp: dp-controller@145B0000 { compatible = "samsung,exynos5-dp"; reg = <0x145B0000 0x1000>; interrupts = <10 3>; diff --git a/dts/src/arm/exynos5250-smdk5250.dts b/dts/src/arm/exynos5250-smdk5250.dts index bc27cc2558..4fe186d01f 100644 --- a/dts/src/arm/exynos5250-smdk5250.dts +++ b/dts/src/arm/exynos5250-smdk5250.dts @@ -131,6 +131,9 @@ reg = <0x09>; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77686_irq>; + wakeup-source; voltage-regulators { ldo1_reg: LDO1 { @@ -410,3 +413,12 @@ }; }; }; + +&pinctrl_0 { + max77686_irq: max77686-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; diff --git a/dts/src/arm/exynos5250-snow.dts b/dts/src/arm/exynos5250-snow.dts index 1eca97ee4b..b7f4122df4 100644 --- a/dts/src/arm/exynos5250-snow.dts +++ b/dts/src/arm/exynos5250-snow.dts @@ -177,30 +177,6 @@ }; }; - i2c@12CD0000 { - ptn3460: lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; - edid-emulation = <5>; - - ports { - port@0 { - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - - port@1 { - bridge_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - }; - }; - sound { compatible = "google,snow-audio-max98095"; @@ -507,6 +483,28 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + ptn3460: lvds-bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; + edid-emulation = <5>; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; + max98095: codec@11 { compatible = "maxim,max98095"; reg = <0x11>; diff --git a/dts/src/arm/exynos5250.dtsi b/dts/src/arm/exynos5250.dtsi index 257e2f1052..bf9bee67c4 100644 --- a/dts/src/arm/exynos5250.dtsi +++ b/dts/src/arm/exynos5250.dtsi @@ -230,6 +230,7 @@ interrupts = <0 91 0>; clocks = <&clock CLK_G2D>; clock-names = "fimg2d"; + iommus = <&sysmmu_g2d>; }; mfc: codec@11000000 { @@ -239,13 +240,8 @@ power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; - }; - - rtc: rtc@101E0000 { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; }; tmu: tmu@10060000 { @@ -276,26 +272,6 @@ }; }; - serial@12C00000 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial@12C10000 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial@12C20000 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial@12C30000 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - }; - sata: sata@122F0000 { compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; @@ -720,6 +696,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; + iommu = <&sysmmu_gsc0>; }; gsc_1: gsc@13e10000 { @@ -729,6 +706,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; + iommu = <&sysmmu_gsc1>; }; gsc_2: gsc@13e20000 { @@ -738,6 +716,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; + iommu = <&sysmmu_gsc2>; }; gsc_3: gsc@13e30000 { @@ -747,6 +726,7 @@ power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; + iommu = <&sysmmu_gsc3>; }; hdmi: hdmi { @@ -770,6 +750,7 @@ clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; + iommus = <&sysmmu_tv>; }; dp_phy: video-phy@10040720 { @@ -778,20 +759,6 @@ #phy-cells = <0>; }; - dp: dp-controller@145B0000 { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_DP>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; - }; - - fimd: fimd@14400000 { - power-domains = <&pd_disp1>; - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - }; - adc: adc@12D10000 { compatible = "samsung,exynos-adc-v1"; reg = <0x12D10000 0x100>; @@ -811,4 +778,287 @@ clocks = <&clock CLK_SSS>; clock-names = "secss"; }; + + sysmmu_g2d: sysmmu@10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + power-domains = <&pd_mfc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + #iommu-cells = <0>; + }; + + sysmmu_rotator: sysmmu@11D40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11D40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg: sysmmu@11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_isp: sysmmu@13260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ISP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_drc: sysmmu@13270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DRC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_fd: sysmmu@132A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132A0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_scc: sysmmu@13280000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13280000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 2>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_scp: sysmmu@13290000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13290000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_SCP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@132B0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132B0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_MCU>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_odc: sysmmu@132C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <11 0>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_ODC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_dis0: sysmmu@132D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_dis1: sysmmu@132E0000{ + compatible = "samsung,exynos-sysmmu"; + reg = <0x132E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <9 4>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_DIS1>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_3dnr: sysmmu@132F0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x132F0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <5 6>; + clock-names = "sysmmu"; + clocks = <&clock CLK_SMMU_FIMC_3DNR>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite0: sysmmu@13C40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@13C50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 1>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; + #iommu-cells = <0>; + }; + + sysmmu_gsc0: sysmmu@13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_gsc1: sysmmu@13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_gsc2: sysmmu@13EA0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13EA0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_gsc3: sysmmu@13EB0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13EB0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 6>; + power-domains = <&pd_gsc>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1: sysmmu@14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + power-domains = <&pd_disp1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; + #iommu-cells = <0>; + }; +}; + +&dp { + power-domains = <&pd_disp1>; + clocks = <&clock CLK_DP>; + clock-names = "dp"; + phys = <&dp_phy>; + phy-names = "dp"; +}; + +&fimd { + power-domains = <&pd_disp1>; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; + clock-names = "sclk_fimd", "fimd"; + iommus = <&sysmmu_fimd1>; +}; + +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; +}; + +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_3 { + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; }; diff --git a/dts/src/arm/exynos5260-xyref5260.dts b/dts/src/arm/exynos5260-xyref5260.dts index a803b60505..3daef94bee 100644 --- a/dts/src/arm/exynos5260-xyref5260.dts +++ b/dts/src/arm/exynos5260-xyref5260.dts @@ -70,7 +70,7 @@ broken-cd; bypass-smu; cap-mmc-highspeed; - supports-hs200-mode; /* 200 Mhz */ + supports-hs200-mode; /* 200 MHz */ card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/dts/src/arm/exynos5420-arndale-octa.dts b/dts/src/arm/exynos5420-arndale-octa.dts index b82b6fa15f..eeb4ac22cf 100644 --- a/dts/src/arm/exynos5420-arndale-octa.dts +++ b/dts/src/arm/exynos5420-arndale-octa.dts @@ -13,6 +13,7 @@ #include "exynos5420.dtsi" #include #include +#include / { model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; @@ -38,325 +39,6 @@ }; }; - rtc@101E0000 { - status = "okay"; - }; - - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - }; - - mmc@12200000 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - vmmc-supply = <&ldo10_reg>; - bus-width = <8>; - cap-mmc-highspeed; - }; - - mmc@12220000 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - vmmc-supply = <&ldo19_reg>; - vqmmc-supply = <&ldo13_reg>; - bus-width = <4>; - cap-sd-highspeed; - }; - - hsi2c_4: i2c@12CA0000 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; - - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "PVDD_ALIVE_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "PVDD_APIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "PVDD_APIO_MMCON_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "PVDD_ADC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "PVDD_PLL_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "PVDD_ANAIP_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo7_reg: LDO7 { - regulator-name = "PVDD_ANAIP_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "PVDD_ABB_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9_reg: LDO9 { - regulator-name = "PVDD_USB_3V3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "PVDD_PRE_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "PVDD_USB_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "PVDD_HSIC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "PVDD_APIO_MMCOFF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "PVDD_PERI_2V8"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "PVDD_PERI_3V3"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "PVDD_EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "PVDD_TFLASH_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "PVDD_BTWIFI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo21_reg: LDO21 { - regulator-name = "PVDD_CAM1IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "PVDD_MIFS_1V1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "PVDD_CAM1_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "PVDD_CAM0_AF_2V8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "PVDD_G3DS_1V0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "PVDD_TSP_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "PVDD_AUDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo31_reg: LDO31 { - regulator-name = "PVDD_PERI_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo32_reg: LDO32 { - regulator-name = "PVDD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "PVDD_CAM0IO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "PVDD_CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo38_reg: LDO38 { - regulator-name = "PVDD_CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "PVDD_MIF_1V1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "PVDD_INT_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "PVDD_G3D_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "PVDD_LPDDR3_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "PVDD_KFC_1V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VIN_HLDO_3V5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "PVDD_EMMCF_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - }; - }; - }; - gpio_keys { compatible = "gpio-keys"; @@ -376,3 +58,335 @@ &cci { status = "disabled"; }; + +&hsi2c_4 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + s2mps11,buck2-ramp-delay = <12>; + s2mps11,buck34-ramp-delay = <12>; + s2mps11,buck16-ramp-delay = <12>; + s2mps11,buck6-ramp-enable = <1>; + s2mps11,buck2-ramp-enable = <1>; + s2mps11,buck3-ramp-enable = <1>; + s2mps11,buck4-ramp-enable = <1>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "PVDD_ALIVE_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "PVDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "PVDD_APIO_MMCON_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "PVDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "PVDD_PLL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "PVDD_ANAIP_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "PVDD_ANAIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "PVDD_ABB_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "PVDD_USB_3V3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "PVDD_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "PVDD_USB_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "PVDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "PVDD_APIO_MMCOFF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "PVDD_PERI_2V8"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "PVDD_PERI_3V3"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "PVDD_EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "PVDD_TFLASH_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "PVDD_BTWIFI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "PVDD_CAM1IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "PVDD_MIFS_1V1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "PVDD_CAM1_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "PVDD_CAM0_AF_2V8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "PVDD_G3DS_1V0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "PVDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "PVDD_AUDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo31_reg: LDO31 { + regulator-name = "PVDD_PERI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo32_reg: LDO32 { + regulator-name = "PVDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "PVDD_CAM0IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "PVDD_CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "PVDD_CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "PVDD_MIF_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "PVDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "PVDD_G3D_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "PVDD_LPDDR3_1V2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "PVDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "PVDD_EMMCF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + vmmc-supply = <&ldo10_reg>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; diff --git a/dts/src/arm/exynos5420-peach-pit.dts b/dts/src/arm/exynos5420-peach-pit.dts index 146e71118a..8f4d76c5e1 100644 --- a/dts/src/arm/exynos5420-peach-pit.dts +++ b/dts/src/arm/exynos5420-peach-pit.dts @@ -1027,7 +1027,7 @@ }; }; -&uart_3 { +&serial_3 { status = "okay"; }; diff --git a/dts/src/arm/exynos5420-smdk5420.dts b/dts/src/arm/exynos5420-smdk5420.dts index 9103f2381a..98871f972c 100644 --- a/dts/src/arm/exynos5420-smdk5420.dts +++ b/dts/src/arm/exynos5420-smdk5420.dts @@ -64,105 +64,6 @@ }; }; - rtc@101E0000 { - status = "okay"; - }; - - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - }; - - mmc@12200000 { - status = "okay"; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 2>; - samsung,read-strobe-delay = <90>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 - &sd0_rclk>; - bus-width = <8>; - cap-mmc-highspeed; - }; - - mmc@12220000 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; - }; - - dp-controller@145B0000 { - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; - }; - - fimd@14400000 { - status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; - }; - - pinctrl@13400000 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@14000000 { - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gpg0-5"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gpg1-4"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - - hdmi@14530000 { - status = "okay"; - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - }; - usb300_vbus_reg: regulator-usb300 { compatible = "regulator-fixed"; regulator-name = "VBUS0"; @@ -185,238 +86,338 @@ enable-active-high; }; - phy@12100000 { - vbus-supply = <&usb300_vbus_reg>; - }; +}; - phy@12500000 { - vbus-supply = <&usb301_vbus_reg>; +&dp { + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + status = "okay"; +}; + +&fimd { + status = "okay"; + display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; + }; }; +}; - i2c_2: i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; +}; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; +&hsi2c_4 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + s2mps11,buck2-ramp-delay = <12>; + s2mps11,buck34-ramp-delay = <12>; + s2mps11,buck16-ramp-delay = <12>; + s2mps11,buck6-ramp-enable = <1>; + s2mps11,buck2-ramp-enable = <1>; + s2mps11,buck3-ramp-enable = <1>; + s2mps11,buck4-ramp-enable = <1>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; }; - }; - hsi2c_4: i2c@12CA0000 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; }; }; }; }; + +&i2c_2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + status = "okay"; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 + &sd0_rclk>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gpg0-5"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gpg1-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi index 45317538bb..534f27ceb1 100644 --- a/dts/src/arm/exynos5420.dtsi +++ b/dts/src/arm/exynos5420.dtsi @@ -179,6 +179,8 @@ clocks = <&clock CLK_MFC>; clock-names = "mfc"; power-domains = <&mfc_pd>; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; }; mmc_0: mmc@12200000 { @@ -264,9 +266,8 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, - <&clock CLK_MOUT_USER_ACLK333>; - clock-names = "oscclk", "pclk0", "clk0"; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; + clock-names = "oscclk", "clk0"; #power-domain-cells = <0>; }; @@ -280,16 +281,12 @@ compatible = "samsung,exynos4210-pd"; reg = <0x100440C0 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_SW_ACLK400>, <&clock CLK_MOUT_USER_ACLK400_DISP1>, <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2", - "asb0", "asb1"; + clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { @@ -328,13 +325,6 @@ interrupts = <0 47 0>; }; - rtc: rtc@101E0000 { - clocks = <&clock CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&pmu_system_controller>; - status = "disabled"; - }; - amba { #address-cells = <1>; #size-cells = <1>; @@ -416,6 +406,9 @@ <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_SCLK_I2S>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk0"; + #sound-dai-cells = <1>; samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; @@ -430,6 +423,9 @@ dma-names = "tx", "rx"; clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk1"; + #sound-dai-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; status = "disabled"; @@ -443,6 +439,9 @@ dma-names = "tx", "rx"; clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; clock-names = "iis", "i2s_opclk0"; + #clock-cells = <1>; + clock-output-names = "i2s_cdclk2"; + #sound-dai-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; status = "disabled"; @@ -496,26 +495,6 @@ status = "disabled"; }; - uart_0: serial@12C00000 { - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; - - uart_1: serial@12C10000 { - clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - }; - - uart_2: serial@12C20000 { - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; - - uart_3: serial@12C30000 { - clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - }; - pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12dd0000 0x100>; @@ -531,17 +510,9 @@ #phy-cells = <0>; }; - dp: dp-controller@145B0000 { - clocks = <&clock CLK_DP1>; - clock-names = "dp"; - phys = <&dp_phy>; - phy-names = "dp"; - power-domains = <&disp_pd>; - }; - mipi_phy: video-phy@10040714 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040714 12>; + syscon = <&pmu_system_controller>; #phy-cells = <1>; }; @@ -558,12 +529,6 @@ status = "disabled"; }; - fimd: fimd@14400000 { - clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; - clock-names = "sclk_fimd", "fimd"; - power-domains = <&disp_pd>; - }; - adc: adc@12D10000 { compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>; @@ -750,6 +715,7 @@ <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; power-domains = <&disp_pd>; + iommus = <&sysmmu_tv>; }; gsc_0: video-scaler@13e00000 { @@ -759,6 +725,7 @@ clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl0>; }; gsc_1: video-scaler@13e10000 { @@ -768,6 +735,25 @@ clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl1>; + }; + + jpeg_0: jpeg@11F50000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F50000 0x1000>; + interrupts = <0 89 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG>; + iommus = <&sysmmu_jpeg0>; + }; + + jpeg_1: jpeg@11F60000 { + compatible = "samsung,exynos5420-jpeg"; + reg = <0x11F60000 0x1000>; + interrupts = <0 168 0>; + clock-names = "jpeg"; + clocks = <&clock CLK_JPEG2>; + iommus = <&sysmmu_jpeg1>; }; pmu_system_controller: system-controller@10040000 { @@ -962,4 +948,221 @@ samsung,sysreg-phandle = <&sysreg_system_controller>; samsung,pmureg-phandle = <&pmu_system_controller>; }; + + sysmmu_g2dr: sysmmu@0x10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_g2dw: sysmmu@0x10A70000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@0x14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl0: sysmmu@0x13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@0x13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0r: sysmmu@0x12880000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1r: sysmmu@0x12890000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12890000 0x1000>; + interrupts = <0 186 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2r: sysmmu@0x128A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128A0000 0x1000>; + interrupts = <0 188 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0w: sysmmu@0x128C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1w: sysmmu@0x128D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2w: sysmmu@0x128E0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg0: sysmmu@0x11F10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg1: sysmmu@0x11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupts = <0 169 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@0x11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@0x11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_0: sysmmu@0x14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_1: sysmmu@0x14680000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; +}; + +&dp { + clocks = <&clock CLK_DP1>; + clock-names = "dp"; + phys = <&dp_phy>; + phy-names = "dp"; + power-domains = <&disp_pd>; +}; + +&fimd { + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; + clock-names = "sclk_fimd", "fimd"; + power-domains = <&disp_pd>; + iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; + iommu-names = "m0", "m1"; +}; + +&rtc { + clocks = <&clock CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&pmu_system_controller>; + status = "disabled"; +}; + +&serial_0 { + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_1 { + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_2 { + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; +}; + +&serial_3 { + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; }; diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi new file mode 100644 index 0000000000..8adf455744 --- /dev/null +++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi @@ -0,0 +1,479 @@ +/* + * Hardkernel Odroid XU3 board device tree source + * + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include "exynos5800.dtsi" + +/ { + memory { + reg = <0x40000000 0x7EA00000>; + }; + + chosen { + linux,stdout-path = &serial_2; + }; + + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + emmc_pwrseq: pwrseq { + pinctrl-0 = <&emmc_nrst_pin>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpd1 0 1>; + }; + + pwmleds { + compatible = "pwm-leds"; + + greenled { + label = "green:mmc0"; + pwms = <&pwm 1 2000000 0>; + pwm-names = "pwm1"; + /* + * Green LED is much brighter than the others + * so limit its max brightness + */ + max_brightness = <127>; + linux,default-trigger = "mmc0"; + }; + + blueled { + label = "blue:heartbeat"; + pwms = <&pwm 2 2000000 0>; + pwm-names = "pwm2"; + max_brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + redled { + label = "red:microSD"; + gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + }; + + sound: sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "Odroid-XU3"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speakers", "Speakers"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + system-clock-frequency = <19200000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&max98090>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + }; + }; +}; + +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FIN_PLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, + <0>, + <19200000>; +}; + +&fimd { + status = "okay"; +}; + + +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; + vdd-supply = <&ldo6_reg>; +}; + +&hsi2c_4 { + status = "okay"; + + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + s2mps11,buck2-ramp-delay = <12>; + s2mps11,buck34-ramp-delay = <12>; + s2mps11,buck16-ramp-delay = <12>; + s2mps11,buck6-ramp-enable = <1>; + s2mps11,buck2-ramp-enable = <1>; + s2mps11,buck3-ramp-enable = <1>; + s2mps11,buck4-ramp-enable = <1>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "vdd_ldo16"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "tsp_avdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_mem"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1.0v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_1.8v_ldo"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2.8v_ldo"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_vmem"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&hsi2c_5 { + status = "okay"; + max98090: max98090@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpx3>; + interrupts = <2 0>; + clocks = <&i2s0 CLK_I2S_CDCLK>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2c_2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + status = "okay"; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + mmc-pwrseq = <&emmc_pwrseq>; + cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&mmc_2 { + status = "okay"; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + +&pinctrl_0 { + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + s2mps11_irq: s2mps11-irq { + samsung,pins = "gpx0-4"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + emmc_nrst_pin: emmc-nrst { + samsung,pins = "gpd1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pwm { + /* + * PWM 0 -- fan + * PWM 1 -- Green LED + * PWM 2 -- Blue LED + * PWM 3 -- on MIPI connector for backlight + */ + pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "otg"; +}; diff --git a/dts/src/arm/exynos5422-odroidxu3-lite.dts b/dts/src/arm/exynos5422-odroidxu3-lite.dts new file mode 100644 index 0000000000..c06882bbb8 --- /dev/null +++ b/dts/src/arm/exynos5422-odroidxu3-lite.dts @@ -0,0 +1,20 @@ +/* + * Hardkernel Odroid XU3-Lite board device tree source + * + * Copyright (c) 2015 Krzysztof Kozlowski + * Copyright (c) 2014 Collabora Ltd. + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5422-odroidxu3-common.dtsi" + +/ { + model = "Hardkernel Odroid XU3 Lite"; + compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; +}; diff --git a/dts/src/arm/exynos5422-odroidxu3.dts b/dts/src/arm/exynos5422-odroidxu3.dts index edc25cf1d7..78e6a502f3 100644 --- a/dts/src/arm/exynos5422-odroidxu3.dts +++ b/dts/src/arm/exynos5422-odroidxu3.dts @@ -11,348 +11,11 @@ */ /dts-v1/; -#include "exynos5800.dtsi" +#include "exynos5422-odroidxu3-common.dtsi" / { model = "Hardkernel Odroid XU3"; compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; - - memory { - reg = <0x40000000 0x7EA00000>; - }; - - chosen { - linux,stdout-path = &serial_2; - }; - - fimd@14400000 { - status = "okay"; - }; - - firmware@02073000 { - compatible = "samsung,secure-firmware"; - reg = <0x02073000 0x1000>; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - hsi2c_4: i2c@12CA0000 { - status = "okay"; - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; - - s2mps11_osc: clocks { - #clock-cells = <1>; - clock-output-names = "s2mps11_ap", - "s2mps11_cp", "s2mps11_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "vdd_ldo16"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "tsp_avdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo24_reg: LDO24 { - regulator-name = "tsp_io"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_mem"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2.8v_ldo"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3750000>; - regulator-always-on; - regulator-boot-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_vmem"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - - emmc_pwrseq: pwrseq { - pinctrl-0 = <&emmc_nrst_pin>; - pinctrl-names = "default"; - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpd1 0 1>; - }; - - i2c_2: i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - rtc@101E0000 { - status = "okay"; - }; -}; - -&hdmi { - status = "okay"; - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - vdd-supply = <&ldo6_reg>; -}; - -&mfc { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; -}; - -&mmc_0 { - status = "okay"; - mmc-pwrseq = <&emmc_pwrseq>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_1 { - emmc_nrst_pin: emmc-nrst { - samsung,pins = "gpd1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "otg"; }; &i2c_0 { diff --git a/dts/src/arm/exynos5440-sd5v1.dts b/dts/src/arm/exynos5440-sd5v1.dts index 268609a42b..a98501bab6 100644 --- a/dts/src/arm/exynos5440-sd5v1.dts +++ b/dts/src/arm/exynos5440-sd5v1.dts @@ -27,13 +27,13 @@ }; }; - gmac: ethernet@00230000 { - fixed_phy; - phy_addr = <1>; - }; - spi { status = "disabled"; }; }; + +&gmac { + fixed_phy; + phy_addr = <1>; +}; diff --git a/dts/src/arm/exynos5440-ssdk5440.dts b/dts/src/arm/exynos5440-ssdk5440.dts index ff55dac6e2..e4443f4e65 100644 --- a/dts/src/arm/exynos5440-ssdk5440.dts +++ b/dts/src/arm/exynos5440-ssdk5440.dts @@ -20,59 +20,58 @@ bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; - spi_0: spi@D0000 { - - flash: w25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128"; - spi-max-frequency = <15625000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <0>; - }; + fixed-rate-clocks { + xtal { + compatible = "samsung,clock-xtal"; + clock-frequency = <50000000>; + }; + }; +}; - partition@00000 { - label = "BootLoader"; - reg = <0x60000 0x80000>; - read-only; - }; +&pcie_0 { + reset-gpio = <&pin_ctrl 5 0>; + status = "okay"; +}; - partition@e0000 { - label = "Recovery-Kernel"; - reg = <0xe0000 0x300000>; - read-only; - }; +&pcie_1 { + reset-gpio = <&pin_ctrl 22 0>; + status = "okay"; +}; - partition@3e0000 { - label = "CRAM-FS"; - reg = <0x3e0000 0x700000>; - read-only; - }; +&spi_0 { + flash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128"; + spi-max-frequency = <15625000>; + reg = <0>; + controller-data { + samsung,spi-feedback-delay = <0>; + }; - partition@ae0000 { - label = "User-Data"; - reg = <0xae0000 0x520000>; - }; + partition@00000 { + label = "BootLoader"; + reg = <0x60000 0x80000>; + read-only; + }; + partition@e0000 { + label = "Recovery-Kernel"; + reg = <0xe0000 0x300000>; + read-only; }; - }; + partition@3e0000 { + label = "CRAM-FS"; + reg = <0x3e0000 0x700000>; + read-only; + }; - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; + partition@ae0000 { + label = "User-Data"; + reg = <0xae0000 0x520000>; }; - }; - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - status = "okay"; }; - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - status = "okay"; - }; }; diff --git a/dts/src/arm/exynos5440.dtsi b/dts/src/arm/exynos5440.dtsi index 59d9416b3b..f18b51f2ee 100644 --- a/dts/src/arm/exynos5440.dtsi +++ b/dts/src/arm/exynos5440.dtsi @@ -279,7 +279,7 @@ clock-names = "usbhost"; }; - pcie@290000 { + pcie_0: pcie@290000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; reg = <0x290000 0x1000 0x270000 0x1000 @@ -300,7 +300,7 @@ status = "disabled"; }; - pcie@2a0000 { + pcie_1: pcie@2a0000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; reg = <0x2a0000 0x1000 0x272000 0x1000 diff --git a/dts/src/arm/exynos5800-peach-pi.dts b/dts/src/arm/exynos5800-peach-pi.dts index 02eb8b1537..7d5b386b5a 100644 --- a/dts/src/arm/exynos5800-peach-pi.dts +++ b/dts/src/arm/exynos5800-peach-pi.dts @@ -990,7 +990,7 @@ }; }; -&uart_3 { +&serial_3 { status = "okay"; }; diff --git a/dts/src/arm/imx23-olinuxino.dts b/dts/src/arm/imx23-olinuxino.dts index 82045398bf..a8b1c53ebe 100644 --- a/dts/src/arm/imx23-olinuxino.dts +++ b/dts/src/arm/imx23-olinuxino.dts @@ -74,6 +74,12 @@ status = "okay"; }; + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_b>; + status = "okay"; + }; + duart: serial@80070000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; diff --git a/dts/src/arm/imx23.dtsi b/dts/src/arm/imx23.dtsi index bbcfb5a19c..c892d58e8d 100644 --- a/dts/src/arm/imx23.dtsi +++ b/dts/src/arm/imx23.dtsi @@ -308,6 +308,39 @@ fsl,voltage = ; fsl,pull-up = ; }; + + i2c_pins_a: i2c@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_I2C_SCL__I2C_SCL + MX23_PAD_I2C_SDA__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c_pins_b: i2c@1 { + reg = <1>; + fsl,pinmux-ids = < + MX23_PAD_LCD_ENABLE__I2C_SCL + MX23_PAD_LCD_HSYNC__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2c_pins_c: i2c@2 { + reg = <2>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DATA1__I2C_SCL + MX23_PAD_SSP1_DATA2__I2C_SDA + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; }; digctl@8001c000 { @@ -444,8 +477,13 @@ status = "disabled"; }; - i2c@80058000 { + i2c: i2c@80058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-i2c"; reg = <0x80058000 0x2000>; + interrupts = <27>; + clock-frequency = <100000>; dmas = <&dma_apbx 3>; dma-names = "rx-tx"; status = "disabled"; diff --git a/dts/src/arm/imx28-cfa10036.dts b/dts/src/arm/imx28-cfa10036.dts index b04b6b8850..570aa339a0 100644 --- a/dts/src/arm/imx28-cfa10036.dts +++ b/dts/src/arm/imx28-cfa10036.dts @@ -99,6 +99,9 @@ solomon,height = <32>; solomon,width = <128>; solomon,page-offset = <0>; + solomon,com-lrremap; + solomon,com-invdir; + solomon,com-offset = <32>; }; }; diff --git a/dts/src/arm/imx6dl-apf6dev.dts b/dts/src/arm/imx6dl-apf6dev.dts new file mode 100644 index 0000000000..df26e542ab --- /dev/null +++ b/dts/src/arm/imx6dl-apf6dev.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-apf6.dtsi" +#include "imx6qdl-apf6dev.dtsi" + +/ { + model = "Armadeus APF6 Solo Module on APF6Dev Board"; + compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/dts/src/arm/imx6dl-aristainetos2_4.dts b/dts/src/arm/imx6dl-aristainetos2_4.dts new file mode 100644 index 0000000000..bb92f309c1 --- /dev/null +++ b/dts/src/arm/imx6dl-aristainetos2_4.dts @@ -0,0 +1,159 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + display0: display@di0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + + port@0 { + reg = <0>; + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&ecspi1 { + lcd_panel: display@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <0>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 + >; + }; +}; diff --git a/dts/src/arm/imx6dl-aristainetos2_7.dts b/dts/src/arm/imx6dl-aristainetos2_7.dts new file mode 100644 index 0000000000..3d5ad2cc7e --- /dev/null +++ b/dts/src/arm/imx6dl-aristainetos2_7.dts @@ -0,0 +1,97 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + panel: panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/dts/src/arm/imx6dl-cubox-i.dts b/dts/src/arm/imx6dl-cubox-i.dts index e0b7fe8e18..2a43917d04 100644 --- a/dts/src/arm/imx6dl-cubox-i.dts +++ b/dts/src/arm/imx6dl-cubox-i.dts @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6dl-gw551x.dts b/dts/src/arm/imx6dl-gw551x.dts new file mode 100644 index 0000000000..82d5f85722 --- /dev/null +++ b/dts/src/arm/imx6dl-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; + compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/dts/src/arm/imx6dl-hummingboard.dts b/dts/src/arm/imx6dl-hummingboard.dts index 7369d2d7da..d5c9660319 100644 --- a/dts/src/arm/imx6dl-hummingboard.dts +++ b/dts/src/arm/imx6dl-hummingboard.dts @@ -8,9 +8,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi index f94bf72832..4b0ec07038 100644 --- a/dts/src/arm/imx6dl.dtsi +++ b/dts/src/arm/imx6dl.dtsi @@ -106,6 +106,10 @@ }; }; +&gpt { + compatible = "fsl,imx6dl-gpt", "fsl,imx6q-gpt"; +}; + &hdmi { compatible = "fsl,imx6dl-hdmi"; }; diff --git a/dts/src/arm/imx6q-apf6dev.dts b/dts/src/arm/imx6q-apf6dev.dts new file mode 100644 index 0000000000..4e4de821d9 --- /dev/null +++ b/dts/src/arm/imx6q-apf6dev.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-apf6.dtsi" +#include "imx6qdl-apf6dev.dtsi" + +/ { + model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board"; + compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/dts/src/arm/imx6q-cubox-i.dts b/dts/src/arm/imx6q-cubox-i.dts index 670bd8c4c8..353425edcd 100644 --- a/dts/src/arm/imx6q-cubox-i.dts +++ b/dts/src/arm/imx6q-cubox-i.dts @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6q-gw551x.dts b/dts/src/arm/imx6q-gw551x.dts new file mode 100644 index 0000000000..2c7feeef1b --- /dev/null +++ b/dts/src/arm/imx6q-gw551x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw551x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; + compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/dts/src/arm/imx6q-hummingboard.dts b/dts/src/arm/imx6q-hummingboard.dts index 0f6044553a..1884c16784 100644 --- a/dts/src/arm/imx6q-hummingboard.dts +++ b/dts/src/arm/imx6q-hummingboard.dts @@ -8,9 +8,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6qdl-apf6.dtsi b/dts/src/arm/imx6qdl-apf6.dtsi new file mode 100644 index 0000000000..1ebf29f43a --- /dev/null +++ b/dts/src/arm/imx6qdl-apf6.dtsi @@ -0,0 +1,158 @@ +/* + * Copyright 2015 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Bluetooth */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Wi-Fi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + tcxo-clock-frequency = <38400000>; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + apf6 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; diff --git a/dts/src/arm/imx6qdl-apf6dev.dtsi b/dts/src/arm/imx6qdl-apf6dev.dtsi new file mode 100644 index 0000000000..e26ebeb5b4 --- /dev/null +++ b/dts/src/arm/imx6qdl-apf6dev.dtsi @@ -0,0 +1,479 @@ +/* + * Copyright 2015 Armadeus Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + display@di0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp1>; + + display-timings { + lw700 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port { + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-button { + label = "User button"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user-led { + label = "User LED"; + gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + + sound { + compatible = "fsl,imx6-armadeus-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-armadeus-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 10 GPIO_ACTIVE_LOW>, + <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@48 { + compatible = "semtech,sx8654"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* GSM */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + dr_mode = "otg"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + apf6dev { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1 + >; + }; + + pinctrl_gsm: gsmgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp1: ipu1disp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + >; + }; + }; +}; diff --git a/dts/src/arm/imx6qdl-aristainetos2.dtsi b/dts/src/arm/imx6qdl-aristainetos2.dtsi new file mode 100644 index 0000000000..1d85de2bef --- /dev/null +++ b/dts/src/arm/imx6qdl-aristainetos2.dtsi @@ -0,0 +1,633 @@ +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2015 Heiko Schocher + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + flash: m25p80@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11"; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <04 0x8>; + + regulators { + bcore1 { + regulator-name = "bcore1"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bcore2 { + regulator-name = "bcore2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bpro { + regulator-name = "bpro"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bperi { + regulator-name = "bperi"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bmem { + regulator-name = "bmem"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3 { + regulator-name = "ldo3"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "ldo4"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "ldo5"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "ldo6"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "ldo7"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8 { + regulator-name = "ldo8"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9 { + regulator-name = "ldo9"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo10 { + regulator-name = "ldo10"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo11 { + regulator-name = "ldo11"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bio { + regulator-name = "bio"; + regulator-always-on = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + expander: tca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@68 { + compatible = "dallas,m41t00"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50{ + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */ + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = ; + }; + + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */ + >; + }; +}; diff --git a/dts/src/arm/imx6qdl-cubox-i.dtsi b/dts/src/arm/imx6qdl-cubox-i.dtsi index d033bb1820..59e5d15e3e 100644 --- a/dts/src/arm/imx6qdl-cubox-i.dtsi +++ b/dts/src/arm/imx6qdl-cubox-i.dtsi @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6qdl-gw551x.dtsi b/dts/src/arm/imx6qdl-gw551x.dtsi new file mode 100644 index 0000000000..d1866a0a2f --- /dev/null +++ b/dts/src/arm/imx6qdl-gw551x.dtsi @@ -0,0 +1,314 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + nand = &gpmi; + ssi0 = &ssi1; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_5p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + gpio_exp: pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw51xx { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + }; +}; diff --git a/dts/src/arm/imx6qdl-hummingboard.dtsi b/dts/src/arm/imx6qdl-hummingboard.dtsi index 151a3db2ae..62a82f3eba 100644 --- a/dts/src/arm/imx6qdl-hummingboard.dtsi +++ b/dts/src/arm/imx6qdl-hummingboard.dtsi @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -192,6 +191,12 @@ >; }; + pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { + fsl,pins = < + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 + >; + }; + pinctrl_hummingboard_pwm1: pwm1grp { fsl,pins = ; }; @@ -245,6 +250,13 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; + reset-gpio = <&gpio3 4 0>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_pwm1>; @@ -263,7 +275,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/dts/src/arm/imx6qdl-microsom-ar8035.dtsi b/dts/src/arm/imx6qdl-microsom-ar8035.dtsi index 4a1820309c..469ef58ce4 100644 --- a/dts/src/arm/imx6qdl-microsom-ar8035.dtsi +++ b/dts/src/arm/imx6qdl-microsom-ar8035.dtsi @@ -10,9 +10,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/dts/src/arm/imx6qdl-microsom.dtsi b/dts/src/arm/imx6qdl-microsom.dtsi index 349f82be81..6d4069cc94 100644 --- a/dts/src/arm/imx6qdl-microsom.dtsi +++ b/dts/src/arm/imx6qdl-microsom.dtsi @@ -7,9 +7,8 @@ * whole. * * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -39,15 +38,98 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ +#include +/ { + clk_sdio: sdio-clock { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_osc>; + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + + reg_brcm: brcm-reg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + }; + + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, + <&gpio6 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_sdio>; + clock-names = "ext_clock"; + }; +}; &iomuxc { microsom { + pinctrl_microsom_brcm_bt: microsom-brcm-bt { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 + >; + }; + + pinctrl_microsom_brcm_osc: microsom-brcm-osc { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 + >; + }; + + pinctrl_microsom_brcm_reg: microsom-brcm-reg { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 + >; + }; + + pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { + fsl,pins = < + MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 + >; + }; + pinctrl_microsom_uart1: microsom-uart1 { fsl,pins = < MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; + + pinctrl_microsom_uart4: microsom-uart4 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_microsom_usdhc1: microsom-usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; }; }; @@ -56,3 +138,23 @@ pinctrl-0 = <&pinctrl_microsom_uart1>; status = "okay"; }; + +/* UART4 - Connected to optional BRCM Wifi/BT/FM */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_brcm>; + status = "okay"; +}; diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi index 08218120e7..3af16dfe41 100644 --- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi @@ -122,7 +122,7 @@ status = "okay"; }; - backlight_lvds { + backlight_lvds: backlight_lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -130,6 +130,17 @@ power-supply = <®_3p3v>; status = "okay"; }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &audmux { @@ -379,18 +390,11 @@ fsl,data-width = <18>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi index 0b28a9d524..e00c44f6a0 100644 --- a/dts/src/arm/imx6qdl-sabrelite.dtsi +++ b/dts/src/arm/imx6qdl-sabrelite.dtsi @@ -121,7 +121,7 @@ status = "okay"; }; - backlight_lvds { + backlight_lvds: backlight_lvds { compatible = "pwm-backlight"; pwms = <&pwm4 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -129,6 +129,17 @@ power-supply = <®_3p3v>; status = "okay"; }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &audmux { @@ -374,18 +385,11 @@ fsl,data-width = <18>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi index f74a8ded51..e6d1359208 100644 --- a/dts/src/arm/imx6qdl.dtsi +++ b/dts/src/arm/imx6qdl.dtsi @@ -119,6 +119,34 @@ status = "disabled"; }; + hdmi: hdmi@0120000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HDMI_ISFR>; + clock-names = "iahb", "isfr"; + status = "disabled"; + + port@0 { + reg = <0>; + + hdmi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_hdmi>; + }; + }; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -343,6 +371,7 @@ clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; clock-names = "per", "ahb"; + power-domains = <&gpc 1>; resets = <&src 1>; iram = <&ocram>; }; @@ -778,34 +807,6 @@ }; }; - hdmi: hdmi@0120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; - dcic1: dcic@020e4000 { reg = <0x020e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/imx6sl-warp.dts b/dts/src/arm/imx6sl-warp.dts index 64f7decf1f..0da906bd8d 100644 --- a/dts/src/arm/imx6sl-warp.dts +++ b/dts/src/arm/imx6sl-warp.dts @@ -58,40 +58,6 @@ reg = <0x80000000 0x20000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 0>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 0>; - enable-active-high; - }; - - reg_1p8v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ @@ -121,14 +87,13 @@ }; &usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - dr_mode = "host"; + dr_mode = "peripheral"; disable-over-current; status = "okay"; }; &usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; disable-over-current; status = "okay"; }; diff --git a/dts/src/arm/imx7d-pinfunc.h b/dts/src/arm/imx7d-pinfunc.h new file mode 100644 index 0000000000..a8d81497ed --- /dev/null +++ b/dts/src/arm/imx7d-pinfunc.h @@ -0,0 +1,1038 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX7D_PINFUNC_H +#define __DTS_IMX7D_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ + +#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 +#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 +#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 +#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 +#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 +#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 +#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 +#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 +#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 +#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 +#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 +#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 +#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 +#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 +#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 +#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 +#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 +#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 +#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 +#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 +#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 +#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 +#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 +#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 +#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 +#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 +#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 +#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 +#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 +#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 +#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 +#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 +#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 +#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 +#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 +#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 +#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 +#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 +#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 +#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 +#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 +#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 +#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 +#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 +#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 +#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 +#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 +#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 +#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 +#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 +#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 +#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 +#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 +#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 +#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 +#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 +#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 +#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 +#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 +#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 +#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 +#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 +#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 +#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 +#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 +#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 +#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 +#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 +#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 +#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 +#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 +#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 +#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 +#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 +#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 +#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 +#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 +#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 +#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 +#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 +#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 +#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 +#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 +#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 +#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 +#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 +#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 +#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 +#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 +#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 +#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 +#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 +#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 +#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 +#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 +#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 +#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 +#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 +#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 +#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 +#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 +#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 +#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 +#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 +#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 +#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 +#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 +#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 +#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 +#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 +#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 +#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 +#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 +#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 +#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 +#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 +#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 +#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 +#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 +#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 +#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 +#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 +#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 +#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 +#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 +#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 +#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 +#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 +#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 +#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 +#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 +#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 +#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 +#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 +#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 +#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 +#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 +#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 +#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 +#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 +#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 +#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 +#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 +#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 +#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 +#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 +#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 +#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 +#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 +#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 +#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 +#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 +#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 +#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 +#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 +#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 +#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 +#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 +#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 +#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 +#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 +#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 +#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 +#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 +#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 +#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 +#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 +#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 +#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 +#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 +#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 +#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 +#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 +#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 +#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 +#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 +#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 +#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 +#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 +#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 +#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 +#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 +#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 +#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 +#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 +#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 +#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 +#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 +#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 +#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 +#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 +#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 +#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 +#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 +#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 +#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 +#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 +#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 +#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 +#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 +#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 +#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 +#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 +#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 +#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 +#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 +#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 +#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 +#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 +#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 +#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 +#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 +#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 +#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 +#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 +#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 +#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 +#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 +#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 +#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 +#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 +#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 +#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 +#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 +#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 +#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 +#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 +#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 +#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 +#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 +#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 +#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 +#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 +#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 +#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 +#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 +#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 +#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 +#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 +#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 +#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 +#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 +#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 +#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 +#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 +#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 +#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 +#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 +#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 +#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 +#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 +#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 +#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 +#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 + +#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts new file mode 100644 index 0000000000..4d1a4b977d --- /dev/null +++ b/dts/src/arm/imx7d-sdb.dts @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 SabreSD Board"; + compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_3v3: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_vref_1v8: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 0>; + wp-gpios = <&gpio5 1 0>; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx7d-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + }; +}; diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi new file mode 100644 index 0000000000..c42cf8db04 --- /dev/null +++ b/dts/src/arm/imx7d.dtsi @@ -0,0 +1,486 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>, + <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>; + clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x1000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = , /* GPIO1_INT15_0 */ + ; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt1: gpt@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = , + ; + + reg_1p0d: regulator-vdd1p0d@210 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <31>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x30370000 0x10000>; + + snvs-rtc-lp@34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = , + ; + }; + }; + + clks: ccm@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src@30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = ; + #reset-cells = <1>; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30870000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30870000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + }; + }; +}; diff --git a/dts/src/arm/integrator.dtsi b/dts/src/arm/integrator.dtsi index 28e38f8c6b..3807d4f46e 100644 --- a/dts/src/arm/integrator.dtsi +++ b/dts/src/arm/integrator.dtsi @@ -6,7 +6,7 @@ / { core-module@10000000 { - compatible = "arm,core-module-integrator", "syscon"; + compatible = "arm,core-module-integrator", "syscon", "simple-mfd"; reg = <0x10000000 0x200>; /* Use core module LED to indicate CPU load */ @@ -95,7 +95,7 @@ syscon { /* Debug registers mapped as syscon */ - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x1a000000 0x10>; led@04.0 { diff --git a/dts/src/arm/k2e-evm.dts b/dts/src/arm/k2e-evm.dts index 560d62150a..50c83c21d9 100644 --- a/dts/src/arm/k2e-evm.dts +++ b/dts/src/arm/k2e-evm.dts @@ -141,6 +141,7 @@ }; &mdio { + status = "ok"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/dts/src/arm/k2e-netcp.dtsi b/dts/src/arm/k2e-netcp.dtsi new file mode 100644 index 0000000000..b13b3c94e7 --- /dev/null +++ b/dts/src/arm/k2e-netcp.dtsi @@ -0,0 +1,206 @@ +/* + * Device Tree Source for Keystone 2 Edison Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x24186000 0x100>, + <0x24187000 0x2a0>, + <0x24188000 0xb60>, + <0x24186100 0x80>, + <0x24189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@24000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x24000000 0x1000000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-9"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + port-4 { + slave-port = <4>; + link-interface = <2>; + }; + port-5 { + slave-port = <5>; + link-interface = <2>; + }; + port-6 { + slave-port = <6>; + link-interface = <2>; + }; + port-7 { + slave-port = <7>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 00]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/dts/src/arm/k2e.dtsi b/dts/src/arm/k2e.dtsi index 5fc14683d6..50e555eab5 100644 --- a/dts/src/arm/k2e.dtsi +++ b/dts/src/arm/k2e.dtsi @@ -130,6 +130,7 @@ ; }; }; + /include/ "k2e-netcp.dtsi" }; }; diff --git a/dts/src/arm/k2hk-evm.dts b/dts/src/arm/k2hk-evm.dts index 3223cc152a..660ebf58d5 100644 --- a/dts/src/arm/k2hk-evm.dts +++ b/dts/src/arm/k2hk-evm.dts @@ -169,6 +169,7 @@ }; &mdio { + status = "ok"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/dts/src/arm/k2hk-netcp.dtsi b/dts/src/arm/k2hk-netcp.dtsi new file mode 100644 index 0000000000..77a32c3c17 --- /dev/null +++ b/dts/src/arm/k2hk-netcp.dtsi @@ -0,0 +1,208 @@ +/* + * Device Tree Source for Keystone 2 Hawking Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + + qmgr1 { + managed-queues = <0x2000 0x2000>; + reg = <0x2a60000 0x20000>, + <0x2a06400 0x400>, + <0x2a04000 0x1000>, + <0x2a05000 0x1000>, + <0x23aa0000 0x20000>, + <0x2aa0000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <8704 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <8720 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <640 9>; + qalloc-by-id; + }; + netcpx-tx { + qrange = <8752 8>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23aa0000 0x23ab0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x2004000 0x100>, + <0x2004400 0x120>, + <0x2004800 0x300>, + <0x2004c00 0x120>, + <0x2005000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@2000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x2000000 0x100000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 22>, + <&dma_gbe 23>, + <&dma_gbe 8>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + ranges; + #address-cells = <1>; + #size-cells = <1>; + gbe@90000 { /* ETHSS */ + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-gbe"; + compatible = "ti,netcp-gbe"; + reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; + /* enable-ale; */ + tx-queue = <648>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8704>; + tx-completion-queue = <8706>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8705>; + tx-completion-queue = <8707>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 6f]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/dts/src/arm/k2hk.dtsi b/dts/src/arm/k2hk.dtsi index d721f4b737..ae6472407b 100644 --- a/dts/src/arm/k2hk.dtsi +++ b/dts/src/arm/k2hk.dtsi @@ -98,5 +98,6 @@ #gpio-cells = <2>; gpio,syscon-dev = <&devctrl 0x25c>; }; + /include/ "k2hk-netcp.dtsi" }; }; diff --git a/dts/src/arm/k2l-evm.dts b/dts/src/arm/k2l-evm.dts index 85cc7f2872..9a69a6b553 100644 --- a/dts/src/arm/k2l-evm.dts +++ b/dts/src/arm/k2l-evm.dts @@ -118,6 +118,7 @@ }; &mdio { + status = "ok"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/dts/src/arm/k2l-netcp.dtsi b/dts/src/arm/k2l-netcp.dtsi new file mode 100644 index 0000000000..6b95284d11 --- /dev/null +++ b/dts/src/arm/k2l-netcp.dtsi @@ -0,0 +1,189 @@ +/* + * Device Tree Source for Keystone 2 Lamarr Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + }; + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x26186000 0x100>, + <0x26187000 0x2a0>, + <0x26188000 0xb60>, + <0x26186100 0x80>, + <0x26189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +netcp: netcp@26000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x26000000 0x1000000>; + + clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>; + ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-5"; + reg = <0x200000 0x900>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 7f]; + netcp-gbe = <&gbe1>; + }; + }; +}; diff --git a/dts/src/arm/k2l.dtsi b/dts/src/arm/k2l.dtsi index e32c3baa77..0e00748361 100644 --- a/dts/src/arm/k2l.dtsi +++ b/dts/src/arm/k2l.dtsi @@ -79,6 +79,7 @@ #gpio-cells = <2>; gpio,syscon-dev = <&devctrl 0x24c>; }; + /include/ "k2l-netcp.dtsi" }; }; diff --git a/dts/src/arm/kirkwood-b3.dts b/dts/src/arm/kirkwood-b3.dts index c9247f8672..d2936ad3af 100644 --- a/dts/src/arm/kirkwood-b3.dts +++ b/dts/src/arm/kirkwood-b3.dts @@ -74,7 +74,7 @@ m25p16@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p16"; + compatible = "st,m25p16", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-cloudbox.dts b/dts/src/arm/kirkwood-cloudbox.dts index ab6ab4933e..7ec76566ac 100644 --- a/dts/src/arm/kirkwood-cloudbox.dts +++ b/dts/src/arm/kirkwood-cloudbox.dts @@ -42,7 +42,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l4005a"; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-dir665.dts b/dts/src/arm/kirkwood-dir665.dts index 786959ee9c..0473fcc260 100644 --- a/dts/src/arm/kirkwood-dir665.dts +++ b/dts/src/arm/kirkwood-dir665.dts @@ -93,7 +93,7 @@ m25p80@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l12805d"; + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/src/arm/kirkwood-dreamplug.dts b/dts/src/arm/kirkwood-dreamplug.dts index 6467c79241..e2abc8246b 100644 --- a/dts/src/arm/kirkwood-dreamplug.dts +++ b/dts/src/arm/kirkwood-dreamplug.dts @@ -42,7 +42,7 @@ m25p40@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l1606e"; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-lsxl.dtsi b/dts/src/arm/kirkwood-lsxl.dtsi index 53484474df..1d6528d829 100644 --- a/dts/src/arm/kirkwood-lsxl.dtsi +++ b/dts/src/arm/kirkwood-lsxl.dtsi @@ -74,7 +74,7 @@ m25p40@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "m25p40"; + compatible = "m25p40", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-mv88f6281gtw-ge.dts b/dts/src/arm/kirkwood-mv88f6281gtw-ge.dts index f82827d6fc..b7e7d78c48 100644 --- a/dts/src/arm/kirkwood-mv88f6281gtw-ge.dts +++ b/dts/src/arm/kirkwood-mv88f6281gtw-ge.dts @@ -65,7 +65,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l12805d"; + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-netxbig.dtsi b/dts/src/arm/kirkwood-netxbig.dtsi index b0cfb7cd30..1508b12147 100644 --- a/dts/src/arm/kirkwood-netxbig.dtsi +++ b/dts/src/arm/kirkwood-netxbig.dtsi @@ -33,7 +33,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l4005a"; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-ns2-common.dtsi b/dts/src/arm/kirkwood-ns2-common.dtsi index fe6c0246db..e832b63202 100644 --- a/dts/src/arm/kirkwood-ns2-common.dtsi +++ b/dts/src/arm/kirkwood-ns2-common.dtsi @@ -29,7 +29,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l4005a"; + compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-rd88f6192.dts b/dts/src/arm/kirkwood-rd88f6192.dts index 35a29dee8d..e0b959396c 100644 --- a/dts/src/arm/kirkwood-rd88f6192.dts +++ b/dts/src/arm/kirkwood-rd88f6192.dts @@ -61,7 +61,7 @@ m25p128@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p128"; + compatible = "st,m25p128", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-synology.dtsi b/dts/src/arm/kirkwood-synology.dtsi index 8be5b2e462..04015c174b 100644 --- a/dts/src/arm/kirkwood-synology.dtsi +++ b/dts/src/arm/kirkwood-synology.dtsi @@ -217,7 +217,7 @@ m25p80@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p80"; + compatible = "st,m25p80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kirkwood-t5325.dts b/dts/src/arm/kirkwood-t5325.dts index 610ec0f958..ed956b849a 100644 --- a/dts/src/arm/kirkwood-t5325.dts +++ b/dts/src/arm/kirkwood-t5325.dts @@ -88,7 +88,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p80"; + compatible = "st,m25p80", "jedec,spi-nor"; spi-max-frequency = <86000000>; reg = <0>; mode = <0>; diff --git a/dts/src/arm/kirkwood-ts219.dtsi b/dts/src/arm/kirkwood-ts219.dtsi index df7f152765..c56ab6bbfe 100644 --- a/dts/src/arm/kirkwood-ts219.dtsi +++ b/dts/src/arm/kirkwood-ts219.dtsi @@ -49,7 +49,7 @@ m25p128@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "m25p128"; + compatible = "m25p128", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; mode = <0>; diff --git a/dts/src/arm/kizbox.dts b/dts/src/arm/kizbox.dts deleted file mode 100644 index e83e4f9310..0000000000 --- a/dts/src/arm/kizbox.dts +++ /dev/null @@ -1,150 +0,0 @@ -/* - * kizbox.dts - Device Tree file for Overkiz Kizbox board - * - * Copyright (C) 2012 Boris BREZILLON - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9g20.dtsi" - -/ { - - model = "Overkiz kizbox"; - compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9"; - - chosen { - bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root"; - }; - - memory { - reg = <0x20000000 0x2000000>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <18432000>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "mii"; - pinctrl-0 = <&pinctrl_macb_rmii - &pinctrl_macb_rmii_mii_alt>; - status = "okay"; - }; - - watchdog@fffffd40 { - timeout-sec = <15>; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - status = "okay"; - - bootloaderkernel@0 { - label = "bootloader-kernel"; - reg = <0x0 0xc0000>; - }; - - ubi@c0000 { - label = "ubi"; - reg = <0xc0000 0x7f40000>; - }; - - }; - - usb0: ohci@00500000 { - num-ports = <1>; - status = "okay"; - }; - }; - - i2c@0 { - status = "okay"; - - pcf8563@51 { - /* nxp pcf8563 rtc */ - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - }; - - leds { - compatible = "gpio-leds"; - - led1g { - label = "led1:green"; - gpios = <&pioB 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led1r { - label = "led1:red"; - gpios = <&pioB 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - - led2g { - label = "led2:green"; - gpios = <&pioB 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "on"; - }; - - led2r { - label = "led2:red"; - gpios = <&pioB 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - reset { - label = "reset"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - gpio-key,wakeup; - }; - - mode { - label = "mode"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - gpio-key,wakeup; - }; - }; -}; diff --git a/dts/src/arm/logicpd-torpedo-37xx-devkit.dts b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts new file mode 100644 index 0000000000..91146c3187 --- /dev/null +++ b/dts/src/arm/logicpd-torpedo-37xx-devkit.dts @@ -0,0 +1,157 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "logicpd-torpedo-som.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom DM3730 Torpedo Development Kit"; + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap36xx"; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; + + sysboot2 { + label = "sysboot2"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ + linux,code = ; + gpio-key,wakeup; + }; + + sysboot5 { + label = "sysboot5"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ + linux,code = ; + gpio-key,wakeup; + }; + + gpio1 { + label = "gpio1"; + gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ + linux,code = ; + gpio-key,wakeup; + }; + + gpio2 { + label = "gpio2"; + gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ + linux,code = ; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led1 { + label = "led1"; + gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ + linux,default-trigger = "none"; + }; + }; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ + reg = <1 0 0xff>; + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd>; + cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; +}; + +&omap3_pmx_wkup { + gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; + + lan9221_pins: pinmux_lan9221_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ + >; + }; + + mmc1_cd: pinmux_mmc1_cd { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ + >; + }; +}; + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/dts/src/arm/logicpd-torpedo-som.dtsi b/dts/src/arm/logicpd-torpedo-som.dtsi new file mode 100644 index 0000000000..36387b1145 --- /dev/null +++ b/dts/src/arm/logicpd-torpedo-som.dtsi @@ -0,0 +1,162 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + leds { + compatible = "gpio-leds"; + user0 { + label = "user0"; + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ + linux,default-trigger = "none"; + }; + }; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 29 0>; /* gpio157 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; + }; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + linux,mtd-name = "micron,mt29f4g16abbda3w"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ + + x-loader@0 { + label = "x-loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "u-boot-env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "fs"; + reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/* + * Only found on the wireless SOM. For the SOM without wireless, the pins for + * MMC3 can be routed with jumpers to the second MMC slot on the devkit and + * gpio157 is not connected. So this should be OK to keep common for now, + * probably device tree overlays is the way to go with the various SOM and + * jumpering combinations for the long run. + */ +&mmc3 { + interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; + pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; + pinctrl-names = "default"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + ref-clock-frequency = <26000000>; + }; +}; + +&omap3_pmx_core { + mmc3_pins: pinmux_mm3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ + >; + }; +}; + +&omap3_pmx_core2 { + mmc3_core2_pins: pinmux_mmc3_core2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ + OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ + >; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl { + twl_power: power { + compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; + ti,use_poweroff; + }; +}; + +&twl_gpio { + ti,use-leds; +}; diff --git a/dts/src/arm/lpc18xx.dtsi b/dts/src/arm/lpc18xx.dtsi new file mode 100644 index 0000000000..204da5b52e --- /dev/null +++ b/dts/src/arm/lpc18xx.dtsi @@ -0,0 +1,114 @@ +/* + * Common base for NXP LPC18xx and LPC43xx devices. + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +#include "armv7-m.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m3"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + /* Temporary hardcode PLL1 until clk drivers are merged */ + pll1: pll1 { + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <12>; + }; + }; + + soc { + uart0: serial@40081000 { + compatible = "ns16550a"; + reg = <0x40081000 0x1000>; + reg-shift = <2>; + interrupts = <24>; + clocks = <&pll1>; + status = "disabled"; + }; + + uart1: serial@40082000 { + compatible = "ns16550a"; + reg = <0x40082000 0x1000>; + reg-shift = <2>; + interrupts = <25>; + clocks = <&pll1>; + status = "disabled"; + }; + + timer0: timer@40084000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40084000 0x1000>; + interrupts = <12>; + clocks = <&pll1>; + clock-names = "timerclk"; + }; + + timer1: timer@40085000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40085000 0x1000>; + interrupts = <13>; + clocks = <&pll1>; + clock-names = "timerclk"; + }; + + uart2: serial@400c1000 { + compatible = "ns16550a"; + reg = <0x400c1000 0x1000>; + reg-shift = <2>; + interrupts = <26>; + clocks = <&pll1>; + status = "disabled"; + }; + + uart3: serial@400c2000 { + compatible = "ns16550a"; + reg = <0x400c2000 0x1000>; + reg-shift = <2>; + interrupts = <27>; + clocks = <&pll1>; + status = "disabled"; + }; + + timer2: timer@400c3000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x400c3000 0x1000>; + interrupts = <14>; + clocks = <&pll1>; + clock-names = "timerclk"; + }; + + timer3: timer@400c4000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x400c4000 0x1000>; + interrupts = <15>; + clocks = <&pll1>; + clock-names = "timerclk"; + }; + }; +}; diff --git a/dts/src/arm/lpc4350-hitex-eval.dts b/dts/src/arm/lpc4350-hitex-eval.dts new file mode 100644 index 0000000000..d04072f408 --- /dev/null +++ b/dts/src/arm/lpc4350-hitex-eval.dts @@ -0,0 +1,45 @@ +/* + * Hitex LPC4350 Evaluation Board + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4350.dtsi" + +/ { + model = "Hitex LPC4350 Evaluation Board"; + compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x800000>; /* 8 MB */ + }; +}; + +&pll1 { + clock-mult = <15>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/lpc4350.dtsi b/dts/src/arm/lpc4350.dtsi new file mode 100644 index 0000000000..c4422f5870 --- /dev/null +++ b/dts/src/arm/lpc4350.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC4350 and LPC4330 SoC + * + * Copyright 2015 Ariel D'Alessandro + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4350", "nxp,lpc4330"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; diff --git a/dts/src/arm/lpc4357-ea4357-devkit.dts b/dts/src/arm/lpc4357-ea4357-devkit.dts new file mode 100644 index 0000000000..08a6f757f9 --- /dev/null +++ b/dts/src/arm/lpc4357-ea4357-devkit.dts @@ -0,0 +1,41 @@ +/* + * Embedded Artist LPC4357 Developer's Kit + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +/ { + model = "Embedded Artists' LPC4357 Developer's Kit"; + compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x2000000>; /* 32 MB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/lpc4357.dtsi b/dts/src/arm/lpc4357.dtsi new file mode 100644 index 0000000000..fb9ecc754e --- /dev/null +++ b/dts/src/arm/lpc4357.dtsi @@ -0,0 +1,39 @@ +/* + * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC + * + * Copyright 2015 Joachim Eastwood + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +/ { + compatible = "nxp,lpc4357"; + + cpus { + cpu@0 { + compatible = "arm,cortex-m4"; + }; + }; + + soc { + sram0: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + }; + + sram1: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + }; + + sram2: sram@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + }; + }; +}; diff --git a/dts/src/arm/mt8127.dtsi b/dts/src/arm/mt8127.dtsi index aaa786233d..ca3402e824 100644 --- a/dts/src/arm/mt8127.dtsi +++ b/dts/src/arm/mt8127.dtsi @@ -107,7 +107,7 @@ <0 0x10216000 0 0x2000>; }; - uart0: serial@11006000 { + uart0: serial@11002000 { compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; @@ -115,7 +115,7 @@ status = "disabled"; }; - uart1: serial@11007000 { + uart1: serial@11003000 { compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; @@ -123,7 +123,7 @@ status = "disabled"; }; - uart2: serial@11008000 { + uart2: serial@11004000 { compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; @@ -131,7 +131,7 @@ status = "disabled"; }; - uart3: serial@11009000 { + uart3: serial@11005000 { compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; diff --git a/dts/src/arm/mt8135-pinfunc.h b/dts/src/arm/mt8135-pinfunc.h new file mode 100644 index 0000000000..5a609875cb --- /dev/null +++ b/dts/src/arm/mt8135-pinfunc.h @@ -0,0 +1,1302 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DTS_MT8135_PINFUNC_H +#define __DTS_MT8135_PINFUNC_H + +#include + +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6) +#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7) + +#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6) +#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7) + +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6) +#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7) + +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6) +#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7) + +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6) +#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7) + +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5) +#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6) + +#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1) +#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2) +#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7) + +#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1) +#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2) +#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6) +#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7) + +#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1) +#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2) +#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3) +#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7) + +#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1) +#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2) +#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3) +#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4) +#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6) +#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7) + +#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1) +#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2) +#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3) +#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4) +#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5) +#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7) + +#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1) +#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2) +#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3) +#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4) +#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5) +#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7) + +#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1) +#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2) +#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3) +#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4) +#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5) +#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7) + +#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1) +#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2) +#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3) +#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4) +#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5) +#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6) +#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7) + +#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1) +#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2) +#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3) +#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4) +#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5) +#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6) +#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7) + +#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1) +#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2) +#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3) +#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4) +#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5) +#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6) +#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7) + +#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1) +#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2) +#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3) +#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4) +#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7) + +#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1) +#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2) +#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3) +#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4) +#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7) + +#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1) +#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2) +#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3) +#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4) +#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7) + +#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1) +#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2) +#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3) +#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4) +#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7) + +#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1) +#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2) +#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3) +#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4) +#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7) + +#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1) +#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2) +#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4) + +#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1) +#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2) +#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4) +#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5) + +#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1) +#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2) +#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4) +#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5) + +#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1) +#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2) +#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4) +#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5) + +#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1) +#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2) +#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3) +#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4) +#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5) + +#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1) +#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2) +#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3) +#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4) +#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5) + +#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1) +#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2) +#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3) +#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4) +#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5) + +#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1) +#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2) +#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3) +#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4) +#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5) + +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6) +#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7) + +#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1) +#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2) + +#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1) +#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2) +#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3) +#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4) + +#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1) +#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2) + +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5) +#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7) + +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5) +#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7) + +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5) +#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7) + +#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1) +#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2) +#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3) +#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5) +#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7) + +#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1) +#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2) +#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3) +#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5) +#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7) + +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5) +#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7) + +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1) +#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2) + +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1) +#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2) + +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1) +#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2) + +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1) +#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2) + +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2) +#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7) + +#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1) + +#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1) +#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2) + +#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1) +#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2) + +#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1) +#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2) + +#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1) +#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2) +#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3) +#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4) +#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5) +#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7) + +#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1) +#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2) +#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4) +#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5) +#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7) + +#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1) +#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2) +#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4) +#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5) +#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7) + +#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1) +#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2) +#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5) +#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7) + +#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1) +#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2) +#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5) +#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7) + +#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1) +#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2) +#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3) + +#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1) +#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2) +#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3) + +#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1) +#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2) +#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3) + +#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1) +#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2) +#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3) + +#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1) +#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2) +#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3) + +#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1) +#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2) +#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3) + +#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5) +#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7) + +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5) +#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7) + +#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5) +#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7) + +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2) +#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5) + +#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1) +#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2) +#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3) +#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6) +#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7) + +#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1) +#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2) +#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3) +#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6) +#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7) + +#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1) +#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2) +#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3) +#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6) +#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7) + +#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1) +#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2) +#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3) +#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6) +#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7) + +#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1) +#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2) +#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5) +#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6) +#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7) + +#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1) +#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2) +#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5) +#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6) +#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7) + +#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7) + +#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3) +#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7) + +#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3) +#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7) + +#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3) +#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7) + +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6) +#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7) + +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6) +#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7) + +#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6) +#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7) + +#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6) +#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7) + +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5) +#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6) + +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5) +#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6) + +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5) +#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7) + +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5) +#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7) + +#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5) +#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7) + +#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4) +#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7) + +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5) +#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7) + +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5) +#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7) + +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6) +#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7) + +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6) +#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7) + +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6) +#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7) + +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6) +#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7) + +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6) +#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7) + +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6) +#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7) + +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6) +#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7) + +#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6) +#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7) + +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6) +#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7) + +#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5) +#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7) + +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6) +#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7) + +#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1) +#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2) +#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3) +#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4) +#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7) + +#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1) +#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2) +#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3) +#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4) +#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7) + +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6) +#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7) + +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6) +#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7) + +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6) +#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7) + +#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1) +#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2) +#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3) +#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4) +#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5) +#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6) +#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7) + +#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1) +#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2) +#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3) +#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4) +#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5) +#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6) +#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7) + +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6) +#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7) + +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6) +#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7) + +#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1) +#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2) +#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3) +#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4) +#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6) +#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7) + +#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1) +#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2) +#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3) +#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4) +#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6) +#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7) + +#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1) +#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2) +#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3) +#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4) +#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6) +#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7) + +#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1) +#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2) +#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3) +#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4) +#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6) +#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7) + +#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1) +#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4) +#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5) +#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6) +#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7) + +#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1) +#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2) +#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5) +#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6) +#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7) + +#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1) +#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2) +#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5) +#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6) +#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7) + +#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1) +#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2) +#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5) +#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7) + +#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1) +#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2) +#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3) +#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5) +#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7) + +#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1) +#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2) +#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3) +#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5) +#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6) +#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7) + +#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1) +#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5) +#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6) +#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7) + +#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1) +#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2) +#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5) +#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7) + +#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1) +#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2) +#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3) +#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4) +#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5) +#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6) + +#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1) +#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2) +#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3) +#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5) +#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6) + +#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1) +#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2) +#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4) +#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5) + +#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1) +#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2) +#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4) +#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5) + +#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1) +#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2) +#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4) + +#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1) +#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2) +#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5) + +#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1) +#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2) +#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3) +#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4) +#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5) + +#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1) +#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2) +#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3) +#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4) +#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5) +#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6) + +#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1) +#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2) +#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4) +#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5) + +#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1) +#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2) +#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3) +#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4) +#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5) + +#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1) +#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2) +#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3) +#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4) +#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5) + +#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1) +#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2) +#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3) +#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4) +#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5) + +#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1) +#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2) +#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3) +#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4) +#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5) + +#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1) +#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2) +#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3) +#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4) +#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5) + +#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1) +#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2) +#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3) +#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4) +#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5) + +#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1) +#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2) +#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3) +#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4) +#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5) + +#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1) +#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2) +#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5) + +#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1) +#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2) +#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5) + +#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1) +#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2) +#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5) + +#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1) +#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2) +#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4) + +#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1) +#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2) +#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4) + +#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1) +#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2) +#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4) + +#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1) +#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2) +#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4) + +#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1) +#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2) +#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4) + +#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1) +#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2) +#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4) + +#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1) +#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2) +#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4) + +#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1) +#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2) +#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4) + +#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1) +#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2) +#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4) + +#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2) + +#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2) + +#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2) + +#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2) + +#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2) + +#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2) + +#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2) + +#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2) + +#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2) + +#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2) + +#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2) + +#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2) + +#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2) + +#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2) + +#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2) + +#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2) + +#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) + +#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) + +#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) + +#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) + +#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1) +#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2) + +#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1) +#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2) + +#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1) +#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2) + +#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1) +#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2) + +#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1) +#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2) + +#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1) +#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2) + +#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1) +#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2) +#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3) + +#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1) +#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2) +#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3) + +#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1) +#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2) + +#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1) +#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2) + +#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1) +#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2) +#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3) + +#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1) +#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2) +#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3) + +#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1) +#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2) +#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3) +#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4) +#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5) +#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6) +#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7) + +#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1) +#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2) +#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5) +#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7) + +#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1) +#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2) +#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5) +#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7) + +#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1) +#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2) +#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5) +#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7) + +#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1) +#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2) +#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3) +#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6) +#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7) + +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6) +#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7) + +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4) +#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6) + +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6) +#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7) + +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4) +#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6) + +#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1) + +#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1) +#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2) +#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3) +#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5) +#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6) + +#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1) +#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2) +#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3) +#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5) +#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6) + +#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1) +#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2) +#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3) +#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4) +#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5) + +#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1) +#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2) +#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3) +#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4) +#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5) + +#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1) +#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2) +#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3) +#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4) +#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5) + +#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1) +#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2) +#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3) +#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4) +#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5) + +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5) +#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6) + +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5) +#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6) + +#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5) +#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6) + +#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4) +#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5) + +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4) +#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5) + +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4) +#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5) + +#endif /* __DTS_MT8135_PINFUNC_H */ diff --git a/dts/src/arm/mt8135.dtsi b/dts/src/arm/mt8135.dtsi index a161e99ffc..0aba9eb28e 100644 --- a/dts/src/arm/mt8135.dtsi +++ b/dts/src/arm/mt8135.dtsi @@ -15,6 +15,7 @@ #include #include #include "skeleton64.dtsi" +#include "mt8135-pinfunc.h" / { compatible = "mediatek,mt8135"; @@ -101,6 +102,29 @@ compatible = "simple-bus"; ranges; + /* + * Pinctrl access register at 0x10005000 and 0x1020c000 through + * regmap. Register 0x1000b000 is used by EINT. + */ + pio: pinctrl@10005000 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + timer: timer@10008000 { compatible = "mediatek,mt8135-timer", "mediatek,mt6577-timer"; @@ -119,6 +143,11 @@ reg = <0 0x10200030 0 0x1c>; }; + syscfg_pctl_b: syscfg_pctl_b@1020c000 { + compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; + reg = <0 0x1020c000 0 0x1000>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; diff --git a/dts/src/arm/omap3-cm-t3517.dts b/dts/src/arm/omap3-cm-t3517.dts index f5b5a1d96c..53ae04f910 100644 --- a/dts/src/arm/omap3-cm-t3517.dts +++ b/dts/src/arm/omap3-cm-t3517.dts @@ -66,7 +66,7 @@ otg_drv_vbus: pinmux_otg_drv_vbus { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ >; }; diff --git a/dts/src/arm/omap3-devkit8000.dts b/dts/src/arm/omap3-devkit8000.dts index 921de6605f..be2297116a 100644 --- a/dts/src/arm/omap3-devkit8000.dts +++ b/dts/src/arm/omap3-devkit8000.dts @@ -157,3 +157,44 @@ }; }; }; + +&gpmc { + ranges = <6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */ + + ethernet@0,0 { + compatible = "davicom,dm9000"; + reg = <6 0x000 2 + 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + bank-width = <2>; + interrupt-parent = <&gpio1>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + davicom,no-eeprom; + + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <0>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <180>; + gpmc,cs-wr-off-ns = <180>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <18>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <144>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <90>; + gpmc,cycle2cycle-delay-ns = <90>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; +}; diff --git a/dts/src/arm/omap3-evm-common.dtsi b/dts/src/arm/omap3-evm-common.dtsi index 346552b94d..b2589f96d5 100644 --- a/dts/src/arm/omap3-evm-common.dtsi +++ b/dts/src/arm/omap3-evm-common.dtsi @@ -96,6 +96,7 @@ }; &mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; vmmc-supply = <&vmmc1>; vmmc_aux-supply = <&vsim>; bus-width = <8>; diff --git a/dts/src/arm/omap3-gta04.dtsi b/dts/src/arm/omap3-gta04.dtsi index b9f68817bd..7166d8876e 100644 --- a/dts/src/arm/omap3-gta04.dtsi +++ b/dts/src/arm/omap3-gta04.dtsi @@ -48,6 +48,28 @@ ti,mcbsp = <&mcbsp2>; }; + /* GSM audio */ + sound_telephony { + compatible = "simple-audio-card"; + simple-audio-card,name = "GTA04 voice"; + simple-audio-card,bitclock-master = <&telephony_link_master>; + simple-audio-card,frame-master = <&telephony_link_master>; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&mcbsp4>; + }; + + telephony_link_master: simple-audio-card,codec { + sound-dai = <>m601_codec>; + }; + }; + + gtm601_codec: gsm_codec { + compatible = "option,gtm601"; + #sound-dai-cells = <0>; + }; + spi_lcd { compatible = "spi-gpio"; #address-cells = <0x1>; @@ -200,6 +222,12 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; + + hdq_pins: hdq_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ + >; + }; }; &omap3_pmx_core2 { @@ -517,3 +545,12 @@ &mcbsp2 { status = "okay"; }; + +&hdqw1w { + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + +&mcbsp4 { + status = "okay"; +}; diff --git a/dts/src/arm/omap3-ldp.dts b/dts/src/arm/omap3-ldp.dts index b699bc48f2..bd6e6769c7 100644 --- a/dts/src/arm/omap3-ldp.dts +++ b/dts/src/arm/omap3-ldp.dts @@ -34,63 +34,63 @@ key_enter { label = "enter"; gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */ - linux,code = <0x0107001c>; /* KEY_ENTER */ + linux,code = ; gpio-key,wakeup; }; key_f1 { label = "f1"; gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */ - linux,code = <0x0303003b>; /* KEY_F1 */ + linux,code = ; gpio-key,wakeup; }; key_f2 { label = "f2"; gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */ - linux,code = <0x0403003c>; /* KEY_F2 */ + linux,code = ; gpio-key,wakeup; }; key_f3 { label = "f3"; gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */ - linux,code = <0x0503003d>; /* KEY_F3 */ + linux,code = ; gpio-key,wakeup; }; key_f4 { label = "f4"; gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */ - linux,code = <0x0704003e>; /* KEY_F4 */ + linux,code = ; gpio-key,wakeup; }; key_left { label = "left"; gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */ - linux,code = <0x04070069>; /* KEY_LEFT */ + linux,code = ; gpio-key,wakeup; }; key_right { label = "right"; gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */ - linux,code = <0x0507006a>; /* KEY_RIGHT */ + linux,code = ; gpio-key,wakeup; }; key_up { label = "up"; gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */ - linux,code = <0x06070067>; /* KEY_UP */ + linux,code = ; gpio-key,wakeup; }; key_down { label = "down"; gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */ - linux,code = <0x0707006c>; /* KEY_DOWN */ + linux,code = ; gpio-key,wakeup; }; }; diff --git a/dts/src/arm/omap5-uevm.dts b/dts/src/arm/omap5-uevm.dts index 74777a6e20..275618f19a 100644 --- a/dts/src/arm/omap5-uevm.dts +++ b/dts/src/arm/omap5-uevm.dts @@ -597,18 +597,20 @@ }; &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; &uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&omap5_pmx_core 0x19c>; }; &uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; }; &cpu0 { diff --git a/dts/src/arm/pxa27x.dtsi b/dts/src/arm/pxa27x.dtsi index 80fc5d7e9e..90b99714ad 100644 --- a/dts/src/arm/pxa27x.dtsi +++ b/dts/src/arm/pxa27x.dtsi @@ -1,6 +1,6 @@ /* The pxa3xx skeleton simply augments the 2xx version */ #include "pxa2xx.dtsi" -#include "dt-bindings/clock/pxa2xx-clock.h" +#include "dt-bindings/clock/pxa-clock.h" / { model = "Marvell PXA27x familiy SoC"; @@ -12,28 +12,61 @@ marvell,intc-nr-irqs = <34>; }; + gpio: gpio@40e00000 { + compatible = "intel,pxa27x-gpio"; + clocks = <&clks CLK_NONE>; + }; + pwm0: pwm@40b00000 { compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; reg = <0x40b00000 0x10>; #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; }; pwm1: pwm@40b00010 { compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; reg = <0x40b00010 0x10>; #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; }; pwm2: pwm@40c00000 { compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; reg = <0x40c00000 0x10>; #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; }; pwm3: pwm@40c00010 { compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; reg = <0x40c00010 0x10>; #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + }; + + pwri2c: i2c@40f000180 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40f00180 0x24>; + interrupts = <6>; + clocks = <&clks CLK_PWRI2C>; + status = "disabled"; + }; + + pxa27x_udc: udc@40600000 { + compatible = "marvell,pxa270-udc"; + reg = <0x40600000 0x10000>; + interrupts = <11>; + clocks = <&clks CLK_USB>; + status = "disabled"; + }; + + keypad: keypad@41500000 { + compatible = "marvell,pxa27x-keypad"; + reg = <0x41500000 0x4c>; + interrupts = <4>; + clocks = <&clks CLK_KEYPAD>; + status = "disabled"; }; }; @@ -46,11 +79,18 @@ #size-cells = <1>; ranges; - pxa2xx_clks: pxa2xx_clks@41300004 { - compatible = "marvell,pxa-clocks"; + clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa270-clocks"; #clock-cells = <1>; status = "okay"; }; }; + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clks CLK_OSTIMER>; + status = "okay"; + }; }; diff --git a/dts/src/arm/pxa2xx.dtsi b/dts/src/arm/pxa2xx.dtsi index c08f84629a..71a0cd7388 100644 --- a/dts/src/arm/pxa2xx.dtsi +++ b/dts/src/arm/pxa2xx.dtsi @@ -6,7 +6,8 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include "dt-bindings/clock/pxa-clock.h" / { model = "Marvell PXA2xx family SoC"; @@ -79,6 +80,7 @@ compatible = "mrvl,pxa-uart"; reg = <0x40100000 0x30>; interrupts = <22>; + clocks = <&clks CLK_FFUART>; status = "disabled"; }; @@ -86,6 +88,7 @@ compatible = "mrvl,pxa-uart"; reg = <0x40200000 0x30>; interrupts = <21>; + clocks = <&clks CLK_BTUART>; status = "disabled"; }; @@ -93,6 +96,7 @@ compatible = "mrvl,pxa-uart"; reg = <0x40700000 0x30>; interrupts = <20>; + clocks = <&clks CLK_STUART>; status = "disabled"; }; @@ -107,6 +111,7 @@ compatible = "mrvl,pxa-i2c"; reg = <0x40301680 0x30>; interrupts = <18>; + clocks = <&clks CLK_I2C>; #address-cells = <0x1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/src/arm/pxa3xx.dtsi b/dts/src/arm/pxa3xx.dtsi index 83bb0eff69..7ad0b17710 100644 --- a/dts/src/arm/pxa3xx.dtsi +++ b/dts/src/arm/pxa3xx.dtsi @@ -1,5 +1,5 @@ /* The pxa3xx skeleton simply augments the 2xx version */ -/include/ "pxa2xx.dtsi" +#include "pxa2xx.dtsi" / { model = "Marvell PXA3xx familiy SoC"; @@ -10,6 +10,7 @@ compatible = "mrvl,pwri2c"; reg = <0x40f500c0 0x30>; interrupts = <6>; + clocks = <&clks CLK_PWRI2C>; #address-cells = <0x1>; #size-cells = <0>; status = "disabled"; @@ -19,6 +20,7 @@ compatible = "marvell,pxa3xx-nand"; reg = <0x43100000 90>; interrupts = <45>; + clocks = <&clks CLK_NAND>; #address-cells = <1>; #size-cells = <1>; status = "disabled"; @@ -32,6 +34,7 @@ gpio: gpio@40e00000 { compatible = "intel,pxa3xx-gpio"; reg = <0x40e00000 0x10000>; + clocks = <&clks CLK_GPIO>; interrupt-names = "gpio0", "gpio1", "gpio_mux"; interrupts = <8 9 10>; gpio-controller; @@ -40,4 +43,28 @@ #interrupt-cells = <0x2>; }; }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clks: pxa3xx_clks@41300004 { + compatible = "marvell,pxa300-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clks CLK_OSTIMER>; + status = "okay"; + }; }; diff --git a/dts/src/arm/qcom-apq8064-cm-qs600.dts b/dts/src/arm/qcom-apq8064-cm-qs600.dts index 5d75666f7f..71512b3ca4 100644 --- a/dts/src/arm/qcom-apq8064-cm-qs600.dts +++ b/dts/src/arm/qcom-apq8064-cm-qs600.dts @@ -14,6 +14,67 @@ }; }; + rpm@108000 { + regulators { + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + }; + }; + gsbi@12440000 { status = "okay"; qcom,mode = ; @@ -40,6 +101,45 @@ }; }; + /* OTG */ + usb1_phy: phy@12500000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + usb3_phy: phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + usb4_phy: phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget1: gadget@12500000 { + status = "ok"; + }; + + /* OTG */ + usb1: usb@12500000 { + status = "ok"; + }; + + usb3: usb@12520000 { + status = "okay"; + }; + + usb4: usb@12530000 { + status = "okay"; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/dts/src/arm/qcom-apq8064-ifc6410.dts b/dts/src/arm/qcom-apq8064-ifc6410.dts index e641001ca2..a7c939ba88 100644 --- a/dts/src/arm/qcom-apq8064-ifc6410.dts +++ b/dts/src/arm/qcom-apq8064-ifc6410.dts @@ -5,15 +5,12 @@ model = "Qualcomm APQ8064/IFC6410"; compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + aliases { + serial0 = &gsbi7_serial; + }; + soc { pinctrl@800000 { - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - card_detect: card_detect { mux { pins = "gpio26"; @@ -23,6 +20,83 @@ }; }; + rpm@108000 { + regulators { + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + }; + }; + + gsbi3: gsbi@16200000 { + status = "okay"; + qcom,mode = ; + i2c3: i2c@16280000 { + status = "okay"; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + }; + }; + gsbi@12440000 { status = "okay"; qcom,mode = ; @@ -49,6 +123,54 @@ }; }; + sata_phy0: phy@1b400000 { + status = "okay"; + }; + + sata0: sata@29000000 { + status = "okay"; + target-supply = <&pm8921_s4>; + }; + + /* OTG */ + usb1_phy: phy@12500000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + usb3_phy: phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + usb4_phy: phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget1: gadget@12500000 { + status = "okay"; + }; + + /* OTG */ + usb1: usb@12500000 { + status = "okay"; + }; + + usb3: usb@12520000 { + status = "okay"; + }; + + usb4: usb@12530000 { + status = "okay"; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi index 6c1511263a..df2061ec63 100644 --- a/dts/src/arm/qcom-apq8064.dtsi +++ b/dts/src/arm/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ #include "skeleton.dtsi" #include +#include #include #include #include @@ -112,6 +113,20 @@ function = "ps_hold"; }; }; + + i2c1_pins: i2c1 { + mux { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + + i2c3_pins: i2c3 { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi3"; + }; + }; }; intc: interrupt-controller@2000000 { @@ -225,6 +240,26 @@ }; }; + gsbi3: gsbi@16200000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c3: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + }; + }; + gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; @@ -235,10 +270,9 @@ #address-cells = <1>; #size-cells = <1>; ranges; - syscon-tcsr = <&tcsr>; - serial@16640000 { + gsbi7_serial: serial@16640000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; @@ -276,6 +310,143 @@ #reset-cells = <1>; }; + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x2011000 0x1000>; + }; + + rpm@108000 { + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + + pm8921_hdmi_switch: hdmi-switch { + bias-pull-down; + }; + }; + }; + + usb1_phy: phy@12500000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12500000 0x400>; + interrupts = ; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS1_XCVR_CLK>, + <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc USB_HS1_RESET>; + reset-names = "link"; + }; + + usb3_phy: phy@12520000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12520000 0x400>; + interrupts = ; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS3_XCVR_CLK>, + <&gcc USB_HS3_H_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc USB_HS3_RESET>; + reset-names = "link"; + }; + + usb4_phy: phy@12530000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12530000 0x400>; + interrupts = ; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS4_XCVR_CLK>, + <&gcc USB_HS4_H_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc USB_HS4_RESET>; + reset-names = "link"; + }; + + gadget1: gadget@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x400>; + status = "disabled"; + dr_mode = "peripheral"; + interrupts = ; + usb-phy = <&usb1_phy>; + }; + + usb1: usb@12500000 { + compatible = "qcom,ehci-host"; + reg = <0x12500000 0x400>; + interrupts = ; + status = "disabled"; + usb-phy = <&usb1_phy>; + }; + + usb3: usb@12520000 { + compatible = "qcom,ehci-host"; + reg = <0x12520000 0x400>; + interrupts = ; + status = "disabled"; + usb-phy = <&usb3_phy>; + }; + + usb4: usb@12530000 { + compatible = "qcom,ehci-host"; + reg = <0x12530000 0x400>; + interrupts = ; + status = "disabled"; + usb-phy = <&usb4_phy>; + }; + + sata_phy0: phy@1b400000 { + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; + }; + + sata0: sata@29000000 { + compatible = "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = ; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; diff --git a/dts/src/arm/qcom-msm8660.dtsi b/dts/src/arm/qcom-msm8660.dtsi index 20bbd19b99..e0b2ce2910 100644 --- a/dts/src/arm/qcom-msm8660.dtsi +++ b/dts/src/arm/qcom-msm8660.dtsi @@ -37,6 +37,11 @@ }; }; + cpu-pmu { + compatible = "qcom,scorpion-mp-pmu"; + interrupts = <1 9 0x304>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; diff --git a/dts/src/arm/qcom-pm8841.dtsi b/dts/src/arm/qcom-pm8841.dtsi index 73813cc118..8f1a0b1620 100644 --- a/dts/src/arm/qcom-pm8841.dtsi +++ b/dts/src/arm/qcom-pm8841.dtsi @@ -1,3 +1,4 @@ +#include #include &spmi_bus { @@ -7,6 +8,23 @@ reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8841_mpps: mpps@a000 { + compatible = "qcom,pm8841-mpp"; + reg = <0xa000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <4 0xa0 0 IRQ_TYPE_NONE>, + <4 0xa1 0 IRQ_TYPE_NONE>, + <4 0xa2 0 IRQ_TYPE_NONE>, + <4 0xa3 0 IRQ_TYPE_NONE>; + }; + + temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; + }; }; usid5: pm8841@5 { diff --git a/dts/src/arm/qcom-pm8941.dtsi b/dts/src/arm/qcom-pm8941.dtsi index 24c5088ace..aa774e6850 100644 --- a/dts/src/arm/qcom-pm8941.dtsi +++ b/dts/src/arm/qcom-pm8941.dtsi @@ -1,3 +1,5 @@ +#include +#include #include &spmi_bus { @@ -7,12 +9,141 @@ reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000 0x100>, + <0x6100 0x100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pm8941_gpios: gpios@c000 { + compatible = "qcom,pm8941-gpio"; + reg = <0xc000 0x2400>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>, + <0 0xcc 0 IRQ_TYPE_NONE>, + <0 0xcd 0 IRQ_TYPE_NONE>, + <0 0xce 0 IRQ_TYPE_NONE>, + <0 0xcf 0 IRQ_TYPE_NONE>, + <0 0xd0 0 IRQ_TYPE_NONE>, + <0 0xd1 0 IRQ_TYPE_NONE>, + <0 0xd2 0 IRQ_TYPE_NONE>, + <0 0xd3 0 IRQ_TYPE_NONE>, + <0 0xd4 0 IRQ_TYPE_NONE>, + <0 0xd5 0 IRQ_TYPE_NONE>, + <0 0xd6 0 IRQ_TYPE_NONE>, + <0 0xd7 0 IRQ_TYPE_NONE>, + <0 0xd8 0 IRQ_TYPE_NONE>, + <0 0xd9 0 IRQ_TYPE_NONE>, + <0 0xda 0 IRQ_TYPE_NONE>, + <0 0xdb 0 IRQ_TYPE_NONE>, + <0 0xdc 0 IRQ_TYPE_NONE>, + <0 0xdd 0 IRQ_TYPE_NONE>, + <0 0xde 0 IRQ_TYPE_NONE>, + <0 0xdf 0 IRQ_TYPE_NONE>, + <0 0xe0 0 IRQ_TYPE_NONE>, + <0 0xe1 0 IRQ_TYPE_NONE>, + <0 0xe2 0 IRQ_TYPE_NONE>, + <0 0xe3 0 IRQ_TYPE_NONE>; + }; + + pm8941_mpps: mpps@a000 { + compatible = "qcom,pm8941-mpp"; + reg = <0xa000 0x800>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>, + <0 0xa4 0 IRQ_TYPE_NONE>, + <0 0xa5 0 IRQ_TYPE_NONE>, + <0 0xa6 0 IRQ_TYPE_NONE>, + <0 0xa7 0 IRQ_TYPE_NONE>; + }; + + pm8941_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8941_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8941_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + die_temp { + reg = ; + }; + ref_625mv { + reg = ; + }; + ref_1250v { + reg = ; + }; + ref_gnd { + reg = ; + }; + ref_vdd { + reg = ; + }; + }; + + pm8941_iadc: iadc@3600 { + compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc"; + reg = <0x3600 0x100>, + <0x12f1 0x1>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + qcom,external-resistor-micro-ohms = <10000>; + }; }; usid1: pm8941@1 { - compatible ="qcom,spmi-pmic"; + compatible = "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + wled@d800 { + compatible = "qcom,pm8941-wled"; + reg = <0xd800 0x100>; + label = "backlight"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; + }; }; }; diff --git a/dts/src/arm/qcom-pma8084.dtsi b/dts/src/arm/qcom-pma8084.dtsi index a5a4fe695a..5e240ccc08 100644 --- a/dts/src/arm/qcom-pma8084.dtsi +++ b/dts/src/arm/qcom-pma8084.dtsi @@ -1,3 +1,5 @@ +#include +#include #include &spmi_bus { @@ -7,6 +9,96 @@ reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000 0x100>, + <0x6100 0x100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pma8084_gpios: gpios@c000 { + compatible = "qcom,pma8084-gpio"; + reg = <0xc000 0x1600>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>, + <0 0xcc 0 IRQ_TYPE_NONE>, + <0 0xcd 0 IRQ_TYPE_NONE>, + <0 0xce 0 IRQ_TYPE_NONE>, + <0 0xcf 0 IRQ_TYPE_NONE>, + <0 0xd0 0 IRQ_TYPE_NONE>, + <0 0xd1 0 IRQ_TYPE_NONE>, + <0 0xd2 0 IRQ_TYPE_NONE>, + <0 0xd3 0 IRQ_TYPE_NONE>, + <0 0xd4 0 IRQ_TYPE_NONE>, + <0 0xd5 0 IRQ_TYPE_NONE>; + }; + + pma8084_mpps: mpps@a000 { + compatible = "qcom,pma8084-mpp"; + reg = <0xa000 0x800>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>, + <0 0xa4 0 IRQ_TYPE_NONE>, + <0 0xa5 0 IRQ_TYPE_NONE>, + <0 0xa6 0 IRQ_TYPE_NONE>, + <0 0xa7 0 IRQ_TYPE_NONE>; + }; + + pma8084_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + io-channels = <&pma8084_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + }; + + pma8084_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + io-channel-ranges; + + die_temp { + reg = ; + }; + ref_625mv { + reg = ; + }; + ref_1250v { + reg = ; + }; + ref_buf_625mv { + reg = ; + }; + ref_gnd { + reg = ; + }; + ref_vdd { + reg = ; + }; + }; }; usid1: pma8084@1 { diff --git a/dts/src/arm/r8a73a4-ape6evm.dts b/dts/src/arm/r8a73a4-ape6evm.dts index 81a38ceee0..a4c425923c 100644 --- a/dts/src/arm/r8a73a4-ape6evm.dts +++ b/dts/src/arm/r8a73a4-ape6evm.dts @@ -147,7 +147,7 @@ &i2c5 { status = "okay"; - vdd_dvfs: max8973@1b { + vdd_dvfs: regulator@1b { compatible = "maxim,max8973"; reg = <0x1b>; diff --git a/dts/src/arm/r8a73a4.dtsi b/dts/src/arm/r8a73a4.dtsi index 0fd889f881..7ee22a41c6 100644 --- a/dts/src/arm/r8a73a4.dtsi +++ b/dts/src/arm/r8a73a4.dtsi @@ -163,6 +163,7 @@ <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>, <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; power-domains = <&pd_c4>; }; @@ -197,6 +198,7 @@ <0 55 IRQ_TYPE_LEVEL_HIGH>, <0 56 IRQ_TYPE_LEVEL_HIGH>, <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; power-domains = <&pd_c4>; }; @@ -724,15 +726,16 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&main_div2_clk>, <&main_div2_clk>, + <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < - R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 - R8A73A4_CLK_IIC3 + R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 + R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 >; clock-output-names = - "iic5", "iic4", "iic3"; + "irqc", "iic5", "iic4", "iic3"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/dts/src/arm/r8a7740-armadillo800eva.dts b/dts/src/arm/r8a7740-armadillo800eva.dts index 9bd0cb439f..2e31d8c01c 100644 --- a/dts/src/arm/r8a7740-armadillo800eva.dts +++ b/dts/src/arm/r8a7740-armadillo800eva.dts @@ -208,7 +208,7 @@ gpios = <&pfc 166 GPIO_ACTIVE_LOW>; }; - wm8978: wm8978@1a { + wm8978: codec@1a { #sound-dai-cells = <0>; compatible = "wlf,wm8978"; reg = <0x1a>; diff --git a/dts/src/arm/r8a7740.dtsi b/dts/src/arm/r8a7740.dtsi index 83c1c3ca1b..d84714468c 100644 --- a/dts/src/arm/r8a7740.dtsi +++ b/dts/src/arm/r8a7740.dtsi @@ -67,7 +67,7 @@ }; /* irqpin0: IRQ0 - IRQ7 */ - irqpin0: irqpin@e6900000 { + irqpin0: interrupt-controller@e6900000 { compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -89,7 +89,7 @@ }; /* irqpin1: IRQ8 - IRQ15 */ - irqpin1: irqpin@e6900004 { + irqpin1: interrupt-controller@e6900004 { compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -111,7 +111,7 @@ }; /* irqpin2: IRQ16 - IRQ23 */ - irqpin2: irqpin@e6900008 { + irqpin2: interrupt-controller@e6900008 { compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -133,7 +133,7 @@ }; /* irqpin3: IRQ24 - IRQ31 */ - irqpin3: irqpin@e690000c { + irqpin3: interrupt-controller@e690000c { compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -275,7 +275,7 @@ status = "disabled"; }; - scifb8: serial@e6c30000 { + scifb: serial@e6c30000 { compatible = "renesas,scifb-r8a7740", "renesas,scifb"; reg = <0xe6c30000 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/r8a7778-bockw-reference.dts b/dts/src/arm/r8a7778-bockw-reference.dts index 04c0c37bb7..dffa6ff303 100644 --- a/dts/src/arm/r8a7778-bockw-reference.dts +++ b/dts/src/arm/r8a7778-bockw-reference.dts @@ -119,7 +119,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl008k"; + compatible = "spansion,s25fl008k", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; m25p,fast-read; diff --git a/dts/src/arm/r8a7778-bockw.dts b/dts/src/arm/r8a7778-bockw.dts index 787fa6f9f4..90543b12d7 100644 --- a/dts/src/arm/r8a7778-bockw.dts +++ b/dts/src/arm/r8a7778-bockw.dts @@ -85,7 +85,7 @@ &i2c0 { status = "okay"; - ak4643: sound-codec@12 { + ak4643: codec@12 { compatible = "asahi-kasei,ak4643"; #sound-dai-cells = <0>; reg = <0x12>; @@ -186,7 +186,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl008k"; + compatible = "spansion,s25fl008k", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; m25p,fast-read; diff --git a/dts/src/arm/r8a7778.dtsi b/dts/src/arm/r8a7778.dtsi index 868f973095..7ce9f5fd58 100644 --- a/dts/src/arm/r8a7778.dtsi +++ b/dts/src/arm/r8a7778.dtsi @@ -68,7 +68,7 @@ }; /* irqpin: IRQ0 - IRQ3 */ - irqpin: irqpin@fe78001c { + irqpin: interrupt-controller@fe78001c { compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; diff --git a/dts/src/arm/r8a7779-marzen.dts b/dts/src/arm/r8a7779-marzen.dts index 540756cdf3..20afea6f06 100644 --- a/dts/src/arm/r8a7779-marzen.dts +++ b/dts/src/arm/r8a7779-marzen.dts @@ -42,10 +42,10 @@ regulator-always-on; }; - lan0@18000000 { + ethernet@18000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x18000000 0x100>; - pinctrl-0 = <&lan0_pins>; + pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; phy-mode = "mii"; @@ -176,7 +176,7 @@ }; }; - lan0_pins: lan0 { + ethernet_pins: ethernet { intc { renesas,groups = "intc_irq1_b"; renesas,function = "intc"; diff --git a/dts/src/arm/r8a7779.dtsi b/dts/src/arm/r8a7779.dtsi index 5c2219b9f3..5c8071e87a 100644 --- a/dts/src/arm/r8a7779.dtsi +++ b/dts/src/arm/r8a7779.dtsi @@ -148,7 +148,7 @@ interrupt-controller; }; - irqpin0: irqpin@fe780010 { + irqpin0: interrupt-controller@fe780010 { compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; #interrupt-cells = <2>; status = "disabled"; diff --git a/dts/src/arm/r8a7790-lager.dts b/dts/src/arm/r8a7790-lager.dts index aaa4f258e2..2eb8a995ae 100644 --- a/dts/src/arm/r8a7790-lager.dts +++ b/dts/src/arm/r8a7790-lager.dts @@ -429,7 +429,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl512s"; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; spi-tx-bus-width = <4>; @@ -525,7 +525,7 @@ clock-frequency = <100000>; - ak4643: sound-codec@12 { + ak4643: codec@12 { compatible = "asahi-kasei,ak4643"; #sound-dai-cells = <0>; reg = <0x12>; diff --git a/dts/src/arm/r8a7790.dtsi b/dts/src/arm/r8a7790.dtsi index 4bb2f4c173..51ab8865ea 100644 --- a/dts/src/arm/r8a7790.dtsi +++ b/dts/src/arm/r8a7790.dtsi @@ -252,6 +252,7 @@ <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7790_CLK_IRQC>; }; dmac0: dma-controller@e6700000 { @@ -370,6 +371,28 @@ dma-channels = <13>; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH + 0 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH + 0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + #dma-cells = <1>; + dma-channels = <2>; + }; + i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -467,6 +490,7 @@ dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; + max-frequency = <97500000>; }; mmcif1: mmc@ee220000 { @@ -478,6 +502,7 @@ dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; + max-frequency = <97500000>; }; pfc: pfc@e6060000 { @@ -531,6 +556,8 @@ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -540,6 +567,8 @@ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -549,6 +578,8 @@ interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -558,6 +589,8 @@ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -567,6 +600,8 @@ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -576,6 +611,8 @@ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -585,6 +622,8 @@ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -594,6 +633,8 @@ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -603,6 +644,8 @@ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -612,6 +655,8 @@ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -650,6 +695,9 @@ renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; status = "disabled"; }; @@ -1158,6 +1206,14 @@ "iic0", "pciec", "iic1", "ssusb", "cmt1", "usbdmac0", "usbdmac1"; }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; @@ -1273,7 +1329,7 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; @@ -1285,7 +1341,7 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; dmas = <&dmac0 0x55>, <&dmac0 0x56>; @@ -1297,7 +1353,7 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; dmas = <&dmac0 0x41>, <&dmac0 0x42>; @@ -1309,7 +1365,7 @@ msiof3: spi@e6c90000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>; + reg = <0 0xe6c90000 0 0x0064>; interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; dmas = <&dmac0 0x45>, <&dmac0 0x46>; @@ -1442,7 +1498,7 @@ status = "disabled"; }; - rcar_sound: rcar_sound@ec500000 { + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required * diff --git a/dts/src/arm/r8a7791-henninger.dts b/dts/src/arm/r8a7791-henninger.dts index e33e4047b0..655d1804e5 100644 --- a/dts/src/arm/r8a7791-henninger.dts +++ b/dts/src/arm/r8a7791-henninger.dts @@ -226,7 +226,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl512s"; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; spi-tx-bus-width = <4>; diff --git a/dts/src/arm/r8a7791-koelsch.dts b/dts/src/arm/r8a7791-koelsch.dts index 824ddab9c3..cffe33ff4d 100644 --- a/dts/src/arm/r8a7791-koelsch.dts +++ b/dts/src/arm/r8a7791-koelsch.dts @@ -474,7 +474,7 @@ flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spansion,s25fl512s"; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <30000000>; spi-tx-bus-width = <4>; @@ -522,7 +522,7 @@ status = "okay"; clock-frequency = <100000>; - ak4643: sound-codec@12 { + ak4643: codec@12 { compatible = "asahi-kasei,ak4643"; #sound-dai-cells = <0>; reg = <0x12>; diff --git a/dts/src/arm/r8a7791.dtsi b/dts/src/arm/r8a7791.dtsi index 4696062f6d..dc1cd3f166 100644 --- a/dts/src/arm/r8a7791.dtsi +++ b/dts/src/arm/r8a7791.dtsi @@ -239,6 +239,7 @@ <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7791_CLK_IRQC>; }; dmac0: dma-controller@e6700000 { @@ -357,6 +358,28 @@ dma-channels = <13>; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH + 0 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH + 0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; + #dma-cells = <1>; + dma-channels = <2>; + }; + /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; @@ -471,6 +494,7 @@ dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; + max-frequency = <97500000>; }; sdhi0: sd@ee100000 { @@ -509,6 +533,8 @@ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -518,6 +544,8 @@ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -527,6 +555,8 @@ interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -536,6 +566,8 @@ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -545,6 +577,8 @@ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -554,6 +588,8 @@ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; clock-names = "sci_ick"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -563,6 +599,8 @@ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -572,6 +610,8 @@ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -581,6 +621,8 @@ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -590,6 +632,8 @@ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -599,6 +643,8 @@ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -608,6 +654,8 @@ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -617,6 +665,8 @@ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -626,6 +676,8 @@ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; clock-names = "sci_ick"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -635,6 +687,8 @@ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; clock-names = "sci_ick"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -644,6 +698,8 @@ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -653,6 +709,8 @@ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -662,6 +720,8 @@ interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -700,6 +760,9 @@ renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; status = "disabled"; }; @@ -1160,6 +1223,14 @@ "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", "usbdmac0", "usbdmac1"; }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; @@ -1288,7 +1359,7 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; @@ -1300,7 +1371,7 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; dmas = <&dmac0 0x55>, <&dmac0 0x56>; @@ -1312,7 +1383,7 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; dmas = <&dmac0 0x41>, <&dmac0 0x42>; @@ -1485,7 +1556,7 @@ status = "disabled"; }; - rcar_sound: rcar_sound@ec500000 { + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required * diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi index 7a3ffa51a8..b738194233 100644 --- a/dts/src/arm/r8a7794.dtsi +++ b/dts/src/arm/r8a7794.dtsi @@ -105,6 +105,7 @@ <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7794_CLK_IRQC>; }; dmac0: dma-controller@e6700000 { @@ -173,6 +174,8 @@ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -182,6 +185,8 @@ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -191,6 +196,8 @@ interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -200,6 +207,8 @@ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -209,6 +218,8 @@ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -218,6 +229,8 @@ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; clock-names = "sci_ick"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -227,6 +240,8 @@ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -236,6 +251,8 @@ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -245,6 +262,8 @@ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -254,6 +273,8 @@ interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,6 +284,8 @@ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -272,6 +295,8 @@ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -281,6 +306,8 @@ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; clock-names = "sci_ick"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -290,6 +317,8 @@ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; clock-names = "sci_ick"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -299,6 +328,8 @@ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; clock-names = "sci_ick"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -308,6 +339,8 @@ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -317,6 +350,8 @@ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; clock-names = "sci_ick"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -326,6 +361,8 @@ interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; clock-names = "sci_ick"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -625,6 +662,14 @@ "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "irqc"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/dts/src/arm/rk3066a-bqcurie2.dts b/dts/src/arm/rk3066a-bqcurie2.dts index baf21ac6ce..b299b26926 100644 --- a/dts/src/arm/rk3066a-bqcurie2.dts +++ b/dts/src/arm/rk3066a-bqcurie2.dts @@ -2,15 +2,43 @@ * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/rk3066a.dtsi b/dts/src/arm/rk3066a.dtsi index 41ffd4951e..d32229b8a9 100644 --- a/dts/src/arm/rk3066a.dtsi +++ b/dts/src/arm/rk3066a.dtsi @@ -2,15 +2,43 @@ * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/dts/src/arm/rk3188-radxarock.dts b/dts/src/arm/rk3188-radxarock.dts index bdf8570198..42faa19edb 100644 --- a/dts/src/arm/rk3188-radxarock.dts +++ b/dts/src/arm/rk3188-radxarock.dts @@ -1,15 +1,43 @@ /* * Copyright (c) 2013 Heiko Stuebner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -152,6 +180,7 @@ compatible = "active-semi,act8846"; reg = <0x5a>; status = "okay"; + system-power-controller; pinctrl-names = "default"; pinctrl-0 = <&act8846_dvs0_ctl>; diff --git a/dts/src/arm/rk3188.dtsi b/dts/src/arm/rk3188.dtsi index 1d4d79c668..0f23aedf93 100644 --- a/dts/src/arm/rk3188.dtsi +++ b/dts/src/arm/rk3188.dtsi @@ -2,15 +2,43 @@ * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/dts/src/arm/rk3288-evb-act8846.dts b/dts/src/arm/rk3288-evb-act8846.dts index 1687e83369..43949a6771 100644 --- a/dts/src/arm/rk3288-evb-act8846.dts +++ b/dts/src/arm/rk3288-evb-act8846.dts @@ -1,13 +1,41 @@ /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/rk3288-evb-rk808.dts b/dts/src/arm/rk3288-evb-rk808.dts index f62ea78754..18eb6cb495 100644 --- a/dts/src/arm/rk3288-evb-rk808.dts +++ b/dts/src/arm/rk3288-evb-rk808.dts @@ -1,13 +1,41 @@ /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/rk3288-evb.dtsi b/dts/src/arm/rk3288-evb.dtsi index 4a457518d8..844a6fb646 100644 --- a/dts/src/arm/rk3288-evb.dtsi +++ b/dts/src/arm/rk3288-evb.dtsi @@ -1,13 +1,41 @@ /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include @@ -112,6 +140,23 @@ regulator-always-on; regulator-boot-on; }; + + /* + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from + * vcc_io directly. Those boards won't be able to power cycle SD cards + * but it shouldn't hurt to toggle this pin there anyway. + */ + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; }; &emmc { @@ -141,6 +186,8 @@ pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; }; &i2c0 { @@ -232,6 +279,10 @@ sdmmc_cmd: sdmmc-cmd { rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; usb { diff --git a/dts/src/arm/rk3288-firefly.dtsi b/dts/src/arm/rk3288-firefly.dtsi index b54dd78580..0b42372e43 100644 --- a/dts/src/arm/rk3288-firefly.dtsi +++ b/dts/src/arm/rk3288-firefly.dtsi @@ -246,6 +246,14 @@ pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; system-power-controller; + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + regulators { vcc_ddr: REG1 { regulator-name = "vcc_ddr"; @@ -457,6 +465,12 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; diff --git a/dts/src/arm/rk3288-popmetal.dts b/dts/src/arm/rk3288-popmetal.dts index d081f0e0da..d582811fbd 100644 --- a/dts/src/arm/rk3288-popmetal.dts +++ b/dts/src/arm/rk3288-popmetal.dts @@ -406,6 +406,12 @@ }; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &vopb { status = "okay"; }; diff --git a/dts/src/arm/rk3288-thermal.dtsi b/dts/src/arm/rk3288-thermal.dtsi index 2695200c0a..3404066521 100644 --- a/dts/src/arm/rk3288-thermal.dtsi +++ b/dts/src/arm/rk3288-thermal.dtsi @@ -3,9 +3,43 @@ * * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi index 165968d51d..22316d0049 100644 --- a/dts/src/arm/rk3288.dtsi +++ b/dts/src/arm/rk3288.dtsi @@ -1,13 +1,41 @@ /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include @@ -44,6 +72,14 @@ spi2 = &spi2; }; + arm-pmu { + compatible = "arm,cortex-a12-pmu"; + interrupts = , + , + , + ; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -434,6 +470,7 @@ interrupts = ; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; + dr_mode = "host"; phys = <&usbphy2>; phy-names = "usb2-phy"; status = "disabled"; @@ -446,6 +483,11 @@ interrupts = ; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/dts/src/arm/rk3xxx.dtsi b/dts/src/arm/rk3xxx.dtsi index c54a9715dc..a2ae9f3246 100644 --- a/dts/src/arm/rk3xxx.dtsi +++ b/dts/src/arm/rk3xxx.dtsi @@ -2,15 +2,43 @@ * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/dts/src/arm/s3c2416-smdk2416.dts b/dts/src/arm/s3c2416-smdk2416.dts index ea92fd6952..f257926c13 100644 --- a/dts/src/arm/s3c2416-smdk2416.dts +++ b/dts/src/arm/s3c2416-smdk2416.dts @@ -31,55 +31,55 @@ #clock-cells = <0>; }; }; +}; - serial@50000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - }; +&rtc { + status = "okay"; +}; - serial@50004000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - }; +&sdhci_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, + <&sd1_bus1>, <&sd1_bus4>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; - serial@50008000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - }; +&sdhci_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, + <&sd0_bus1>, <&sd0_bus4>; + bus-width = <4>; + cd-gpios = <&gpf 1 0>; + cd-inverted; + status = "okay"; +}; - serial@5000C000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - }; +&uart_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>, <&uart0_fctl>; +}; - watchdog@53000000 { - status = "okay"; - }; +&uart_1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>, <&uart1_fctl>; +}; - rtc@57000000 { - status = "okay"; - }; +&uart_2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; +}; - sdhci@4AC00000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, - <&sd0_bus1>, <&sd0_bus4>; - bus-width = <4>; - cd-gpios = <&gpf 1 0>; - cd-inverted; - status = "okay"; - }; +&uart_3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; +}; - sdhci@4A800000 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, - <&sd1_bus1>, <&sd1_bus4>; - bus-width = <4>; - broken-cd; - status = "okay"; - }; +&watchdog { + status = "okay"; }; diff --git a/dts/src/arm/s3c2416.dtsi b/dts/src/arm/s3c2416.dtsi index 30b8f7e474..a5184ff569 100644 --- a/dts/src/arm/s3c2416.dtsi +++ b/dts/src/arm/s3c2416.dtsi @@ -17,7 +17,7 @@ compatible = "samsung,s3c2416"; aliases { - serial3 = &uart3; + serial3 = &uart_3; }; cpus { @@ -48,7 +48,7 @@ clock-names = "timers"; }; - serial@50000000 { + uart_0: serial@50000000 { compatible = "samsung,s3c2440-uart"; clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; @@ -56,7 +56,7 @@ <&clocks SCLK_UART>; }; - serial@50004000 { + uart_1: serial@50004000 { compatible = "samsung,s3c2440-uart"; clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; @@ -64,7 +64,7 @@ <&clocks SCLK_UART>; }; - serial@50008000 { + uart_2: serial@50008000 { compatible = "samsung,s3c2440-uart"; clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; @@ -72,7 +72,7 @@ <&clocks SCLK_UART>; }; - uart3: serial@5000C000 { + uart_3: serial@5000C000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; interrupts = <1 18 24 4>, <1 18 25 4>; @@ -83,7 +83,7 @@ status = "disabled"; }; - sdhci@4AC00000 { + sdhci_1: sdhci@4AC00000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; @@ -94,7 +94,7 @@ status = "disabled"; }; - sdhci@4A800000 { + sdhci_0: sdhci@4A800000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; @@ -105,13 +105,13 @@ status = "disabled"; }; - watchdog@53000000 { + watchdog: watchdog@53000000 { interrupts = <1 9 27 3>; clocks = <&clocks PCLK_WDT>; clock-names = "watchdog"; }; - rtc@57000000 { + rtc: rtc@57000000 { compatible = "samsung,s3c2416-rtc"; clocks = <&clocks PCLK_RTC>; clock-names = "rtc"; diff --git a/dts/src/arm/sama5d3.dtsi b/dts/src/arm/sama5d3.dtsi index 57ab8587f7..9e2444b07b 100644 --- a/dts/src/arm/sama5d3.dtsi +++ b/dts/src/arm/sama5d3.dtsi @@ -1321,7 +1321,7 @@ usb0: gadget@00500000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; + compatible = "atmel,sama5d3-udc"; reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1439,9 +1439,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, - <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1449,8 +1448,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ehci_clk", "uhpck"; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1478,7 +1477,7 @@ #address-cells = <1>; #size-cells = <1>; reg = < - 0x70000000 0x10000000 /* NFC Command Registers */ + 0x70000000 0x08000000 /* NFC Command Registers */ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; diff --git a/dts/src/arm/sama5d3xcm.dtsi b/dts/src/arm/sama5d3xcm.dtsi index 7d6babdab0..2cf9c3611d 100644 --- a/dts/src/arm/sama5d3xcm.dtsi +++ b/dts/src/arm/sama5d3xcm.dtsi @@ -11,7 +11,8 @@ compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; chosen { - bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; }; memory { @@ -67,12 +68,6 @@ rxd3-skew-ps = <400>; }; }; - - pmc: pmc@fffffc00 { - main: mainck { - clock-frequency = <12000000>; - }; - }; }; nand0: nand@60000000 { diff --git a/dts/src/arm/sama5d4.dtsi b/dts/src/arm/sama5d4.dtsi index 6b1bb58f9c..3ee22ee13c 100644 --- a/dts/src/arm/sama5d4.dtsi +++ b/dts/src/arm/sama5d4.dtsi @@ -59,6 +59,10 @@ serial0 = &usart3; serial1 = &usart4; serial2 = &usart2; + serial3 = &usart0; + serial4 = &usart1; + serial5 = &uart0; + serial6 = &uart1; gpio0 = &pioA; gpio1 = &pioB; gpio2 = &pioC; @@ -123,7 +127,7 @@ usb0: gadget@00400000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9rl-udc"; + compatible = "atmel,sama5d3-udc"; reg = <0x00400000 0x100000 0xfc02c000 0x4000>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; @@ -254,9 +258,8 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, - <&uhpck>; - clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -264,8 +267,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>, <&uhpck>; - clock-names = "usb_clk", "ehci_clk", "uhpck"; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -299,7 +302,7 @@ #address-cells = <1>; #size-cells = <1>; reg = < - 0x90000000 0x10000000 /* NFC Command Registers */ + 0x90000000 0x08000000 /* NFC Command Registers */ 0xfc05c000 0x00000070 /* NFC HSMC regs */ 0x00100000 0x00100000 /* NFC SRAM banks */ >; @@ -847,6 +850,24 @@ clock-names = "mci_clk"; }; + uart0: serial@f8004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8004000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(22))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + ssc0: ssc@f8008000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf8008000 0x4000>; @@ -977,6 +998,42 @@ reg = <0xf8028000 0x60>; }; + usart0: serial@f802c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf802c000 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8030000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8030000 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + mmc1: mmc@fc000000 { compatible = "atmel,hsmci"; reg = <0xfc000000 0x600>; @@ -994,6 +1051,24 @@ clock-names = "mci_clk"; }; + uart1: serial@fc004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc004000 0x100>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(24))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + usart2: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; @@ -1066,6 +1141,46 @@ status = "disabled"; }; + spi1: spi@fc018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc018000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(12))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi2: spi@fc01c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc01c000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(14))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&spi2_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + tcb1: timer@fc020000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; @@ -1125,10 +1240,10 @@ compatible = "atmel,at91sam9g46-aes"; reg = <0xfc044000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(41)>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(40)>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(41))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(40))>; dma-names = "tx", "rx"; clocks = <&aes_clk>; clock-names = "aes_clk"; @@ -1139,10 +1254,10 @@ compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc04c000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(42)>, - <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(43)>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(42))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(43))>; dma-names = "tx", "rx"; clocks = <&tdes_clk>; clock-names = "tdes_clk"; @@ -1153,8 +1268,8 @@ compatible = "atmel,at91sam9g46-sha"; reg = <0xfc050000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) - AT91_XDMAC_DT_PERID(44)>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(44))>; dma-names = "tx"; clocks = <&sha_clk>; clock-names = "sha_clk"; @@ -1232,7 +1347,8 @@ #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; - ranges = <0xfc06a000 0xfc06a000 0x4000>; + ranges = <0xfc068000 0xfc068000 0x100 + 0xfc06a000 0xfc06a000 0x4000>; /* WARNING: revisit as pin spec has changed */ atmel,mux-mask = < /* A B C */ @@ -1623,6 +1739,74 @@ }; }; + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; + }; + }; + + spi2 { + pinctrl_spi2: spi2-0 { + atmel,pins = + ; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = ; + }; + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = ; + }; + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = ; + }; + }; + usart2 { pinctrl_usart2: usart2-0 { atmel,pins = diff --git a/dts/src/arm/sh73a0-kzm9g.dts b/dts/src/arm/sh73a0-kzm9g.dts index 022ba505f5..24b4cd24dc 100644 --- a/dts/src/arm/sh73a0-kzm9g.dts +++ b/dts/src/arm/sh73a0-kzm9g.dts @@ -147,6 +147,7 @@ gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; linux,code = ; label = "SW1"; + gpio-key,wakeup; }; }; diff --git a/dts/src/arm/sh73a0.dtsi b/dts/src/arm/sh73a0.dtsi index 45b539ce4d..11e17c5f26 100644 --- a/dts/src/arm/sh73a0.dtsi +++ b/dts/src/arm/sh73a0.dtsi @@ -90,7 +90,7 @@ status = "disabled"; }; - irqpin0: irqpin@e6900000 { + irqpin0: interrupt-controller@e6900000 { compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -112,7 +112,7 @@ control-parent; }; - irqpin1: irqpin@e6900004 { + irqpin1: interrupt-controller@e6900004 { compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -134,7 +134,7 @@ control-parent; }; - irqpin2: irqpin@e6900008 { + irqpin2: interrupt-controller@e6900008 { compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -156,7 +156,7 @@ control-parent; }; - irqpin3: irqpin@e690000c { + irqpin3: interrupt-controller@e690000c { compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; @@ -376,7 +376,7 @@ status = "disabled"; }; - scifb8: serial@e6c30000 { + scifb: serial@e6c30000 { compatible = "renesas,scifb-sh73a0", "renesas,scifb"; reg = <0xe6c30000 0x100>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/socfpga.dtsi b/dts/src/arm/socfpga.dtsi index d9176e6061..80f924deed 100644 --- a/dts/src/arm/socfpga.dtsi +++ b/dts/src/arm/socfpga.dtsi @@ -36,6 +36,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -451,6 +452,14 @@ clk-phase = <0 135>; }; + sdmmc_clk_divided: sdmmc_clk_divided { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&sdmmc_clk>; + clk-gate = <0xa0 8>; + fixed-divider = <4>; + }; + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; @@ -488,6 +497,8 @@ reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -504,6 +515,8 @@ reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -635,7 +648,7 @@ fifo-depth = <0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; }; @@ -655,6 +668,11 @@ status = "disabled"; }; + scu: snoop-control-unit@fffec000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffec000 0x100>; + }; + spi1: spi@fff01000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; diff --git a/dts/src/arm/socfpga_arria10.dtsi b/dts/src/arm/socfpga_arria10.dtsi index 8a05c47fd5..4779b07310 100644 --- a/dts/src/arm/socfpga_arria10.dtsi +++ b/dts/src/arm/socfpga_arria10.dtsi @@ -21,21 +21,10 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-a10-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -98,6 +87,21 @@ #address-cells = <1>; #size-cells = <0>; + cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb_intosc_ls_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s_free_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -107,47 +111,338 @@ #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>; + reg = <0x40>; + + main_mpu_base_clk: main_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x140 0 11>; + }; + + main_noc_base_clk: main_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x144 0 11>; + }; + + main_emaca_clk: main_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x68>; + }; + + main_emacb_clk: main_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x6C>; + }; + + main_emac_ptp_clk: main_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x70>; + }; + + main_gpio_db_clk: main_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x74>; + }; + + main_sdmmc_clk: main_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk" +; + clocks = <&main_pll>; + reg = <0x78>; + }; + + main_s2f_usr0_clk: main_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x7C>; + }; + + main_s2f_usr1_clk: main_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x80>; + }; + + main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x84>; + }; + + main_periph_ref_clk: main_periph_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x9C>; + }; }; periph_pll: periph_pll { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>, <&main_periph_ref_clk>; + reg = <0xC0>; + + peri_mpu_base_clk: peri_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x140 16 11>; + }; + + peri_noc_base_clk: peri_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x144 16 11>; + }; + + peri_emaca_clk: peri_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xE8>; + }; + + peri_emacb_clk: peri_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xEC>; + }; + + peri_emac_ptp_clk: peri_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF0>; + }; + + peri_gpio_db_clk: peri_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF4>; + }; + + peri_sdmmc_clk: peri_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF8>; + }; + + peri_s2f_usr0_clk: peri_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xFC>; + }; + + peri_s2f_usr1_clk: peri_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x100>; + }; + + peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x104>; + }; + }; + + mpu_free_clk: mpu_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x60>; + }; + + noc_free_clk: noc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x64>; + }; + + s2f_user1_free_clk: s2f_user1_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x104>; + }; + + sdmmc_free_clk: sdmmc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + fixed-divider = <4>; + reg = <0xF8>; + }; + + l4_sys_free_clk: l4_sys_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&noc_free_clk>; + fixed-divider = <4>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 0 2>; + clk-gate = <0x48 1>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 8 2>; + clk-gate = <0x48 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 16 2>; + clk-gate = <0x48 3>; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&mpu_free_clk>; + fixed-divider = <4>; + clk-gate = <0x48 0>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&sdmmc_free_clk>; + clk-gate = <0xC8 5>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 11>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 10>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 9>; + }; + + usb_clk: usb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 8>; + }; + + s2f_usr1_clk: s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&peri_s2f_usr1_clk>; + clk-gate = <0xC8 6>; }; }; }; gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; reg = <0xff800000 0x2000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; /* Filled in by bootloader */ mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; gmac1: ethernet@ff802000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; /* Filled in by bootloader */ mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; gmac2: ethernet@ff804000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 0>; reg = <0xff804000 0x2000>; interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; /* Filled in by bootloader */ mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; status = "disabled"; }; @@ -253,6 +548,17 @@ status = "disabled"; }; + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffcfb100 0x80>; + }; + + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 2 4>, <0 0 4>; + }; + L2: l2-cache@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; @@ -268,6 +574,9 @@ reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; + clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; + clock-names = "biu", "ciu"; + status = "disabled"; }; ocram: sram@ffe00000 { @@ -281,9 +590,15 @@ reg = <0xffd05000 0x100>; }; + scu: snoop-control-unit@ffffc000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffffc000 0x100>; + }; + sysmgr: sysmgr@ffd06000 { compatible = "altr,sys-mgr", "syscon"; reg = <0xffd06000 0x300>; + cpu1-start-addr = <0xffd06230>; }; /* Local timer */ @@ -291,30 +606,39 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xffffc600 0x100>; interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; }; timer0: timer0@ffc02700 { compatible = "snps,dw-apb-timer"; interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; reg = <0xffc02700 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer1: timer1@ffc02800 { compatible = "snps,dw-apb-timer"; interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; reg = <0xffc02800 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer2: timer2@ffd00000 { compatible = "snps,dw-apb-timer"; interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; reg = <0xffd00000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; }; timer3: timer3@ffd00100 { compatible = "snps,dw-apb-timer"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; reg = <0xffd01000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; }; uart0: serial0@ffc02000 { @@ -323,6 +647,7 @@ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uart1: serial1@ffc02100 { @@ -331,6 +656,8 @@ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clocks = <&l4_sp_clk>; + status = "disabled"; }; usbphy0: usbphy@0 { @@ -343,6 +670,8 @@ compatible = "snps,dwc2"; reg = <0xffb00000 0xffff>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -361,6 +690,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00200 0x100>; interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; status = "disabled"; }; @@ -368,6 +698,7 @@ compatible = "snps,dw-wdt"; reg = <0xffd00300 0x100>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; status = "disabled"; }; }; diff --git a/dts/src/arm/socfpga_arria10_socdk.dts b/dts/src/arm/socfpga_arria10_socdk.dts deleted file mode 100755 index 3015ce8d30..0000000000 --- a/dts/src/arm/socfpga_arria10_socdk.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2014 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -#include "socfpga_arria10.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200 rootwait"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - serial0@ffc02000 { - status = "okay"; - }; - }; -}; diff --git a/dts/src/arm/socfpga_arria10_socdk.dtsi b/dts/src/arm/socfpga_arria10_socdk.dtsi new file mode 100644 index 0000000000..94a0709b2f --- /dev/null +++ b/dts/src/arm/socfpga_arria10_socdk.dtsi @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include "socfpga_arria10.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200 rootwait"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts b/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts new file mode 100644 index 0000000000..dbbb751ac1 --- /dev/null +++ b/dts/src/arm/socfpga_arria10_socdk_sdmmc.dts @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2014-2015 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&mmc { + status = "okay"; + num-slots = <1>; + broken-cd; + bus-width = <4>; +}; diff --git a/dts/src/arm/socfpga_cyclone5_sockit.dts b/dts/src/arm/socfpga_cyclone5_sockit.dts index 16ea6f5f2a..71468a7eb2 100644 --- a/dts/src/arm/socfpga_cyclone5_sockit.dts +++ b/dts/src/arm/socfpga_cyclone5_sockit.dts @@ -68,3 +68,19 @@ &usb1 { status = "okay"; }; + +&gpio2 { + status = "okay"; +}; + +&i2c1{ + status = "okay"; + + accel1: accel1@53{ + compatible = "adxl34x"; + reg = <0x53>; + + interrupt-parent = < &portc >; + interrupts = <3 2>; + }; +}; diff --git a/dts/src/arm/socfpga_cyclone5_socrates.dts b/dts/src/arm/socfpga_cyclone5_socrates.dts index a1814b4574..019dd2fea2 100644 --- a/dts/src/arm/socfpga_cyclone5_socrates.dts +++ b/dts/src/arm/socfpga_cyclone5_socrates.dts @@ -30,12 +30,23 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + leds: gpio-leds { + }; }; &gmac1 { status = "okay"; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -45,6 +56,26 @@ }; }; +&leds { + compatible = "gpio-leds"; + + led@0 { + label = "led:green:heartbeat"; + gpios = <&porta 28 1>; + linux,default-trigger = "heartbeat"; + }; + + led@1 { + label = "led:green:D7"; + gpios = <&portb 19 1>; + }; + + led@2 { + label = "led:green:D8"; + gpios = <&portb 25 1>; + }; +}; + &mmc { status = "okay"; }; diff --git a/dts/src/arm/ste-dbx5x0.dtsi b/dts/src/arm/ste-dbx5x0.dtsi index 2201cd5da3..853684ad77 100644 --- a/dts/src/arm/ste-dbx5x0.dtsi +++ b/dts/src/arm/ste-dbx5x0.dtsi @@ -22,6 +22,160 @@ interrupt-parent = <&intc>; ranges; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + ptm@801ae000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801ae000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU0>; + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + + ptm@801af000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x801af000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + cpu = <&CPU1>; + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + + funnel@801a6000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x801a6000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output ports */ + port@0 { + reg = <0>; + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm1_out_port>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + clocks = <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + + tpiu@80190000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x80190000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + etb@801a4000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x801a4000 0x1000>; + + clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; + clock-names = "apb_pclk", "atclk"; + port { + etb_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + intc: interrupt-controller@a0411000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -31,6 +185,20 @@ <0xa0410100 0x100>; }; + scu@a04100000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xa0410000 0x100>; + }; + + /* + * The backup RAM is used for retention during sleep + * and various things like spin tables + */ + backupram@80150000 { + compatible = "ste,dbx500-backupram"; + reg = <0x80150000 0x2000>; + }; + L2: l2-cache { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; @@ -91,6 +259,13 @@ clocks = <&smp_twd_clk>; }; + watchdog@a0410620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xa0410620 0x20>; + interrupts = <1 14 0x304>; + clocks = <&smp_twd_clk>; + }; + rtc@80154000 { compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; diff --git a/dts/src/arm/ste-href-stuib.dtsi b/dts/src/arm/ste-href-stuib.dtsi index 7d4f8184c5..78b75256c6 100644 --- a/dts/src/arm/ste-href-stuib.dtsi +++ b/dts/src/arm/ste-href-stuib.dtsi @@ -77,6 +77,34 @@ }; }; + /* Sensors mounted on this board variant */ + i2c@80128000 { + lis331dl@1c { + /* Accelerometer */ + compatible = "st,lis331dl-accel"; + st,drdy-int-pin = <1>; + reg = <0x1c>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_stuib_mode>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; + }; + ak8974@0f { + /* Magnetometer */ + compatible = "asahi-kasei,ak8974"; + reg = <0x0f>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_stuib_mode>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + }; + i2c@80110000 { bu21013_tp@5c { compatible = "rohm,bu21013_tp"; @@ -116,6 +144,28 @@ }; }; }; + accelerometer { + accel_stuib_mode: accel_stuib { + /* Accelerometer interrupt lines 1 & 2 */ + stuib_cfg { + pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_stuib_mode: magneto_stuib { + /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ + stuib_cfg1 { + pins = "GPIO31_V3"; + ste,config = <&gpio_in_pu>; + }; + stuib_cfg2 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; }; }; diff --git a/dts/src/arm/ste-href-tvk1281618.dtsi b/dts/src/arm/ste-href-tvk1281618.dtsi index 062c6aae3a..0e1c96943d 100644 --- a/dts/src/arm/ste-href-tvk1281618.dtsi +++ b/dts/src/arm/ste-href-tvk1281618.dtsi @@ -99,10 +99,13 @@ vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>, + <19 IRQ_TYPE_EDGE_RISING>; }; - lsm303dlm@1e { + lsm303dlh@1e { /* Magnetometer */ - compatible = "st,lsm303dlm-magn"; + compatible = "st,lsm303dlh-magn"; reg = <0x1e>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; diff --git a/dts/src/arm/ste-nomadik-stn8815.dtsi b/dts/src/arm/ste-nomadik-stn8815.dtsi index f182f6538e..9a5f2ba139 100644 --- a/dts/src/arm/ste-nomadik-stn8815.dtsi +++ b/dts/src/arm/ste-nomadik-stn8815.dtsi @@ -722,8 +722,9 @@ reg = <0x1a>; }; lis3lv02dl@1d { - compatible = "st,lis3lv02dl"; - reg = <0x1d>; + /* Accelerometer */ + compatible = "st,lis3lv02dl-accel"; + reg = <0x1d>; }; }; diff --git a/dts/src/arm/ste-snowball.dts b/dts/src/arm/ste-snowball.dts index 1bc84ebdcc..9edadc3771 100644 --- a/dts/src/arm/ste-snowball.dts +++ b/dts/src/arm/ste-snowball.dts @@ -262,15 +262,19 @@ vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_snowball_mode>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>, /* INT1 */ + <4 IRQ_TYPE_EDGE_RISING>; /* INT2 */ }; - lsm303dlm@1e { + lsm303dlh@1e { /* Magnetometer */ - compatible = "st,lsm303dlm-magn"; + compatible = "st,lsm303dlh-magn"; reg = <0x1e>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&magneto_snowball_mode>; + gpios = <&gpio5 5 0x4>; /* DRDY line */ }; l3g4200d@68 { /* Gyroscope */ @@ -279,6 +283,11 @@ reg = <0x68>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gyro_snowball_mode>; + gpios = <&gpio5 6 0x4>; /* DRDY line */ + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* INT1 */ }; lsp001wm@5c { /* Barometer/pressure sensor */ @@ -489,6 +498,16 @@ }; }; }; + gyro { + gyro_snowball_mode: gyro_snowball { + snowball_cfg1 { + pins = + "GPIO166_A22", /* DRDY */ + "GPIO169_D22"; /* INT */ + ste,config = <&gpio_in_pu>; + }; + }; + }; magnetometer { magneto_snowball_mode: magneto_snowball { snowball_cfg1 { diff --git a/dts/src/arm/stih407-b2120.dts b/dts/src/arm/stih407-b2120.dts index af487145cd..6d93475be5 100644 --- a/dts/src/arm/stih407-b2120.dts +++ b/dts/src/arm/stih407-b2120.dts @@ -7,8 +7,8 @@ * published by the Free Software Foundation. */ /dts-v1/; -#include "stihxxx-b2120.dtsi" #include "stih407.dtsi" +#include "stihxxx-b2120.dtsi" / { model = "STiH407 B2120"; compatible = "st,stih407-b2120", "st,stih407"; diff --git a/dts/src/arm/stih407-family.dtsi b/dts/src/arm/stih407-family.dtsi index c06a546819..838b812cbd 100644 --- a/dts/src/arm/stih407-family.dtsi +++ b/dts/src/arm/stih407-family.dtsi @@ -7,7 +7,10 @@ * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" +#include +#include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -56,6 +59,12 @@ cache-level = <2>; }; + arm-pmu { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -63,6 +72,12 @@ ranges; compatible = "simple-bus"; + restart { + compatible = "st,stih407-restart"; + st,syscfg = <&syscfg_sbc_reg>; + status = "okay"; + }; + powerdown: powerdown-controller { compatible = "st,stih407-powerdown"; #reset-cells = <1>; @@ -113,6 +128,15 @@ reg = <0x94b5100 0x1000>; }; + irq-syscfg { + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; @@ -280,7 +304,7 @@ #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; + <&picophyreset STIH407_PICOPHY2_RESET>; reset-names = "global", "port"; }; @@ -336,5 +360,210 @@ resets = <&softreset STIH407_MIPHY2_SOFTRESET>; }; }; + + spi@9840000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9840000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + pinctrl-0 = <&pinctrl_spi0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi@9841000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9841000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9842000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9842000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9843000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9843000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9844000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9844000 0x110>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "ssc"; + + status = "disabled"; + }; + + /* SBC SSC */ + spi@9540000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9540000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9541000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9541000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; + + spi@9542000 { + compatible = "st,comms-ssc4-spi"; + reg = <0x9542000 0x110>; + interrupts = ; + clocks = <&clk_sysin>; + clock-names = "ssc"; + + status = "disabled"; + }; + + mmc0: sdhci@09060000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09060000 0x7ff>, <0x9061008 0x20>; + reg-names = "mmc", "top-mmc-delay"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>; + bus-width = <8>; + non-removable; + }; + + mmc1: sdhci@09080000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + status = "disabled"; + reg = <0x09080000 0x7ff>; + reg-names = "mmc"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + clock-names = "mmc"; + clocks = <&clk_s_c0_flexgen CLK_MMC_1>; + resets = <&softreset STIH407_MMC1_SOFTRESET>; + bus-width = <4>; + }; + + /* Watchdog and Real-Time Clock */ + lpc@8787000 { + compatible = "st,stih407-lpc"; + reg = <0x8787000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + timeout-sec = <120>; + st,syscfg = <&syscfg_core>; + st,lpc-mode = ; + }; + + lpc@8788000 { + compatible = "st,stih407-lpc"; + reg = <0x8788000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_1>; + st,lpc-mode = ; + }; + + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + st_dwc3: dwc3@8f94000 { + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + ranges; + + status = "disabled"; + + dwc3: dwc3@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = ; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy0>, + <&phy_port2 PHY_TYPE_USB3>; + }; + }; }; }; diff --git a/dts/src/arm/stih407-pinctrl.dtsi b/dts/src/arm/stih407-pinctrl.dtsi index 402844cb31..0a754f2752 100644 --- a/dts/src/arm/stih407-pinctrl.dtsi +++ b/dts/src/arm/stih407-pinctrl.dtsi @@ -104,6 +104,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO5"; + st,retime-pin-mask = <0x3f>; }; rc { @@ -519,6 +520,7 @@ #interrupt-cells = <2>; reg = <0x5000 0x100>; st,bank-name = "PIO35"; + st,retime-pin-mask = <0x7f>; }; i2c4 { diff --git a/dts/src/arm/stih407.dtsi b/dts/src/arm/stih407.dtsi index 3efa3b2ebe..2c560fc305 100644 --- a/dts/src/arm/stih407.dtsi +++ b/dts/src/arm/stih407.dtsi @@ -147,5 +147,33 @@ }; }; }; + + /* COMMS PWM Module */ + pwm0: pwm@9810000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + }; + + /* SBC PWM Module */ + pwm1: pwm@9510000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + }; }; }; diff --git a/dts/src/arm/stih410-b2120.dts b/dts/src/arm/stih410-b2120.dts index 2f61a9960d..16f02c5e33 100644 --- a/dts/src/arm/stih410-b2120.dts +++ b/dts/src/arm/stih410-b2120.dts @@ -26,4 +26,14 @@ aliases { ttyAS0 = &sbc_serial0; }; + + soc { + + mmc0: sdhci@09060000 { + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + }; + }; }; diff --git a/dts/src/arm/stih416-b2020e.dts b/dts/src/arm/stih416-b2020e.dts index 961799e1dc..f1ceee192a 100644 --- a/dts/src/arm/stih416-b2020e.dts +++ b/dts/src/arm/stih416-b2020e.dts @@ -51,5 +51,15 @@ sata0: sata@fe380000{ status = "okay"; }; + + /* SAS PWM Module */ + pwm0: pwm@fed10000 { + status = "okay"; + }; + + /* SBC PWM Module */ + pwm1: pwm@fe510000 { + status = "okay"; + }; }; }; diff --git a/dts/src/arm/stih416-pinctrl.dtsi b/dts/src/arm/stih416-pinctrl.dtsi index 9cccf2d6aa..051fc16f37 100644 --- a/dts/src/arm/stih416-pinctrl.dtsi +++ b/dts/src/arm/stih416-pinctrl.dtsi @@ -216,6 +216,29 @@ }; }; }; + + pwm1 { + pinctrl_pwm1_chan0_default: pwm1-0-default { + st,pins { + pwm-out = <&pio3 0 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan1_default: pwm1-1-default { + st,pins { + pwm-out = <&pio4 4 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan2_default: pwm1-2-default { + st,pins { + pwm-out = <&pio4 6 ALT3 OUT>; + }; + }; + pinctrl_pwm1_chan3_default: pwm1-3-default { + st,pins { + pwm-out = <&pio4 7 ALT3 OUT>; + }; + }; + }; }; pin-controller-front { @@ -310,6 +333,14 @@ st,bank-name = "PIO31"; }; + pwm0 { + pinctrl_pwm0_chan0_default: pwm0-0-default { + st,pins { + pwm-out = <&pio9 7 ALT2 OUT>; + }; + }; + }; + serial2-oe { pinctrl_serial2_oe: serial2-1 { st,pins { @@ -540,6 +571,25 @@ }; }; }; + + pwm0 { + pinctrl_pwm0_chan1_default: pwm0-1-default { + st,pins { + pwm-out = <&pio13 2 ALT2 OUT>; + }; + }; + pinctrl_pwm0_chan2_default: pwm0-2-default { + st,pins { + pwm-out = <&pio15 2 ALT4 OUT>; + }; + }; + pinctrl_pwm0_chan3_default: pwm0-3-default { + st,pins { + pwm-out = <&pio17 4 ALT1 OUT>; + }; + }; + }; + }; pin-controller-fvdp-fe { diff --git a/dts/src/arm/stih416.dtsi b/dts/src/arm/stih416.dtsi index eeb7afecbb..9dca173e69 100644 --- a/dts/src/arm/stih416.dtsi +++ b/dts/src/arm/stih416.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -23,6 +24,12 @@ cache-level = <2>; }; + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = ; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -30,6 +37,12 @@ ranges; compatible = "simple-bus"; + restart { + compatible = "st,stih416-restart"; + st,syscfg = <&syscfg_sbc>; + status = "okay"; + }; + powerdown: powerdown-controller { #reset-cells = <1>; compatible = "st,stih416-powerdown"; @@ -86,6 +99,15 @@ reg = <0xfe4b5100 0x8>; }; + irq-syscfg { + compatible = "st,stih416-irq-syscfg"; + st,syscfg = <&syscfg_cpu>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + serial2: serial@fed32000{ compatible = "st,asc"; status = "disabled"; @@ -104,7 +126,7 @@ interrupts = <0 210 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; + clocks = <&clk_sysin>; }; i2c@fed40000 { @@ -445,5 +467,47 @@ <&softreset STIH416_USB3_SOFTRESET>; reset-names = "power", "softreset"; }; + + /* SAS PWM Module */ + pwm0: pwm@fed10000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0xfed10000 0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default + &pinctrl_pwm0_chan1_default + &pinctrl_pwm0_chan2_default + &pinctrl_pwm0_chan3_default>; + + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + }; + + /* SBC PWM Module */ + pwm1: pwm@fe510000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0xfe510000 0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + /* + * Shared with SBC_OBS_NOTRST. Don't + * enable unless you really know what + * you're doing. + * + * &pinctrl_pwm1_chan1_default + */ + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <3>; + }; }; }; diff --git a/dts/src/arm/stih418-b2199.dts b/dts/src/arm/stih418-b2199.dts index 926235c08e..82eee39ccb 100644 --- a/dts/src/arm/stih418-b2199.dts +++ b/dts/src/arm/stih418-b2199.dts @@ -74,5 +74,32 @@ st,i2c-min-scl-pulse-width-us = <0>; st,i2c-min-sda-pulse-width-us = <5>; }; + + mmc1: sdhci@09080000 { + status = "okay"; + }; + + mmc0: sdhci@09060000 { + status = "okay"; + max-frequency = <200000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; }; }; diff --git a/dts/src/arm/stihxxx-b2120.dtsi b/dts/src/arm/stihxxx-b2120.dtsi index c1d859092b..f589fe487f 100644 --- a/dts/src/arm/stihxxx-b2120.dtsi +++ b/dts/src/arm/stihxxx-b2120.dtsi @@ -47,6 +47,14 @@ status = "okay"; }; + mmc0: sdhci@09060000 { + status = "okay"; + }; + + mmc1: sdhci@09080000 { + status = "okay"; + }; + /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { status = "okay"; @@ -66,5 +74,10 @@ st,osc-force-ext; }; }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + }; }; diff --git a/dts/src/arm/stm32f429-disco.dts b/dts/src/arm/stm32f429-disco.dts new file mode 100644 index 0000000000..6b9aa59d97 --- /dev/null +++ b/dts/src/arm/stm32f429-disco.dts @@ -0,0 +1,71 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f429.dtsi" + +/ { + model = "STMicroelectronics STM32F429i-DISCO board"; + compatible = "st,stm32f429i-disco", "st,stm32f429"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/ram rdinit=/linuxrc"; + linux,stdout-path = &usart1; + }; + + memory { + reg = <0x90000000 0x800000>; + }; + + aliases { + serial0 = &usart1; + }; +}; + +&usart1 { + status = "okay"; +}; diff --git a/dts/src/arm/stm32f429.dtsi b/dts/src/arm/stm32f429.dtsi new file mode 100644 index 0000000000..aa73b4f417 --- /dev/null +++ b/dts/src/arm/stm32f429.dtsi @@ -0,0 +1,214 @@ +/* + * Copyright 2015 - Maxime Coquelin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armv7-m.dtsi" + +/ { + clocks { + clk_sysclk: clk-sysclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_hclk: clk-hclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_pclk1: clk-pclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <45000000>; + }; + + clk_pclk2: clk-pclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr1: clk-pmtr1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr2: clk-pmtr2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_systick: clk-systick { + compatible = "fixed-factor-clock"; + clocks = <&clk_hclk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + }; + + soc { + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&clk_pmtr1>; + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&clk_pmtr1>; + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&clk_pmtr1>; + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&clk_pmtr1>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&clk_pmtr1>; + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&clk_pmtr1>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&clk_pclk1>; + status = "disabled"; + }; + + usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&clk_pclk2>; + status = "disabled"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&clk_pclk2>; + status = "disabled"; + }; + }; +}; + +&systick { + clocks = <&clk_systick>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-a1000.dts b/dts/src/arm/sun4i-a10-a1000.dts index b67e5be618..2630d78d9e 100644 --- a/dts/src/arm/sun4i-a10-a1000.dts +++ b/dts/src/arm/sun4i-a10-a1000.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,101 +53,12 @@ model = "Mele A1000"; compatible = "mele,a1000", "allwinner,sun4i-a10"; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; - - mdio@01c0b080 { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - emac_power_pin_a1000: emac_power_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_a1000: led_pins@0 { - allwinner,pins = "PH10", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; + aliases { + serial0 = &uart0; + }; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -181,12 +87,111 @@ enable-active-high; gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; }; +}; + +&ahci { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + emac_power_pin_a1000: emac_power_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb2_vbus: usb2-vbus { - status = "okay"; + led_pins_a1000: led_pins@0 { + allwinner,pins = "PH10", "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-ba10-tvbox.dts b/dts/src/arm/sun4i-a10-ba10-tvbox.dts index 490b77c9bb..93d435670e 100644 --- a/dts/src/arm/sun4i-a10-ba10-tvbox.dts +++ b/dts/src/arm/sun4i-a10-ba10-tvbox.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -55,94 +50,104 @@ model = "BA10 tvbox"; compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; - - mdio@01c0b080 { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - usb2_vbus_pin_a: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; - reg_usb1_vbus: usb1-vbus { - status = "okay"; + interrupt-controller; + #interrupt-cells = <1>; }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + status = "okay"; - reg_usb2_vbus: usb2-vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; + phy1: ethernet-phy@1 { + reg = <1>; }; }; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + usb2_vbus_pin_a: usb2_vbus_pin@0 { + allwinner,pins = "PH12"; + }; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts b/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts index 58214f2495..5878a0b11f 100644 --- a/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts +++ b/dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -49,10 +44,19 @@ #include "sun4i-a10.dtsi" #include "sunxi-common-regulators.dtsi" #include +#include / { model = "Chuwi V7 CW0825"; compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ehci1 { @@ -74,6 +78,32 @@ }; }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@800 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <800000>; + }; + + button@1000 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button@1200 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; diff --git a/dts/src/arm/sun4i-a10-cubieboard.dts b/dts/src/arm/sun4i-a10-cubieboard.dts index 4260c2b476..9afb4e0185 100644 --- a/dts/src/arm/sun4i-a10-cubieboard.dts +++ b/dts/src/arm/sun4i-a10-cubieboard.dts @@ -17,11 +17,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -57,102 +52,12 @@ model = "Cubietech Cubieboard"; compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; - - mdio@01c0b080 { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - led_pins_cubieboard: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; + aliases { + serial0 = &uart0; + }; - spi0: spi@01c05000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -171,26 +76,100 @@ linux,default-trigger = "heartbeat"; }; }; +}; - reg_ahci_5v: ahci-5v { - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; }; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; }; }; -#include "axp209.dtsi" +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; -&cpu0 { - cpu-supply = <®_dcdc2>; +&ohci0 { + status = "okay"; }; +&ohci1 { + status = "okay"; +}; + +&pio { + led_pins_cubieboard: led_pins@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -215,3 +194,30 @@ regulator-max-microvolt = <3000000>; regulator-name = "avcc"; }; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-gemei-g9.dts b/dts/src/arm/sun4i-a10-gemei-g9.dts new file mode 100644 index 0000000000..570754d8df --- /dev/null +++ b/dts/src/arm/sun4i-a10-gemei-g9.dts @@ -0,0 +1,171 @@ +/* + * Copyright 2015 Priit Laes + * + * Priit Laes + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "Gemei G9 Tablet"; + compatible = "gemei,g9", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * TODO: + * 2x cameras via CSI + * bma250 IRQs + * AXP battery management + * NAND + * OTG + * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 + */ + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + /* Accelerometer */ + bma250@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + + /* + * TODO: interrupt pins: + * int1 - PH00 + * int2 - PI10 + */ + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + + status = "okay"; + + button@158 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <158730>; + }; + + button@349 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <349206>; + }; + + button@1142 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1142856>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */ + cd-inverted; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-hackberry.dts b/dts/src/arm/sun4i-a10-hackberry.dts index d3f73ea255..2b17c51991 100644 --- a/dts/src/arm/sun4i-a10-hackberry.dts +++ b/dts/src/arm/sun4i-a10-hackberry.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,100 +53,12 @@ model = "Miniand Hackberry"; compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy0>; - status = "okay"; - }; - - mdio@01c0b080 { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pio: pinctrl@01c20800 { - pinctrl-names = "default"; - pinctrl-0 = <&hackberry_hogs>; - - hackberry_hogs: hogs@0 { - allwinner,pins = "PH19"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; reg_emac_3v3: emac-3v3 { @@ -162,14 +69,97 @@ enable-active-high; gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy0>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; }; +}; - reg_usb2_vbus: usb2-vbus { - pinctrl-0 = <&usb2_vbus_pin_hackberry>; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&hackberry_hogs>; + + hackberry_hogs: hogs@0 { + allwinner,pins = "PH19"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + pinctrl-0 = <&usb2_vbus_pin_hackberry>; + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-hyundai-a7hd.dts b/dts/src/arm/sun4i-a10-hyundai-a7hd.dts index c88382aacc..43f58fbe16 100644 --- a/dts/src/arm/sun4i-a10-hyundai-a7hd.dts +++ b/dts/src/arm/sun4i-a10-hyundai-a7hd.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -53,6 +48,14 @@ / { model = "Hyundai A7HD"; compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ehci1 { diff --git a/dts/src/arm/sun4i-a10-inet97fv2.dts b/dts/src/arm/sun4i-a10-inet97fv2.dts index 482914333b..6c927a824b 100644 --- a/dts/src/arm/sun4i-a10-inet97fv2.dts +++ b/dts/src/arm/sun4i-a10-inet97fv2.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -61,66 +56,68 @@ serial0 = &uart0; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; }; }; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-jesurun-q5.dts b/dts/src/arm/sun4i-a10-jesurun-q5.dts new file mode 100644 index 0000000000..dc2f2aeaff --- /dev/null +++ b/dts/src/arm/sun4i-a10-jesurun-q5.dts @@ -0,0 +1,193 @@ +/* + * Copyright 2015 Gábor Nyers + * + * Gábor Nyers + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Jesurun Q5"; + compatible = "jesurun,q5", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_q5>; + + green { + label = "q5:green:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + }; + + }; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&emac_power_pin_q5>; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mdio { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + emac_power_pin_q5: emac_power_pin@0 { + allwinner,pins = "PH19"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_q5: led_pins@0 { + allwinner,pins = "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-marsboard.dts b/dts/src/arm/sun4i-a10-marsboard.dts index 9ee86a700c..02158bcd64 100644 --- a/dts/src/arm/sun4i-a10-marsboard.dts +++ b/dts/src/arm/sun4i-a10-marsboard.dts @@ -17,11 +17,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -57,6 +52,14 @@ model = "HAOYU Electronics Marsboard A10"; compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -96,6 +99,10 @@ status = "okay"; }; +&emac_sram { + status = "okay"; +}; + &emac { pinctrl-names = "default"; pinctrl-0 = <&emac_pins_a>; @@ -166,7 +173,8 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>; status = "okay"; }; diff --git a/dts/src/arm/sun4i-a10-mini-xplus.dts b/dts/src/arm/sun4i-a10-mini-xplus.dts index eb5fd6904a..ebe2a04ef6 100644 --- a/dts/src/arm/sun4i-a10-mini-xplus.dts +++ b/dts/src/arm/sun4i-a10-mini-xplus.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,79 +53,83 @@ model = "PineRiver Mini X-Plus"; compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - ir0_pins_a: ir0@0 { - /* The ir receiver is not always populated */ - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + aliases { + serial0 = &uart0; }; - reg_usb1_vbus: usb1-vbus { - status = "okay"; + chosen { + stdout-path = "serial0:115200n8"; }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - reg_usb2_vbus: usb2-vbus { - status = "okay"; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; }; }; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&ir0_rx_pins_a { + /* The ir receiver is not always populated */ + allwinner,pull = ; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-mk802.dts b/dts/src/arm/sun4i-a10-mk802.dts index e9a6886f0d..3c7eebe170 100644 --- a/dts/src/arm/sun4i-a10-mk802.dts +++ b/dts/src/arm/sun4i-a10-mk802.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -53,6 +48,14 @@ / { model = "MK802"; compatible = "allwinner,mk802", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ehci0 { diff --git a/dts/src/arm/sun4i-a10-mk802ii.dts b/dts/src/arm/sun4i-a10-mk802ii.dts index 802eda494d..c861fa7e35 100644 --- a/dts/src/arm/sun4i-a10-mk802ii.dts +++ b/dts/src/arm/sun4i-a10-mk802ii.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -53,6 +48,14 @@ / { model = "MK802ii"; compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ehci0 { diff --git a/dts/src/arm/sun4i-a10-olinuxino-lime.dts b/dts/src/arm/sun4i-a10-olinuxino-lime.dts index 75742f8f96..b64aa4eb07 100644 --- a/dts/src/arm/sun4i-a10-olinuxino-lime.dts +++ b/dts/src/arm/sun4i-a10-olinuxino-lime.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -56,136 +51,143 @@ model = "Olimex A10-OLinuXino-LIME"; compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; - cpus { - cpu0: cpu@0 { - /* - * The A10-Lime is known to be unstable - * when running at 1008 MHz - */ - operating-points = < - /* kHz uV */ - 912000 1350000 - 864000 1300000 - 624000 1250000 - >; - cooling-max-level = <2>; - }; + aliases { + serial0 = &uart0; }; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; - - mdio@01c0b080 { - status = "okay"; + chosen { + stdout-path = "serial0:115200n8"; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; + green { + label = "a10-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; +}; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; - ehci0: usb@01c14000 { - status = "okay"; - }; +&cpu0 { + /* + * The A10-Lime is known to be unstable when running at 1008 MHz + */ + operating-points = < + /* kHz uV */ + 912000 1350000 + 864000 1300000 + 624000 1250000 + >; + cooling-max-level = <2>; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - ehci1: usb@01c1c000 { - status = "okay"; - }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&emac_sram { + status = "okay"; +}; - pinctrl@01c20800 { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; +&mdio { + status = "okay"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + phy1: ethernet-phy@1 { + reg = <1>; }; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; - green { - label = "a10-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; +&ohci0 { + status = "okay"; +}; - reg_ahci_5v: ahci-5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; +&ohci1 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&pio { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb2_vbus: usb2-vbus { - status = "okay"; + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10-pcduino.dts b/dts/src/arm/sun4i-a10-pcduino.dts index 9d1e5482cf..4e3e1b9d82 100644 --- a/dts/src/arm/sun4i-a10-pcduino.dts +++ b/dts/src/arm/sun4i-a10-pcduino.dts @@ -17,11 +17,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,90 +53,12 @@ model = "LinkSprite pcDuino"; compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; - - pinctrl@01c20800 { - led_pins_pcduino: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - key_pins_pcduino: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - mdio@01c0b080 { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; + aliases { + serial0 = &uart0; + }; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -185,12 +102,100 @@ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; }; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; + +&emac_sram { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + led_pins_pcduino: led_pins@0 { + allwinner,pins = "PH15", "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb2_vbus: usb2-vbus { - status = "okay"; + key_pins_pcduino: key_pins@0 { + allwinner,pins = "PH17", "PH18", "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun4i-a10.dtsi b/dts/src/arm/sun4i-a10.dtsi index eebb7853e0..61c03d1fe5 100644 --- a/dts/src/arm/sun4i-a10.dtsi +++ b/dts/src/arm/sun4i-a10.dtsi @@ -2,12 +2,43 @@ * Copyright 2012 Stefan Roese * Stefan Roese * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" @@ -30,7 +61,8 @@ ranges; framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; @@ -38,7 +70,8 @@ }; framebuffer@1 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>, <&ahb_gates 46>; @@ -74,11 +107,11 @@ clocks = <&cpu>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < - /* kHz uV */ + /* kHz uV */ 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1250000 + 912000 1350000 + 864000 1300000 + 624000 1250000 >; #cooling-cells = <2>; cooling-min-level = <0>; @@ -398,11 +431,12 @@ usb_clk: clk@01c200cc { #clock-cells = <1>; - #reset-cells = <1>; + #reset-cells = <1>; compatible = "allwinner,sun4i-a10-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + clock-output-names = "usb_ohci0", "usb_ohci1", + "usb_phy"; }; spi3_clk: clk@01c200d4 { @@ -420,6 +454,42 @@ #size-cells = <1>; ranges; + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + dma: dma-controller@01c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; @@ -461,6 +531,7 @@ reg = <0x01c0b000 0x1000>; interrupts = <55>; clocks = <&ahb_gates 17>; + allwinner,sram = <&emac_sram 1>; status = "disabled"; }; @@ -485,6 +556,8 @@ "sample"; interrupts = <32>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -500,6 +573,8 @@ "sample"; interrupts = <33>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -515,6 +590,8 @@ "sample"; interrupts = <34>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc3: mmc@01c12000 { @@ -530,6 +607,8 @@ "sample"; interrupts = <35>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; usbphy: phy@01c13400 { @@ -706,7 +785,8 @@ }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; allwinner,function = "mmc0"; allwinner,drive = ; allwinner,pull = ; @@ -719,43 +799,85 @@ allwinner,pull = ; }; - ir0_pins_a: ir0@0 { - allwinner,pins = "PB3","PB4"; + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; allwinner,function = "ir0"; allwinner,drive = ; allwinner,pull = ; }; - ir1_pins_a: ir1@0 { - allwinner,pins = "PB22","PB23"; + ir0_tx_pins_a: ir0@1 { + allwinner,pins = "PB3"; + allwinner,function = "ir0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_rx_pins_a: ir1@0 { + allwinner,pins = "PB23"; + allwinner,function = "ir1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_tx_pins_a: ir1@1 { + allwinner,pins = "PB22"; allwinner,function = "ir1"; allwinner,drive = ; allwinner,pull = ; }; spi0_pins_a: spi0@0 { - allwinner,pins = "PI10", "PI11", "PI12", "PI13"; + allwinner,pins = "PI11", "PI12", "PI13"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi0_cs0_pins_a: spi0_cs0@0 { + allwinner,pins = "PI10"; allwinner,function = "spi0"; allwinner,drive = ; allwinner,pull = ; }; spi1_pins_a: spi1@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,pins = "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi1_cs0_pins_a: spi1_cs0@0 { + allwinner,pins = "PI16"; allwinner,function = "spi1"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_a: spi2@0 { - allwinner,pins = "PB14", "PB15", "PB16", "PB17"; + allwinner,pins = "PC20", "PC21", "PC22"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_b: spi2@1 { - allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,pins = "PB15", "PB16", "PB17"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_a: spi2_cs0@0 { + allwinner,pins = "PC19"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_b: spi2_cs0@1 { + allwinner,pins = "PB14"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; diff --git a/dts/src/arm/sun5i-a10s-auxtek-t004.dts b/dts/src/arm/sun5i-a10s-auxtek-t004.dts new file mode 100644 index 0000000000..2b3511ea2e --- /dev/null +++ b/dts/src/arm/sun5i-a10s-auxtek-t004.dts @@ -0,0 +1,154 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a10s.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "Auxtek t004 A10s hdmi tv-stick"; + compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_t004>; + + red { + label = "t004-tv-dongle:red:usr"; + gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + default-state = "on"; + }; + }; + + reg_vmmc1: vmmc1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_vcc_en_pin_t004>; + regulator-name = "vmmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vmmc1>; + bus-width = <4>; + non-removable; + cap-sdio-irq; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_t004: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 { + allwinner,pins = "PB18"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_t004: led_pins@0 { + allwinner,pins = "PB2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb1_vbus_pin_a { + allwinner,pins = "PG13"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun5i-a10s-mk802.dts b/dts/src/arm/sun5i-a10s-mk802.dts index b21af87d9e..46ff940782 100644 --- a/dts/src/arm/sun5i-a10s-mk802.dts +++ b/dts/src/arm/sun5i-a10s-mk802.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -54,6 +49,14 @@ model = "MK802-A10s"; compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; diff --git a/dts/src/arm/sun5i-a10s-olinuxino-micro.dts b/dts/src/arm/sun5i-a10s-olinuxino-micro.dts index 2bbc93b935..a7e19e4847 100644 --- a/dts/src/arm/sun5i-a10s-olinuxino-micro.dts +++ b/dts/src/arm/sun5i-a10s-olinuxino-micro.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -65,184 +60,191 @@ serial2 = &uart3; }; - soc@01c00000 { - emac: ethernet@01c0b000 { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; - phy = <&phy1>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - mdio@01c0b080 { - status = "okay"; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; - phy1: ethernet-phy@1 { - reg = <1>; - }; + green { + label = "a10s-olinuxino-micro:green:usr"; + gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; +}; - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - mmc1: mmc@01c10000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - cd-inverted; - status = "okay"; - }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; +}; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; +&emac_sram { + status = "okay"; +}; - ehci0: usb@01c14000 { - status = "okay"; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; - pinctrl@01c20800 { - mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PE3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { - allwinner,pins = "PB10"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; + at24@50 { + compatible = "at,24c16"; + pagesize = <16>; + reg = <0x50>; + read-only; + }; +}; - lradc: lradc@01c22800 { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; - uart2: serial@01c28800 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; - }; + button@191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; - uart3: serial@01c28c00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; - status = "okay"; - }; + button@392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; + }; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; + button@601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - at24@50 { - compatible = "at,24c16"; - pagesize = <16>; - reg = <0x50>; - read-only; - }; - }; + button@795 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; + button@987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; }; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; +&mdio { + status = "okay"; - green { - label = "a10s-olinuxino-micro:green:usr"; - gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; + phy1: ethernet-phy@1 { + reg = <1>; }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; - status = "okay"; +&pio { + mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; + + mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_olinuxino: led_pins@0 { + allwinner,pins = "PE3"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { + allwinner,pins = "PB10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; + gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; + status = "okay"; }; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + diff --git a/dts/src/arm/sun5i-a10s-r7-tv-dongle.dts b/dts/src/arm/sun5i-a10s-r7-tv-dongle.dts index 7deddfc9df..3b057983c7 100644 --- a/dts/src/arm/sun5i-a10s-r7-tv-dongle.dts +++ b/dts/src/arm/sun5i-a10s-r7-tv-dongle.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -56,67 +51,12 @@ model = "R7 A10s hdmi tv-stick"; compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - cd-inverted; - status = "okay"; - }; - - mmc1: mmc@01c10000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - pinctrl@01c20800 { - mmc0_cd_pin_r7: mmc0_cd_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_r7: led_pins@0 { - allwinner,pins = "PB2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_r7: usb1_vbus_pin@0 { - allwinner,pins = "PG13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; + aliases { + serial0 = &uart0; + }; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -130,10 +70,71 @@ default-state = "on"; }; }; +}; + +&ehci0 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_r7>; - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_r7: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_r7: led_pins@0 { + allwinner,pins = "PB2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; + + usb1_vbus_pin_r7: usb1_vbus_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_r7>; + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun5i-a10s.dtsi b/dts/src/arm/sun5i-a10s.dtsi index 2fd8988f31..f11efb722b 100644 --- a/dts/src/arm/sun5i-a10s.dtsi +++ b/dts/src/arm/sun5i-a10s.dtsi @@ -3,16 +3,49 @@ * * Maxime Ripard * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" +#include "sun5i.dtsi" + #include #include @@ -29,7 +62,8 @@ ranges; framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; @@ -45,133 +79,23 @@ }; }; - cpus { - cpu@0 { - compatible = "arm,cortex-a8"; - }; - }; - - memory { - reg = <0x40000000 0x20000000>; - }; - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; - clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", - "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", - "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", - "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", - "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; + clock-output-names = "ahb_usbotg", "ahb_ehci", + "ahb_ohci", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_nand", + "ahb_sdram", "ahb_emac", "ahb_ts", + "ahb_spi0", "ahb_spi1", "ahb_spi2", + "ahb_gps", "ahb_stimer", "ahb_ve", + "ahb_tve", "ahb_lcd", "ahb_csi", + "ahb_hdmi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", + "ahb_mali400"; }; apb0_gates: clk@01c20068 { @@ -179,16 +103,9 @@ compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; - clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", - "apb0_ir", "apb0_keypad"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; + clock-output-names = "apb0_codec", "apb0_iis", + "apb0_pio", "apb0_ir", + "apb0_keypad"; }; apb1_gates: clk@01c2006c { @@ -200,166 +117,15 @@ "apb1_i2c2", "apb1_uart0", "apb1_uart1", "apb1_uart2", "apb1_uart3"; }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; }; soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-a10-emac"; reg = <0x01c0b000 0x1000>; interrupts = <55>; clocks = <&ahb_gates 17>; + allwinner,sram = <&emac_sram 1>; status = "disabled"; }; @@ -371,214 +137,6 @@ #size-cells = <0>; }; - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <33>; - status = "disabled"; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun5i-a10s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; - #gpio-cells = <3>; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PB19", "PB20"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart2_pins_a: uart2@0 { - allwinner,pins = "PC18", "PC19"; - allwinner,function = "uart2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart3_pins_a: uart3@0 { - allwinner,pins = "PG9", "PG10"; - allwinner,function = "uart3"; - allwinner,drive = ; - allwinner,pull = ; - }; - - emac_pins_a: emac0@0 { - allwinner,pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -589,16 +147,6 @@ status = "disabled"; }; - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - uart2: serial@01c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; @@ -608,52 +156,57 @@ clocks = <&apb1_gates 18>; status = "disabled"; }; + }; +}; - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; +&pio { + compatible = "allwinner,sun5i-a10s-pinctrl"; - i2c0: i2c@01c2ac00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - }; + uart0_pins_a: uart0@0 { + allwinner,pins = "PB19", "PB20"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; - i2c1: i2c@01c2b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - }; + uart2_pins_a: uart2@0 { + allwinner,pins = "PC18", "PC19"; + allwinner,function = "uart2"; + allwinner,drive = ; + allwinner,pull = ; + }; - i2c2: i2c@01c2b400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - }; + uart3_pins_a: uart3@0 { + allwinner,pins = "PG9", "PG10"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; - timer@01c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; - }; + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&sram_a { + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; }; }; diff --git a/dts/src/arm/sun5i-a13-hsg-h702.dts b/dts/src/arm/sun5i-a13-hsg-h702.dts index 03aa045556..990f9d61ae 100644 --- a/dts/src/arm/sun5i-a13-hsg-h702.dts +++ b/dts/src/arm/sun5i-a13-hsg-h702.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -60,81 +55,72 @@ serial0 = &uart1; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_ldo3>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - pinctrl@01c20800 { - mmc0_cd_pin_h702: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - uart1: serial@01c28400 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; }; }; -#include "axp209.dtsi" - &cpu0 { cpu-supply = <®_dcdc2>; }; +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_h702: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +#include "axp209.dtsi" + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -165,3 +151,14 @@ regulator-max-microvolt = <3300000>; regulator-name = "vcc-wifi"; }; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/dts/src/arm/sun5i-a13-olinuxino-micro.dts b/dts/src/arm/sun5i-a13-olinuxino-micro.dts index 03deb84268..ad84fe4276 100644 --- a/dts/src/arm/sun5i-a13-olinuxino-micro.dts +++ b/dts/src/arm/sun5i-a13-olinuxino-micro.dts @@ -17,11 +17,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -61,76 +56,8 @@ serial0 = &uart1; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - pinctrl@01c20800 { - mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinom: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - uart1: serial@01c28400 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -144,10 +71,80 @@ default-state = "on"; }; }; +}; + +&ehci0 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; + + led_pins_olinuxinom: led_pins@0 { + allwinner,pins = "PG9"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun5i-a13-olinuxino.dts b/dts/src/arm/sun5i-a13-olinuxino.dts index 6b24876ed4..42324005eb 100644 --- a/dts/src/arm/sun5i-a13-olinuxino.dts +++ b/dts/src/arm/sun5i-a13-olinuxino.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -63,141 +58,143 @@ serial0 = &uart1; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; - ehci0: usb@01c14000 { - status = "okay"; + power { + gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - pinctrl@01c20800 { - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PG9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - lradc: lradc@01c22800 { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - }; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; - uart1: serial@01c28400 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; - }; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; + button@191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; + button@392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; + button@601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; - power { - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; + button@795 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; + + button@987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_olinuxino: led_pins@0 { + allwinner,pins = "PG9"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino>; - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; + usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_olinuxino>; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun5i-a13-utoo-p66.dts b/dts/src/arm/sun5i-a13-utoo-p66.dts new file mode 100644 index 0000000000..514f159a14 --- /dev/null +++ b/dts/src/arm/sun5i-a13-utoo-p66.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include +#include +#include + +/ { + model = "Utoo P66"; + compatible = "utoo,p66", "allwinner,sun5i-a13"; + + i2c_lcd: i2c@0 { + /* The lcd panel i2c interface is hooked up via gpios */ + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_lcd_pins>; + gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */ + <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */ + i2c-gpio,delay-us = <5>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + icn8318: touchscreen@40 { + compatible = "chipone,icn8318"; + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_wake_pin_p66>; + wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_p66>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; + +&pio { + mmc0_cd_pin_p66: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c_lcd_pins: i2c_lcd_pin@0 { + allwinner,pins = "PG10", "PG12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ts_wake_pin_p66: ts_wake_pin@0 { + allwinner,pins = "PB3"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_vbus_pin_a: usb0_vbus_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/dts/src/arm/sun5i-a13.dtsi b/dts/src/arm/sun5i-a13.dtsi index 883cb48736..976d4faa21 100644 --- a/dts/src/arm/sun5i-a13.dtsi +++ b/dts/src/arm/sun5i-a13.dtsi @@ -3,20 +3,51 @@ * * Maxime Ripard * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" -#include +#include "sun5i.dtsi" -#include #include +#include / { interrupt-parent = <&intc>; @@ -35,31 +66,6 @@ }; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&cpu>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = < - /* kHz uV */ - 1008000 1400000 - 912000 1350000 - 864000 1300000 - 624000 1200000 - 576000 1200000 - 432000 1200000 - >; - #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <5>; - }; - }; - thermal-zones { cpu_thermal { /* milliseconds */ @@ -92,126 +98,22 @@ }; }; - memory { - reg = <0x40000000 0x20000000>; - }; - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; - }; - - /* dummy is 200M */ - cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - axi_gates: clk@01c2005c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-axi-gates-clk"; - reg = <0x01c2005c 0x4>; - clocks = <&axi>; - clock-output-names = "axi_dram"; - }; - - ahb: ahb@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; - clock-output-names = "ahb"; - }; - ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; - clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", - "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", - "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", - "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", - "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", - "ahb_de_fe", "ahb_iep", "ahb_mali400"; - }; - - apb0: apb0@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; - clock-output-names = "apb0"; + clock-output-names = "ahb_usbotg", "ahb_ehci", + "ahb_ohci", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_nand", + "ahb_sdram", "ahb_spi0", + "ahb_spi1", "ahb_spi2", + "ahb_stimer", "ahb_ve", "ahb_lcd", + "ahb_csi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", + "ahb_mali400"; }; apb0_gates: clk@01c20068 { @@ -219,15 +121,8 @@ compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; - clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; - }; - - apb1: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1"; + clock-output-names = "apb0_codec", "apb0_pio", + "apb0_ir"; }; apb1_gates: clk@01c2006c { @@ -238,384 +133,39 @@ clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; - - nand_clk: clk@01c20080 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20080 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "nand"; - }; - - ms_clk: clk@01c20084 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20084 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ms"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - ts_clk: clk@01c20098 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c20098 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ts"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "spi2"; - }; - - ir0_clk: clk@01c200b0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200b0 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "ir0"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_phy"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun5i-a13-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mbus"; - }; }; +}; - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ahb_gates 6>; - #dma-cells = <2>; - }; - - spi0: spi@01c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ahb_gates 20>, <&spi0_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@01c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ahb_gates 21>, <&spi1_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <32>; - status = "disabled"; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - interrupts = <34>; - status = "disabled"; - }; - - usbphy: phy@01c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10 0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&usb_clk 8>; - clock-names = "usb_phy"; - resets = <&usb_clk 0>, <&usb_clk 1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@01c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ahb_gates 1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@01c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&usb_clk 6>, <&ahb_gates 2>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ahb_gates 22>, <&spi2_clk>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - intc: interrupt-controller@01c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun5i-a13-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&apb0_gates 5>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #size-cells = <0>; - #gpio-cells = <3>; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PE10", "PE11"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - uart1_pins_b: uart1@1 { - allwinner,pins = "PG3", "PG4"; - allwinner,function = "uart1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB15", "PB16"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB17", "PB18"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>; - clocks = <&osc24M>; - }; - - wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@01c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 17>; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb1_gates 19>; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&apb1_gates 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; +&cpu0 { + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1400000 + 912000 1350000 + 864000 1300000 + 624000 1200000 + 576000 1200000 + 432000 1200000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <5>; +}; - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&apb1_gates 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; +&pio { + compatible = "allwinner,sun5i-a13-pinctrl"; - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&apb1_gates 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; + uart1_pins_a: uart1@0 { + allwinner,pins = "PE10", "PE11"; + allwinner,function = "uart1"; + allwinner,drive = ; + allwinner,pull = ; + }; - timer@01c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ahb_gates 28>; - }; + uart1_pins_b: uart1@1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = ; + allwinner,pull = ; }; }; diff --git a/dts/src/arm/sun5i.dtsi b/dts/src/arm/sun5i.dtsi new file mode 100644 index 0000000000..54b0978304 --- /dev/null +++ b/dts/src/arm/sun5i.dtsi @@ -0,0 +1,609 @@ +/* + * Copyright 2012-2015 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include +#include + +/ { + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&cpu>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll4: clk@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll5: clk@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + + /* dummy is 200M */ + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 1>; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + + apb1: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + + axi_gates: clk@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-output-names = "axi_dram"; + }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <32>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@01c20800 { + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #size-cells = <0>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc2_pins_a: mmc2@0 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + lradc: lradc@01c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + sid: eeprom@01c23800 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c23800 0x10>; + }; + + rtp: rtp@01c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + timer@01c60000 { + compatible = "allwinner,sun5i-a13-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <82>, <83>; + clocks = <&ahb_gates 28>; + }; + }; +}; diff --git a/dts/src/arm/sun6i-a31-app4-evb1.dts b/dts/src/arm/sun6i-a31-app4-evb1.dts index be9f5ee6b5..2f8cfab771 100644 --- a/dts/src/arm/sun6i-a31-app4-evb1.dts +++ b/dts/src/arm/sun6i-a31-app4-evb1.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,39 +53,41 @@ model = "Allwinner A31 APP4 EVB1 Evaluation Board"; compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; + aliases { + serial0 = &uart0; + }; + chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; +}; - soc@01c00000 { - pio: pinctrl@01c20800 { - usb1_vbus_pin_a: usb1_vbus_pin@0 { - allwinner,pins = "PH27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&ehci0 { + status = "okay"; +}; - usbphy: phy@01c19400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; +&pio { + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH27"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; - ehci0: usb@01c1a000 { - status = "okay"; - }; +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_a>; + gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_a>; - gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun6i-a31-colombus.dts b/dts/src/arm/sun6i-a31-colombus.dts index 84630e56ac..0cf9926d1e 100644 --- a/dts/src/arm/sun6i-a31-colombus.dts +++ b/dts/src/arm/sun6i-a31-colombus.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,79 +53,81 @@ model = "WITS A31 Colombus Evaluation Board"; compatible = "wits,colombus", "allwinner,sun6i-a31"; + aliases { + serial0 = &uart0; + }; + chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "fail"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + cd-inverted; + status = "okay"; +}; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c19400 { - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci1: usb@01c1b000 { - status = "okay"; - }; - - pio: pinctrl@01c20800 { - mmc0_pins_a: mmc0@0 { - allwinner,pull = ; - }; - - mmc0_cd_pin_colombus: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb2_vbus_pin_colombus: usb2_vbus_pin@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "fail"; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; +&mmc0_pins_a { + allwinner,pull = ; +}; + +&pio { + mmc0_cd_pin_colombus: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb2_vbus: usb2-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_colombus>; - gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; - status = "okay"; + usb2_vbus_pin_colombus: usb2_vbus_pin@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb2_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_pin_colombus>; + gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-a31-hummingbird.dts b/dts/src/arm/sun6i-a31-hummingbird.dts index 8b61b1b342..d0cfadac06 100644 --- a/dts/src/arm/sun6i-a31-hummingbird.dts +++ b/dts/src/arm/sun6i-a31-hummingbird.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -58,8 +53,17 @@ model = "Merrii A31 Hummingbird"; compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; + aliases { + serial0 = &uart0; + }; + chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; }; @@ -106,10 +110,16 @@ }; }; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <&vcc_3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ cd-inverted; @@ -121,6 +131,16 @@ allwinner,pull = ; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>; + vmmc-supply = <&vcc_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &ohci0 { status = "okay"; }; @@ -132,6 +152,80 @@ allwinner,drive = ; allwinner,pull = ; }; + + wifi_reset_pin_hummingbird: wifi_reset_pin@0 { + allwinner,pins = "PG10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&p2wi { + status = "okay"; + + axp221: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + dcdc1-supply = <&vcc_3v0>; + dcdc5-supply = <&vcc_dram>; + + regulators { + x-powers,dcdc-freq = <3000>; + + vcc_3v0: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; + }; + + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; + }; + + vdd_gpu: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; + }; + + vdd_sys_dll: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys-dll"; + }; + + vcc_dram: dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; + }; + + vcc_wifi: aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_wifi"; + }; + + avcc: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + }; + }; }; ®_usb1_vbus { diff --git a/dts/src/arm/sun6i-a31-i7.dts b/dts/src/arm/sun6i-a31-i7.dts new file mode 100644 index 0000000000..e9185dad67 --- /dev/null +++ b/dts/src/arm/sun6i-a31-i7.dts @@ -0,0 +1,149 @@ +/* + * Copyright 2015 Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Mele I7 Quad top set box"; + compatible = "mele,i7", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_i7>; + + blue { + label = "i7:blue:usr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + cd-inverted; + status = "okay"; +}; + +&pio { + led_pins_i7: led_pins@0 { + allwinner,pins = "PH13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_i7: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_i7: usb1_vbus_pin@0 { + allwinner,pins = "PC27"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_i7>; + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-a31-m9.dts b/dts/src/arm/sun6i-a31-m9.dts index 139a21e6b6..6e0e5687a0 100644 --- a/dts/src/arm/sun6i-a31-m9.dts +++ b/dts/src/arm/sun6i-a31-m9.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -53,100 +48,102 @@ #include / { - model = "Mele M9 / A1000G Quad top set box"; + model = "Mele M9 top set box"; compatible = "mele,m9", "allwinner,sun6i-a31"; + aliases { + serial0 = &uart0; + }; + chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ - cd-inverted; - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_m9>; - usbphy: phy@01c19400 { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; + blue { + label = "m9:blue:usr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; }; + }; +}; - ehci0: usb@01c1a000 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - ehci1: usb@01c1b000 { - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - pio: pinctrl@01c20800 { - led_pins_m9: led_pins@0 { - allwinner,pins = "PH13"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_m9: mmc0_cd_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_m9: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; - gmac: ethernet@01c30000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + cd-inverted; + status = "okay"; +}; - ir@01f02000 { - pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; - status = "okay"; - }; +&pio { + led_pins_m9: led_pins@0 { + allwinner,pins = "PH13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m9>; - - blue { - label = "m9:blue:usr"; - gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; - }; + mmc0_cd_pin_m9: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb1_vbus: usb1-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_m9>; - gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; - status = "okay"; + usb1_vbus_pin_m9: usb1_vbus_pin@0 { + allwinner,pins = "PC27"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_usb1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_m9>; + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-a31-mele-a1000g-quad.dts b/dts/src/arm/sun6i-a31-mele-a1000g-quad.dts new file mode 100644 index 0000000000..4404f37d13 --- /dev/null +++ b/dts/src/arm/sun6i-a31-mele-a1000g-quad.dts @@ -0,0 +1,149 @@ +/* + * Copyright 2014 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Mele A1000G Quad top set box"; + compatible = "mele,a1000g-quad", "allwinner,sun6i-a31"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_m9>; + + blue { + label = "m9:blue:usr"; + gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + cd-inverted; + status = "okay"; +}; + +&pio { + led_pins_m9: led_pins@0 { + allwinner,pins = "PH13"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_m9: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_m9: usb1_vbus_pin@0 { + allwinner,pins = "PC27"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_m9>; + gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi index fa2f403ccf..008047a018 100644 --- a/dts/src/arm/sun6i-a31.dtsi +++ b/dts/src/arm/sun6i-a31.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -50,6 +45,7 @@ #include "skeleton.dtsi" #include +#include #include @@ -66,7 +62,8 @@ ranges; framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll6 0>; status = "disabled"; @@ -96,10 +93,22 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&cpu>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <3>; }; cpu@1 { @@ -121,6 +130,38 @@ }; }; + thermal-zones { + cpu_thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&rtp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + memory { reg = <0x40000000 0x80000000>; }; @@ -196,6 +237,14 @@ reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; clock-output-names = "ahb1"; + + /* + * Clock AHB1 from PLL6, instead of CPU/AXI which + * has rate changes due to cpufreq. Also the DMA + * controller requires AHB1 clocked from PLL6. + */ + assigned-clocks = <&ahb1>; + assigned-clock-parents = <&pll6 0>; }; ahb1_gates: clk@01c20060 { @@ -251,9 +300,10 @@ reg = <0x01c2006c 0x4>; clocks = <&apb2>; clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_i2c3", "apb2_uart0", - "apb2_uart1", "apb2_uart2", "apb2_uart3", - "apb2_uart4", "apb2_uart5"; + "apb2_i2c2", "apb2_i2c3", + "apb2_uart0", "apb2_uart1", + "apb2_uart2", "apb2_uart3", + "apb2_uart4", "apb2_uart5"; }; mmc0_clk: clk@01c20088 { @@ -330,7 +380,7 @@ usb_clk: clk@01c200cc { #clock-cells = <1>; - #reset-cells = <1>; + #reset-cells = <1>; compatible = "allwinner,sun6i-a31-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&osc24M>; @@ -340,10 +390,13 @@ }; /* - * The following two are dummy clocks, placeholders used in the gmac_tx - * clock. The gmac driver will choose one parent depending on the PHY - * interface mode, using clk_set_rate auto-reparenting. - * The actual TX clock rate is not controlled by the gmac_tx clock. + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. */ mii_phy_tx_clk: clk@1 { #clock-cells = <0>; @@ -381,10 +434,6 @@ clocks = <&ahb1_gates 6>; resets = <&ahb1_rst 6>; #dma-cells = <1>; - - /* DMA controller requires AHB1 clocked from PLL6 */ - assigned-clocks = <&ahb1>; - assigned-clock-parents = <&pll6 0>; }; mmc0: mmc@01c0f000 { @@ -402,6 +451,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -419,6 +470,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -436,6 +489,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc3: mmc@01c12000 { @@ -453,6 +508,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; usbphy: phy@01c19400 { @@ -575,12 +632,21 @@ }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; allwinner,function = "mmc0"; allwinner,drive = ; allwinner,pull = ; }; + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + gmac_pins_mii_a: gmac_mii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", @@ -805,7 +871,8 @@ }; timer@01c60000 { - compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; + compatible = "allwinner,sun6i-a31-hstimer", + "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; interrupts = , , @@ -896,7 +963,8 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, + <&pll6 0>; clock-output-names = "ar100"; }; @@ -973,6 +1041,27 @@ allwinner,drive = ; allwinner,pull = ; }; + + p2wi_pins: p2wi { + allwinner,pins = "PL0", "PL1"; + allwinner,function = "s_p2wi"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + p2wi: i2c@01f03400 { + compatible = "allwinner,sun6i-a31-p2wi"; + reg = <0x01f03400 0x400>; + interrupts = ; + clocks = <&apb0_gates 3>; + clock-frequency = <100000>; + resets = <&apb0_rst 3>; + pinctrl-names = "default"; + pinctrl-0 = <&p2wi_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; diff --git a/dts/src/arm/sun6i-a31s-cs908.dts b/dts/src/arm/sun6i-a31s-cs908.dts index bc3734f67c..1e2411a2bc 100644 --- a/dts/src/arm/sun6i-a31s-cs908.dts +++ b/dts/src/arm/sun6i-a31s-cs908.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -53,10 +48,14 @@ / { model = "CSQ CS908 top set box"; compatible = "csq,cs908", "allwinner,sun6i-a31s"; -}; -&usbphy { - status = "okay"; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ehci0 { @@ -67,25 +66,6 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - -&pio { - usb1_vbus_pin_csq908: usb1_vbus_pin@0 { - allwinner,pins = "PC27"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - &gmac { pinctrl-names = "default"; pinctrl-0 = <&gmac_pins_mii_a>; @@ -102,3 +82,17 @@ pinctrl-0 = <&ir_pins_a>; status = "okay"; }; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/dts/src/arm/sun6i-a31s.dtsi b/dts/src/arm/sun6i-a31s.dtsi index eaf5ec8fd4..c17a32771b 100644 --- a/dts/src/arm/sun6i-a31s.dtsi +++ b/dts/src/arm/sun6i-a31s.dtsi @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person diff --git a/dts/src/arm/sun7i-a20-bananapi.dts b/dts/src/arm/sun7i-a20-bananapi.dts index 5dd139e779..9f7b472e67 100644 --- a/dts/src/arm/sun7i-a20-bananapi.dts +++ b/dts/src/arm/sun7i-a20-bananapi.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -65,160 +60,164 @@ serial2 = &uart7; }; - soc@01c00000 { - spi0: spi@01c05000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - cd-inverted; - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bananapi>; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; + green { + label = "bananapi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; }; + }; - ehci0: usb@01c14000 { - status = "okay"; - }; + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_bananapi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; + }; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&ahci { + status = "okay"; +}; - ahci: sata@01c18000 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - ehci1: usb@01c1c000 { - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; - pinctrl@01c20800 { - mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_bananapi: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_bananapi: led_pins@0 { - allwinner,pins = "PH24"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - uart3: serial@01c28c00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_b>; - status = "okay"; - }; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - uart7: serial@01c29c00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; - }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; +&ohci0 { + status = "okay"; +}; - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; +&ohci1 { + status = "okay"; +}; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; +&pio { + mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapi>; - - green { - label = "bananapi:green:usr"; - gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; - }; + gmac_power_pin_bananapi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb1_vbus: usb1-vbus { - status = "okay"; + led_pins_bananapi: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; - }; +®_usb1_vbus { + status = "okay"; +}; - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; - }; +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>, + <&spi0_cs1_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_b>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun7i-a20-bananapro.dts b/dts/src/arm/sun7i-a20-bananapro.dts index fb89fe7ed2..18fcc87f46 100644 --- a/dts/src/arm/sun7i-a20-bananapro.dts +++ b/dts/src/arm/sun7i-a20-bananapro.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -55,6 +50,16 @@ model = "LeMaker Banana Pro"; compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; + aliases { + serial0 = &uart0; + serial1 = &uart4; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -144,7 +149,7 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; + pinctrl-0 = <&ir0_rx_pins_a>; status = "okay"; }; @@ -233,7 +238,9 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>, + <&spi0_cs1_pins_a>; status = "okay"; }; @@ -243,9 +250,9 @@ status = "okay"; }; -&uart2 { +&uart4 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; + pinctrl-0 = <&uart4_pins_b>; status = "okay"; }; diff --git a/dts/src/arm/sun7i-a20-cubieboard2.dts b/dts/src/arm/sun7i-a20-cubieboard2.dts index c4ab6edb6f..39a51d5143 100644 --- a/dts/src/arm/sun7i-a20-cubieboard2.dts +++ b/dts/src/arm/sun7i-a20-cubieboard2.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -59,94 +54,12 @@ model = "Cubietech Cubieboard2"; compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - led_pins_cubieboard2: led_pins@0 { - allwinner,pins = "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; + aliases { + serial0 = &uart0; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -164,26 +77,94 @@ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; }; }; +}; - reg_ahci_5v: ahci-5v { - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; }; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; }; -#include "axp209.dtsi" +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; -&cpu0 { - cpu-supply = <®_dcdc2>; +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; }; +&ohci1 { + status = "okay"; +}; + +&pio { + led_pins_cubieboard2: led_pins@0 { + allwinner,pins = "PH20", "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -208,3 +189,23 @@ regulator-max-microvolt = <3000000>; regulator-name = "avcc"; }; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-cubietruck.dts b/dts/src/arm/sun7i-a20-cubietruck.dts index 8f74a64957..4611e2f5a9 100644 --- a/dts/src/arm/sun7i-a20-cubietruck.dts +++ b/dts/src/arm/sun7i-a20-cubietruck.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -59,142 +54,12 @@ model = "Cubietech Cubietruck"; compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - mmc3: mmc@01c12000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - mmc3_pins_a: mmc3@0 { - /* AP6210 requires pull-up */ - allwinner,pull = ; - }; - - vmmc3_pin_cubietruck: vmmc3_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PH17"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - pwm: pwm@01c20e00 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; - status = "okay"; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; - - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; + aliases { + serial0 = &uart0; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -223,26 +88,6 @@ }; }; - reg_ahci_5v: ahci-5v { - pinctrl-0 = <&ahci_pwr_pin_cubietruck>; - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb0_vbus: usb0-vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; - gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; - - reg_usb2_vbus: usb2-vbus { - status = "okay"; - }; - reg_vmmc3: vmmc3 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -255,12 +100,149 @@ }; }; -#include "axp209.dtsi" +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; &cpu0 { cpu-supply = <®_dcdc2>; }; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc3_pins_a { + /* AP6210 requires pull-up */ + allwinner,pull = ; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vmmc3_pin_cubietruck: vmmc3_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_cubietruck: led_pins@0 { + allwinner,pins = "PH7", "PH11", "PH20", "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_vbus_pin_a: usb0_vbus_pin@0 { + allwinner,pins = "PH17"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; +}; + +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_cubietruck>; + gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +#include "axp209.dtsi" + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -285,3 +267,30 @@ regulator-max-microvolt = <3000000>; regulator-name = "avcc"; }; + +®_usb0_vbus { + pinctrl-0 = <&usb0_vbus_pin_a>; + gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-hummingbird.dts b/dts/src/arm/sun7i-a20-hummingbird.dts index 86a944ce19..37f4a54974 100644 --- a/dts/src/arm/sun7i-a20-hummingbird.dts +++ b/dts/src/arm/sun7i-a20-hummingbird.dts @@ -3,12 +3,43 @@ * * Wills Wang * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -31,197 +62,8 @@ serial4 = &uart5; }; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - mmc3: mmc@01c12000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_mmc3_vdd>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pio: pinctrl@01c20800 { - ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { - allwinner,pins = "PH15"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { - allwinner,pins = "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - pwm: pwm@01c20e00 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - uart2: serial@01c28800 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; - status = "okay"; - }; - - uart3: serial@01c28c00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; - status = "okay"; - }; - - uart4: serial@01c29000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; - }; - - uart5: serial@01c29400 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; - - i2c3: i2c@01c2b800 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; - status = "okay"; - }; - - spi2: spi@01c17000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>; - status = "okay"; - }; - - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - phy-supply = <®_gmac_vdd>; - /* phy reset config */ - snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ - snps,reset-active-low; - /* wait 1s after reset, otherwise fail to read phy id */ - snps,reset-delays-us = <0 10000 1000000>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; - - reg_ahci_5v: ahci-5v { - pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; - }; - - reg_usb1_vbus: usb1-vbus { - pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - status = "okay"; - }; - - reg_usb2_vbus: usb2-vbus { - status = "okay"; + chosen { + stdout-path = "serial0:115200n8"; }; reg_mmc3_vdd: mmc3_vdd { @@ -246,3 +88,195 @@ gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */ }; }; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_vdd>; + /* phy reset config */ + snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ + snps,reset-active-low; + /* wait 1s after reset, otherwise fail to read phy id */ + snps,reset-delays-us = <0 10000 1000000>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_mmc3_vdd>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { + allwinner,pins = "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; + gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>, + <&spi2_cs0_pins_b>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-i12-tvbox.dts b/dts/src/arm/sun7i-a20-i12-tvbox.dts index 06148b4d00..f32f6f20d9 100644 --- a/dts/src/arm/sun7i-a20-i12-tvbox.dts +++ b/dts/src/arm/sun7i-a20-i12-tvbox.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -57,123 +52,12 @@ model = "I12 / Q5 / QT840A A20 tvbox"; compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - mmc3: mmc@01c12000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - mmc3_pins_a: mmc3@0 { - /* AP6210 / AP6330 requires pull-up */ - allwinner,pull = ; - }; - - vmmc3_pin_i12_tvbox: vmmc3_pin@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { - allwinner,pins = "PH12"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - gmac_power_pin_i12_tvbox: gmac_power_pin@0 { - allwinner,pins = "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_i12_tvbox: led_pins@0 { - allwinner,pins = "PH9", "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + aliases { + serial0 = &uart0; + }; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - phy-supply = <®_gmac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -192,14 +76,6 @@ }; }; - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; - - reg_usb2_vbus: usb2-vbus { - status = "okay"; - }; - reg_vmmc3: vmmc3 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -236,3 +112,136 @@ gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; }; }; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc3_pins_a { + /* AP6210 / AP6330 requires pull-up */ + allwinner,pull = ; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vmmc3_pin_i12_tvbox: vmmc3_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + gmac_power_pin_i12_tvbox: gmac_power_pin@0 { + allwinner,pins = "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_i12_tvbox: led_pins@0 { + allwinner,pins = "PH9", "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-m3.dts b/dts/src/arm/sun7i-a20-m3.dts index 5add9f243e..8d9ea48dd9 100644 --- a/dts/src/arm/sun7i-a20-m3.dts +++ b/dts/src/arm/sun7i-a20-m3.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -59,114 +54,120 @@ model = "Mele M3"; compatible = "mele,m3", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; + aliases { + serial0 = &uart0; + }; - mmc2: mmc@01c11000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_m3>; - ehci0: usb@01c14000 { - status = "okay"; + blue { + label = "m3:blue:usr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; }; + }; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - ehci1: usb@01c1c000 { - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; - pinctrl@01c20800 { - led_pins_m3: led_pins@0 { - allwinner,pins = "PH20"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; +&ohci0 { + status = "okay"; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m3>; +&ohci1 { + status = "okay"; +}; - blue { - label = "m3:blue:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - }; +&pio { + led_pins_m3: led_pins@0 { + allwinner,pins = "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; +®_usb1_vbus { + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; - }; +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun7i-a20-mk808c.dts b/dts/src/arm/sun7i-a20-mk808c.dts new file mode 100644 index 0000000000..4f432f8ade --- /dev/null +++ b/dts/src/arm/sun7i-a20-mk808c.dts @@ -0,0 +1,148 @@ +/* + * Copyright 2015 Marcus Cooper + * + * Marcus Cooper + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "mk808c"; + compatible = "allwinner,mk808c", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-olinuxino-lime.dts b/dts/src/arm/sun7i-a20-olinuxino-lime.dts index 12ded69d61..769726dfb0 100644 --- a/dts/src/arm/sun7i-a20-olinuxino-lime.dts +++ b/dts/src/arm/sun7i-a20-olinuxino-lime.dts @@ -19,11 +19,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -60,118 +55,124 @@ model = "Olimex A20-OLinuXino-LIME"; compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; + aliases { + serial0 = &uart0; + }; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - ehci0: usb@01c14000 { - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; - ohci0: usb@01c14400 { - status = "okay"; + green { + label = "a20-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; +}; - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; - ehci1: usb@01c1c000 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - pinctrl@01c20800 { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; +&ohci0 { + status = "okay"; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; +&ohci1 { + status = "okay"; +}; - green { - label = "a20-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; +&pio { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_ahci_5v: ahci-5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; - }; +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; }; diff --git a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts index 260dbd3bf2..8acff78272 100644 --- a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts +++ b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -57,176 +52,182 @@ model = "Olimex A20-OLinuXino-LIME2"; compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; + aliases { + serial0 = &uart0; + }; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - ehci0: usb@01c14000 { - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; - ohci0: usb@01c14400 { - status = "okay"; + green { + label = "a20-olinuxino-lime2:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; + reg_axp_ipsout: axp_ipsout { + compatible = "regulator-fixed"; + regulator-name = "axp-ipsout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; - ehci1: usb@01c1c000 { - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - pinctrl@01c20800 { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - allwinner,pins = "PC3"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; - led_pins_olinuxinolime: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + + acin-supply = <®_axp_ipsout>; + vin2-supply = <®_axp_ipsout>; + vin3-supply = <®_axp_ipsout>; + ldo24in-supply = <®_axp_ipsout>; + ldo3in-supply = <®_axp_ipsout>; + + regulators { + vdd_rtc: ldo1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; }; - }; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; + avcc: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - - acin-supply = <®_axp_ipsout>; - vin2-supply = <®_axp_ipsout>; - vin3-supply = <®_axp_ipsout>; - ldo24in-supply = <®_axp_ipsout>; - ldo3in-supply = <®_axp_ipsout>; - - regulators { - vdd_rtc: ldo1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - avcc: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_csi0: ldo3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - - vcc_csi1: ldo4 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_cpu: dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <2275000>; - regulator-always-on; - }; - - vdd_int: dcdc3 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <3500000>; - regulator-always-on; - }; - }; + vcc_csi0: ldo3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; }; - }; - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; + vcc_csi1: ldo4 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; - phy = <&phy1>; - phy-mode = "rgmii"; - status = "okay"; + vdd_cpu: dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2275000>; + regulator-always-on; + }; - phy1: ethernet-phy@1 { - reg = <1>; + vdd_int: dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; }; }; }; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; - green { - label = "a20-olinuxino-lime2:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; - reg_ahci_5v: ahci-5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; +&ohci0 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; - }; +&ohci1 { + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; +&pio { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_axp_ipsout: axp_ipsout { - compatible = "regulator-fixed"; - regulator-name = "axp-ipsout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-olinuxino-micro.dts b/dts/src/arm/sun7i-a20-olinuxino-micro.dts index 714e15ac54..00f8f25ecc 100644 --- a/dts/src/arm/sun7i-a20-olinuxino-micro.dts +++ b/dts/src/arm/sun7i-a20-olinuxino-micro.dts @@ -3,12 +3,43 @@ * * Maxime Ripard * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -32,216 +63,220 @@ spi1 = &spi2; }; - soc@01c00000 { - spi1: spi@01c06000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "okay"; - }; - - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; + chosen { + stdout-path = "serial0:115200n8"; + }; - mmc3: mmc@01c12000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - cd-inverted; - status = "okay"; - }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxino>; - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; + green { + label = "a20-olinuxino-micro:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; + }; +}; - ehci0: usb@01c14000 { - status = "okay"; - }; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; - ohci0: usb@01c14400 { - status = "okay"; - }; +&ehci0 { + status = "okay"; +}; - spi2: spi@01c17000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; +&ehci1 { + status = "okay"; +}; - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; - ehci1: usb@01c1c000 { - status = "okay"; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; - ohci1: usb@01c1c400 { - status = "okay"; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - pinctrl@01c20800 { - mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { - allwinner,pins = "PH11"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - led_pins_olinuxino: led_pins@0 { - allwinner,pins = "PH2"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - lradc: lradc@01c22800 { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@191 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <191274>; - }; - - button@392 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <392644>; - }; - - button@601 { - label = "Menu"; - linux,code = ; - channel = <0>; - voltage = <601151>; - }; - - button@795 { - label = "Search"; - linux,code = ; - channel = <0>; - voltage = <795090>; - }; - - button@987 { - label = "Home"; - linux,code = ; - channel = <0>; - voltage = <987387>; - }; - - button@1184 { - label = "Esc"; - linux,code = ; - channel = <0>; - voltage = <1184678>; - }; - - button@1398 { - label = "Enter"; - linux,code = ; - channel = <0>; - voltage = <1398804>; - }; - }; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; - uart6: serial@01c29800 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pins_a>; - status = "okay"; - }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; - uart7: serial@01c29c00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; - }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; + button@191 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191274>; + }; - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + button@392 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <392644>; + }; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; + button@601 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <601151>; + }; - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; + button@795 { + label = "Search"; + linux,code = ; + channel = <0>; + voltage = <795090>; + }; - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; + button@987 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <987387>; + }; - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; + button@1184 { + label = "Esc"; + linux,code = ; + channel = <0>; + voltage = <1184678>; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + button@1398 { + label = "Enter"; + linux,code = ; + channel = <0>; + voltage = <1398804>; }; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; - green { - label = "a20-olinuxino-micro:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + cd-inverted; + status = "okay"; +}; - reg_ahci_5v: ahci-5v { - status = "okay"; - }; +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&pio { + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_usb2_vbus: usb2-vbus { - status = "okay"; + led_pins_olinuxino: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_ahci_5v { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, + <&spi1_cs0_pins_a>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>, + <&spi2_cs0_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins_a>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-orangepi-mini.dts b/dts/src/arm/sun7i-a20-orangepi-mini.dts new file mode 100644 index 0000000000..73cd81ee02 --- /dev/null +++ b/dts/src/arm/sun7i-a20-orangepi-mini.dts @@ -0,0 +1,250 @@ +/* + * Copyright 2015 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Orange Pi Mini"; + compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_orangepi>; + + green { + label = "orangepi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + }; + + blue { + label = "orangepi:blue:usr"; + gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_orangepi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc3_cd_pin_orangepi: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + gmac_power_pin_orangepi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_orangepi: led_pins@0 { + allwinner,pins = "PH24", "PH25"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { + allwinner,pins = "PH26"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_bananapro>; + gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ + status = "okay"; +}; + +®_usb2_vbus { + pinctrl-0 = <&usb2_vbus_pin_bananapro>; + gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-orangepi.dts b/dts/src/arm/sun7i-a20-orangepi.dts new file mode 100644 index 0000000000..55a06ceb80 --- /dev/null +++ b/dts/src/arm/sun7i-a20-orangepi.dts @@ -0,0 +1,228 @@ +/* + * Copyright 2015 Hans de Goede + * + * Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Orange Pi"; + compatible = "xunlong,orangepi", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_orangepi>; + + green { + label = "orangepi:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_orangepi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp209.dtsi" + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + gmac_power_pin_orangepi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_orangepi: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { + allwinner,pins = "PH26"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_bananapro>; + gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ + status = "okay"; +}; + +®_usb2_vbus { + pinctrl-0 = <&usb2_vbus_pin_bananapro>; + gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-pcduino3-nano.dts b/dts/src/arm/sun7i-a20-pcduino3-nano.dts new file mode 100644 index 0000000000..5361fce26b --- /dev/null +++ b/dts/src/arm/sun7i-a20-pcduino3-nano.dts @@ -0,0 +1,194 @@ +/* + * Copyright 2015 Adam Sampson + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LinkSprite pcDuino3 Nano"; + compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_pcduino3_nano>; + + /* Marked "LED3" on the PCB. */ + usr1 { + label = "pcduino3-nano:green:usr1"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ + }; + + /* Marked "LED4" on the PCB. */ + usr2 { + label = "pcduino3-nano:green:usr2"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + led_pins_pcduino3_nano: led_pins@0 { + allwinner,pins = "PH16", "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +®_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>; + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + status = "okay"; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>; + gpio = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-pcduino3.dts b/dts/src/arm/sun7i-a20-pcduino3.dts index 0a2c2aeb46..afc9ecebed 100644 --- a/dts/src/arm/sun7i-a20-pcduino3.dts +++ b/dts/src/arm/sun7i-a20-pcduino3.dts @@ -17,11 +17,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -59,103 +54,12 @@ model = "LinkSprite pcDuino3"; compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - cd-inverted; - status = "okay"; - }; - - usbphy: phy@01c13400 { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; - }; - - ehci0: usb@01c14000 { - status = "okay"; - }; - - ohci0: usb@01c14400 { - status = "okay"; - }; - - ahci: sata@01c18000 { - target-supply = <®_ahci_5v>; - status = "okay"; - }; - - ehci1: usb@01c1c000 { - status = "okay"; - }; - - ohci1: usb@01c1c400 { - status = "okay"; - }; - - pinctrl@01c20800 { - ahci_pwr_pin_a: ahci_pwr_pin@0 { - allwinner,pins = "PH2"; - }; - - led_pins_pcduino3: led_pins@0 { - allwinner,pins = "PH15", "PH16"; - allwinner,function = "gpio_out"; - allwinner,drive = ; - allwinner,pull = ; - }; - - key_pins_pcduino3: key_pins@0 { - allwinner,pins = "PH17", "PH18", "PH19"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ir0: ir@01c21800 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_pins_a>; - status = "okay"; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - gmac: ethernet@01c50000 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; - phy = <&phy1>; - phy-mode = "mii"; - status = "okay"; + aliases { + serial0 = &uart0; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; + chosen { + stdout-path = "serial0:115200n8"; }; leds { @@ -196,17 +100,114 @@ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; }; }; +}; - reg_usb1_vbus: usb1-vbus { - status = "okay"; +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&ahci_pwr_pin_a { + allwinner,pins = "PH2"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; - reg_usb2_vbus: usb2-vbus { - status = "okay"; +&pio { + led_pins_pcduino3: led_pins@0 { + allwinner,pins = "PH15", "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; }; - reg_ahci_5v: ahci-5v { - gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; - status = "okay"; + key_pins_pcduino3: key_pins@0 { + allwinner,pins = "PH17", "PH18", "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +®_ahci_5v { + gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20-wexler-tab7200.dts b/dts/src/arm/sun7i-a20-wexler-tab7200.dts new file mode 100644 index 0000000000..83c6d3f872 --- /dev/null +++ b/dts/src/arm/sun7i-a20-wexler-tab7200.dts @@ -0,0 +1,183 @@ +/* + * Copyright 2015 Aleksei Mamlin + * Aleksei Mamlin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Wexler TAB7200"; + compatible = "wexler,tab7200", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@571 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <571428>; + }; + + button@761 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <761904>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi index fdd181792b..6a63f30c9a 100644 --- a/dts/src/arm/sun7i-a20.dtsi +++ b/dts/src/arm/sun7i-a20.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -68,7 +63,8 @@ ranges; framebuffer@0 { - compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; @@ -104,14 +100,14 @@ clocks = <&cpu>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < - /* kHz uV */ - 960000 1400000 - 912000 1400000 - 864000 1300000 - 720000 1200000 - 528000 1100000 - 312000 1000000 - 144000 900000 + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 900000 >; #cooling-cells = <2>; cooling-min-level = <0>; @@ -224,7 +220,8 @@ compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; - clock-output-names = "pll6_sata", "pll6_other", "pll6"; + clock-output-names = "pll6_sata", "pll6_other", "pll6", + "pll6_div_4"; }; pll8: clk@01c20040 { @@ -253,10 +250,16 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-ahb-clk"; + compatible = "allwinner,sun5i-a13-ahb-clk"; reg = <0x01c20054 0x4>; - clocks = <&axi>; + clocks = <&axi>, <&pll6 3>, <&pll6 1>; clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 3>; }; ahb_gates: clk@01c20060 { @@ -441,11 +444,12 @@ usb_clk: clk@01c200cc { #clock-cells = <1>; - #reset-cells = <1>; + #reset-cells = <1>; compatible = "allwinner,sun4i-a10-usb-clk"; reg = <0x01c200cc 0x4>; clocks = <&pll6 1>; - clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + clock-output-names = "usb_ohci0", "usb_ohci1", + "usb_phy"; }; spi3_clk: clk@01c200d4 { @@ -465,10 +469,13 @@ }; /* - * The following two are dummy clocks, placeholders used in the gmac_tx - * clock. The gmac driver will choose one parent depending on the PHY - * interface mode, using clk_set_rate auto-reparenting. - * The actual TX clock rate is not controlled by the gmac_tx clock. + * The following two are dummy clocks, placeholders + * used in the gmac_tx clock. The gmac driver will + * choose one parent depending on the PHY interface + * mode, using clk_set_rate auto-reparenting. + * + * The actual TX clock rate is not controlled by the + * gmac_tx clock. */ mii_phy_tx_clk: clk@2 { #clock-cells = <0>; @@ -527,6 +534,42 @@ #size-cells = <1>; ranges; + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + nmi_intc: interrupt-controller@01c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -576,6 +619,7 @@ reg = <0x01c0b000 0x1000>; interrupts = ; clocks = <&ahb_gates 17>; + allwinner,sram = <&emac_sram 1>; status = "disabled"; }; @@ -600,6 +644,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -615,6 +661,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -630,6 +678,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc3: mmc@01c12000 { @@ -645,6 +695,8 @@ "sample"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; usbphy: phy@01c13400 { @@ -795,6 +847,13 @@ allwinner,pull = ; }; + uart4_pins_b: uart4@1 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "uart4"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart5_pins_a: uart5@0 { allwinner,pins = "PI10", "PI11"; allwinner,function = "uart5"; @@ -896,35 +955,71 @@ }; spi0_pins_a: spi0@0 { - allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; + allwinner,pins = "PI11", "PI12", "PI13"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi0_cs0_pins_a: spi0_cs0@0 { + allwinner,pins = "PI10"; + allwinner,function = "spi0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi0_cs1_pins_a: spi0_cs1@0 { + allwinner,pins = "PI14"; allwinner,function = "spi0"; allwinner,drive = ; allwinner,pull = ; }; spi1_pins_a: spi1@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,pins = "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi1_cs0_pins_a: spi1_cs0@0 { + allwinner,pins = "PI16"; allwinner,function = "spi1"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_a: spi2@0 { - allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,pins = "PC20", "PC21", "PC22"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; spi2_pins_b: spi2@1 { - allwinner,pins = "PB14", "PB15", "PB16", "PB17"; + allwinner,pins = "PB15", "PB16", "PB17"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_a: spi2_cs0@0 { + allwinner,pins = "PC19"; + allwinner,function = "spi2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + spi2_cs0_pins_b: spi2_cs0@1 { + allwinner,pins = "PB14"; allwinner,function = "spi2"; allwinner,drive = ; allwinner,pull = ; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; allwinner,function = "mmc0"; allwinner,drive = ; allwinner,pull = ; @@ -938,28 +1033,44 @@ }; mmc2_pins_a: mmc2@0 { - allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; + allwinner,pins = "PC6", "PC7", "PC8", + "PC9", "PC10", "PC11"; allwinner,function = "mmc2"; allwinner,drive = ; allwinner,pull = ; }; mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; allwinner,function = "mmc3"; allwinner,drive = ; allwinner,pull = ; }; - ir0_pins_a: ir0@0 { - allwinner,pins = "PB3","PB4"; + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; allwinner,function = "ir0"; allwinner,drive = ; allwinner,pull = ; }; - ir1_pins_a: ir1@0 { - allwinner,pins = "PB22","PB23"; + ir0_tx_pins_a: ir0@1 { + allwinner,pins = "PB3"; + allwinner,function = "ir0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_rx_pins_a: ir1@0 { + allwinner,pins = "PB23"; + allwinner,function = "ir1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + ir1_tx_pins_a: ir1@1 { + allwinner,pins = "PB22"; allwinner,function = "ir1"; allwinner,drive = ; allwinner,pull = ; @@ -1042,7 +1153,7 @@ }; rtp: rtp@01c25000 { - compatible = "allwinner,sun4i-a10-ts"; + compatible = "allwinner,sun5i-a13-ts"; reg = <0x01c25000 0x100>; interrupts = ; #thermal-sensor-cells = <0>; @@ -1129,7 +1240,8 @@ }; i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; clocks = <&apb1_gates 0>; @@ -1139,7 +1251,8 @@ }; i2c1: i2c@01c2b000 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; clocks = <&apb1_gates 1>; @@ -1149,7 +1262,8 @@ }; i2c2: i2c@01c2b400 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = ; clocks = <&apb1_gates 2>; @@ -1159,7 +1273,8 @@ }; i2c3: i2c@01c2b800 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = ; clocks = <&apb1_gates 3>; @@ -1169,7 +1284,8 @@ }; i2c4: i2c@01c2c000 { - compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; + compatible = "allwinner,sun7i-a20-i2c", + "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = ; clocks = <&apb1_gates 15>; diff --git a/dts/src/arm/sun8i-a23-a33.dtsi b/dts/src/arm/sun8i-a23-a33.dtsi new file mode 100644 index 0000000000..7abd0ae314 --- /dev/null +++ b/dts/src/arm/sun8i-a23-a33.dtsi @@ -0,0 +1,636 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include + +#include + +/ { + interrupt-parent = <&gic>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0"; + clocks = <&pll6 0>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + cpus { + enable-method = "allwinner,sun8i-a23"; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll5: pll5_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll5"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + + /* + * PLL1 is listed twice here. + * While it looks suspicious, it's actually documented + * that way both in the datasheet and in the code from + * Allwinner. + */ + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + ahb1_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb1>; + clock-output-names = "ahb1_mipidsi", "ahb1_dma", + "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", + "ahb1_nand", "ahb1_sdram", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", "ahb1_ehci", + "ahb1_ohci", "ahb1_ve", "ahb1_lcd", + "ahb1_csi", "ahb1_be", "ahb1_fe", + "ahb1_gpu", "ahb1_spinlock", + "ahb1_drc"; + }; + + apb1_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_codec", "apb1_pio", + "apb1_daudio0", "apb1_daudio1"; + }; + + apb2: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + apb2_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb2>; + clock-output-names = "apb2_i2c0", "apb2_i2c1", + "apb2_i2c2", "apb2_uart0", + "apb2_uart1", "apb2_uart2", + "apb2_uart3", "apb2_uart4"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-a23-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", + "usb_hsic_12M", "usb_ohci0"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-a23-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c20800 0x400>; + /* interrupts get set in SoC specific dtsi file */ + clocks = <&apb1_gates 5>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PE12", "PE13"; + allwinner,function = "i2c2"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + }; + + lradc: lradc@01c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = ; + status = "disabled"; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 20>; + resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&apb2_gates 0>; + resets = <&apb2_rst 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&apb2_gates 1>; + resets = <&apb2_rst 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&apb2_gates 2>; + resets = <&apb2_rst 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = , + ; + }; + + prcm@01f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + + cpucfg@01f01c00 { + compatible = "allwinner,sun8i-a23-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + + r_uart: serial@01f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; + status = "disabled"; + }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-a23-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = ; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + r_uart_pins_a: r_uart@0 { + allwinner,pins = "PL2", "PL3"; + allwinner,function = "s_uart"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + }; +}; diff --git a/dts/src/arm/sun8i-a23-evb.dts b/dts/src/arm/sun8i-a23-evb.dts new file mode 100644 index 0000000000..610786e635 --- /dev/null +++ b/dts/src/arm/sun8i-a23-evb.dts @@ -0,0 +1,134 @@ +/* + * Copyright 2015 Maxime Ripard + * + * Maxime Ripard + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Allwinner A23 Evaluation Board"; + compatible = "allwinner,sun8i-a23-evb", "allwinner,sun8i-a23"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &r_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@190 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <190000>; + }; + + button@390 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <390000>; + }; + + button@600 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_evb: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +/* + * The RX line has a non-populated resistance. In order to use it, you + * need to solder R207 on the back of the board in order to close the + * line and get a working UART. + */ +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a23-ippo-q8h-v1.2.dts b/dts/src/arm/sun8i-a23-ippo-q8h-v1.2.dts index dd31c53e2a..382d64c3b7 100644 --- a/dts/src/arm/sun8i-a23-ippo-q8h-v1.2.dts +++ b/dts/src/arm/sun8i-a23-ippo-q8h-v1.2.dts @@ -16,11 +16,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person diff --git a/dts/src/arm/sun8i-a23-ippo-q8h-v5.dts b/dts/src/arm/sun8i-a23-ippo-q8h-v5.dts index 623573e460..95134c69cf 100644 --- a/dts/src/arm/sun8i-a23-ippo-q8h-v5.dts +++ b/dts/src/arm/sun8i-a23-ippo-q8h-v5.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -64,71 +59,69 @@ }; chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; +}; - soc@01c00000 { - mmc0: mmc@01c0f000 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; - }; - - pinctrl@01c20800 { - mmc0_cd_pin_q8h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; - lradc: lradc@01c22800 { - vref-supply = <®_vcc3v0>; - status = "okay"; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + /* pull-ups and devices require PMIC regulator */ + status = "failed"; +}; - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - }; +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - /* pull-ups and devices require PMIC regulator */ - status = "failed"; - }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; - r_uart: serial@01f02800 { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; - }; +&pio { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; }; }; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a23.dtsi b/dts/src/arm/sun8i-a23.dtsi index 382ebd137e..8698f7aa31 100644 --- a/dts/src/arm/sun8i-a23.dtsi +++ b/dts/src/arm/sun8i-a23.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -47,206 +42,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - -#include - -#include +#include "sun8i-a23-a33.dtsi" / { - interrupt-parent = <&gic>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - }; - }; - memory { reg = <0x40000000 0x40000000>; }; clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - /* dummy clock until actually implemented */ - pll5: pll5_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll5"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - }; - - apb1: apb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-output-names = "ahb1_mipidsi", "ahb1_dma", - "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", - "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_spinlock", - "ahb1_drc"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-output-names = "apb1_codec", "apb1_pio", - "apb1_daudio0", "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_uart0", - "apb2_uart1", "apb2_uart2", - "apb2_uart3", "apb2_uart4"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-mbus-clk"; @@ -255,357 +58,11 @@ clock-output-names = "mbus"; }; }; +}; - soc@01c00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun8i-a23-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; - #dma-cells = <1>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb1_rst 8>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb1_rst 9>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ahb1_rst 10>; - reset-names = "ahb"; - interrupts = ; - status = "disabled"; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-a23-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - , - ; - clocks = <&apb1_gates 5>; - gpio-controller; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <3>; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; - allwinner,function = "mmc0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; - allwinner,function = "mmc1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH2", "PH3"; - allwinner,function = "i2c0"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "i2c1"; - allwinner,drive = ; - allwinner,pull = ; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PE12", "PE13"; - allwinner,function = "i2c2"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = , - ; - clocks = <&osc24M>; - }; - - wdt0: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - }; - - lradc: lradc@01c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@01c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; - dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; - - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = , - ; - }; - - prcm@01f01400 { - compatible = "allwinner,sun8i-a23-prcm"; - reg = <0x01f01400 0x200>; - - ar100: ar100_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "ar100"; - }; - - ahb0: ahb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&ar100>; - clock-output-names = "ahb0"; - }; - - apb0: apb0_clk { - compatible = "allwinner,sun8i-a23-apb0-clk"; - #clock-cells = <0>; - clocks = <&ahb0>; - clock-output-names = "apb0"; - }; - - apb0_gates: apb0_gates_clk { - compatible = "allwinner,sun8i-a23-apb0-gates-clk"; - #clock-cells = <1>; - clocks = <&apb0>; - clock-output-names = "apb0_pio", "apb0_timer", - "apb0_rsb", "apb0_uart", - "apb0_i2c"; - }; - - apb0_rst: apb0_rst { - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - }; - - r_uart: serial@01f02800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01f02800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apb0_gates 4>; - resets = <&apb0_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun8i-a23-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&apb0_gates 0>; - resets = <&apb0_rst 0>; - gpio-controller; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #gpio-cells = <3>; - - r_uart_pins_a: r_uart@0 { - allwinner,pins = "PL2", "PL3"; - allwinner,function = "s_uart"; - allwinner,drive = ; - allwinner,pull = ; - }; - }; - }; +&pio { + compatible = "allwinner,sun8i-a23-pinctrl"; + interrupts = , + , + ; }; diff --git a/dts/src/arm/sun8i-a33-et-q8-v1.6.dts b/dts/src/arm/sun8i-a33-et-q8-v1.6.dts new file mode 100644 index 0000000000..19db844863 --- /dev/null +++ b/dts/src/arm/sun8i-a33-et-q8-v1.6.dts @@ -0,0 +1,88 @@ +/* + * Copyright 2015 Vishnu Patekar + * Vishnu Patekar + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "ET Q8 Quad Core Tablet (v1.6)"; + compatible = "et,q8-v1.6", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a33-ga10h-v1.1.dts b/dts/src/arm/sun8i-a33-ga10h-v1.1.dts new file mode 100644 index 0000000000..866703355b --- /dev/null +++ b/dts/src/arm/sun8i-a33-ga10h-v1.1.dts @@ -0,0 +1,125 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Allwinner GA10H Quad Core Tablet (v1.1)"; + compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; + + aliases { + serial0 = &r_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; + + button@600 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a33-sinlinx-sina33.dts b/dts/src/arm/sun8i-a33-sinlinx-sina33.dts new file mode 100644 index 0000000000..5788c29cb5 --- /dev/null +++ b/dts/src/arm/sun8i-a33-sinlinx-sina33.dts @@ -0,0 +1,129 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Sinlinx SinA33"; + compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191011>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <391304>; + }; + + button@600 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* eMMC is missing pull-ups */ + allwinner,pull = ; +}; + +&pio { + mmc0_cd_pin_sina33: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; diff --git a/dts/src/arm/sun8i-a33.dtsi b/dts/src/arm/sun8i-a33.dtsi new file mode 100644 index 0000000000..85ee08098b --- /dev/null +++ b/dts/src/arm/sun8i-a33.dtsi @@ -0,0 +1,97 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-a23-a33.dtsi" + +/ { + cpus { + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + /* Dummy clock for pll11 (DDR1) until actually implemented */ + pll11: pll11_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll11"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>; + clock-output-names = "mbus"; + }; + }; +}; + +&pio { + compatible = "allwinner,sun8i-a33-pinctrl"; + interrupts = , + ; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + +}; diff --git a/dts/src/arm/sun9i-a80-cubieboard4.dts b/dts/src/arm/sun9i-a80-cubieboard4.dts new file mode 100644 index 0000000000..6484dcf698 --- /dev/null +++ b/dts/src/arm/sun9i-a80-cubieboard4.dts @@ -0,0 +1,99 @@ +/* + * Copyright 2015 Tyler Baker + * + * Tyler Baker + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun9i-a80.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Cubietech Cubieboard4"; + compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + +}; + +&pio { + mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 { + allwinner,pins = "PH18"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/dts/src/arm/sun9i-a80-optimus.dts b/dts/src/arm/sun9i-a80-optimus.dts index a3fed2bdf6..6ce4b5e8b6 100644 --- a/dts/src/arm/sun9i-a80-optimus.dts +++ b/dts/src/arm/sun9i-a80-optimus.dts @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -64,7 +59,7 @@ }; chosen { - bootargs = "earlyprintk console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; }; leds { @@ -86,6 +81,29 @@ gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; }; }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_pin_optimus>; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; }; &i2c3 { @@ -99,6 +117,14 @@ allwinner,pull = ; }; +&ohci0 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; @@ -113,6 +139,20 @@ allwinner,drive = ; allwinner,pull = ; }; + + usb1_vbus_pin_optimus: usb1_vbus_pin@1 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb3_vbus_pin_optimus: usb3_vbus_pin@1 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &mmc0 { @@ -134,6 +174,12 @@ status = "okay"; }; +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_optimus>; + gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -150,3 +196,17 @@ /* Enable internal pull-up */ allwinner,pull = ; }; + +&usbphy1 { + phy-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbphy3 { + phy-supply = <®_usb3_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/sun9i-a80.dtsi b/dts/src/arm/sun9i-a80.dtsi index f0f6fb91f8..a43ad779ee 100644 --- a/dts/src/arm/sun9i-a80.dtsi +++ b/dts/src/arm/sun9i-a80.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person @@ -114,6 +109,16 @@ reg = <0 0x20000000 0x02 0>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -137,6 +142,28 @@ clock-output-names = "osc32k"; }; + usb_mod_clk: clk@00a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + + usb_phy_clk: clk@00a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + pll4: clk@0600000c { #clock-cells = <0>; compatible = "allwinner,sun9i-a80-pll4-clk"; @@ -257,7 +284,7 @@ "ahb0_ss", "ahb0_sd", "ahb0_nand1", "ahb0_nand0", "ahb0_sdram", "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", - "ahb0_spi0","ahb0_spi1", "ahb0_spi2", + "ahb0_spi0", "ahb0_spi1", "ahb0_spi2", "ahb0_spi3"; }; @@ -323,6 +350,98 @@ */ ranges = <0 0 0 0x20000000>; + ehci0: usb@00a00000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a00000 0x100>; + interrupts = ; + clocks = <&usb_mod_clk 1>; + resets = <&usb_mod_clk 17>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@00a00400 { + compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; + reg = <0x00a00400 0x100>; + interrupts = ; + clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; + resets = <&usb_mod_clk 17>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy1: phy@00a00800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a00800 0x4>; + clocks = <&usb_phy_clk 1>; + clock-names = "phy"; + resets = <&usb_phy_clk 17>; + reset-names = "phy"; + status = "disabled"; + #phy-cells = <0>; + }; + + ehci1: usb@00a01000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a01000 0x100>; + interrupts = ; + clocks = <&usb_mod_clk 3>; + resets = <&usb_mod_clk 18>; + phys = <&usbphy2>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy2: phy@00a01800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a01800 0x4>; + clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, + <&usb_phy_clk 3>; + clock-names = "hsic_480M", "hsic_12M", "phy"; + resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; + reset-names = "hsic", "phy"; + status = "disabled"; + #phy-cells = <0>; + /* usb1 is always used with HSIC */ + phy_type = "hsic"; + }; + + ehci2: usb@00a02000 { + compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; + reg = <0x00a02000 0x100>; + interrupts = ; + clocks = <&usb_mod_clk 5>; + resets = <&usb_mod_clk 19>; + phys = <&usbphy3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@00a02400 { + compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; + reg = <0x00a02400 0x100>; + interrupts = ; + clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; + resets = <&usb_mod_clk 19>; + phys = <&usbphy3>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy3: phy@00a02800 { + compatible = "allwinner,sun9i-a80-usb-phy"; + reg = <0x00a02800 0x4>; + clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, + <&usb_phy_clk 5>; + clock-names = "hsic_480M", "hsic_12M", "phy"; + resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; + reset-names = "hsic", "phy"; + status = "disabled"; + #phy-cells = <0>; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; @@ -333,6 +452,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -345,6 +466,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -357,6 +480,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc3: mmc@01c12000 { @@ -369,6 +494,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; mmc_config_clk: clk@01c13000 { @@ -438,6 +565,12 @@ clocks = <&osc24M>; }; + wdt: watchdog@06000ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x06000ca0 0x20>; + interrupts = ; + }; + pio: pinctrl@06000800 { compatible = "allwinner,sun9i-a80-pinctrl"; reg = <0x06000800 0x400>; diff --git a/dts/src/arm/sunxi-common-regulators.dtsi b/dts/src/arm/sunxi-common-regulators.dtsi index e02baa66b3..51cc8383f7 100644 --- a/dts/src/arm/sunxi-common-regulators.dtsi +++ b/dts/src/arm/sunxi-common-regulators.dtsi @@ -18,11 +18,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person diff --git a/dts/src/arm/tegra124-jetson-tk1.dts b/dts/src/arm/tegra124-jetson-tk1.dts index ed8a8acd3d..bd43ed6d6e 100644 --- a/dts/src/arm/tegra124-jetson-tk1.dts +++ b/dts/src/arm/tegra124-jetson-tk1.dts @@ -1647,6 +1647,10 @@ target-12v-supply = <&vdd_12v0_sata>; }; + hda@0,70030000 { + status = "okay"; + }; + padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; diff --git a/dts/src/arm/tegra124-venice2.dts b/dts/src/arm/tegra124-venice2.dts index 5c3f781336..79e724bb7d 100644 --- a/dts/src/arm/tegra124-venice2.dts +++ b/dts/src/arm/tegra124-venice2.dts @@ -899,6 +899,7 @@ sdhci@0,700b0600 { status = "okay"; bus-width = <8>; + non-removable; }; ahub@0,70300000 { @@ -1040,6 +1041,8 @@ compatible = "regulator-fixed"; reg = <5>; regulator-name = "+VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_mux>; diff --git a/dts/src/arm/tegra124.dtsi b/dts/src/arm/tegra124.dtsi index 13cc7ca5e0..01a9f742b0 100644 --- a/dts/src/arm/tegra124.dtsi +++ b/dts/src/arm/tegra124.dtsi @@ -300,7 +300,7 @@ apbmisc@0,70000800 { compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ + <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ }; pinmux: pinmux@0,70000868 { @@ -633,11 +633,11 @@ clocks = <&tegra_car TEGRA124_CLK_HDA>, <&tegra_car TEGRA124_CLK_HDA2HDMI>, <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hdacodec_2x"; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; resets = <&tegra_car 125>, /* hda */ <&tegra_car 128>, /* hda2hdmi */ <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hdacodec_2x"; + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; status = "disabled"; }; diff --git a/dts/src/arm/tegra20-seaboard.dts b/dts/src/arm/tegra20-seaboard.dts index e2fed27122..aea8994b35 100644 --- a/dts/src/arm/tegra20-seaboard.dts +++ b/dts/src/arm/tegra20-seaboard.dts @@ -31,6 +31,7 @@ vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) @@ -893,6 +894,17 @@ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vdd_hdmi: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; }; sound { diff --git a/dts/src/arm/tegra20.dtsi b/dts/src/arm/tegra20.dtsi index adf6b048d0..f444b67f55 100644 --- a/dts/src/arm/tegra20.dtsi +++ b/dts/src/arm/tegra20.dtsi @@ -563,7 +563,7 @@ fuse@7000f800 { compatible = "nvidia,tegra20-efuse"; - reg = <0x7000F800 0x400>; + reg = <0x7000f800 0x400>; clocks = <&tegra_car TEGRA20_CLK_FUSE>; clock-names = "fuse"; resets = <&tegra_car 39>; diff --git a/dts/src/arm/tegra30-cardhu.dtsi b/dts/src/arm/tegra30-cardhu.dtsi index a1b682ea01..bb1ca15827 100644 --- a/dts/src/arm/tegra30-cardhu.dtsi +++ b/dts/src/arm/tegra30-cardhu.dtsi @@ -1,3 +1,4 @@ +#include #include "tegra30.dtsi" /** @@ -12,7 +13,7 @@ * tegra30-cardhu-a04.dts. * The identification of board is done in two ways, by looking the sticker * on PCB and by reading board id eeprom. - * The stciker will have number like 600-81291-1000-002 C.3. In this 4th + * The sticker will have number like 600-81291-1000-002 C.3. In this 4th * number is the fab version like here it is 002 and hence fab version A02. * The (downstream internal) U-Boot of Cardhu display the board-id as * follows: @@ -615,4 +616,31 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + interrupt-parent = <&pmic>; + interrupts = <2 0>; + linux,code = ; + debounce-interval = <100>; + gpio-key,wakeup; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; }; diff --git a/dts/src/arm/tegra30.dtsi b/dts/src/arm/tegra30.dtsi index 60e205a0f6..782b11b2af 100644 --- a/dts/src/arm/tegra30.dtsi +++ b/dts/src/arm/tegra30.dtsi @@ -654,6 +654,21 @@ reset-names = "fuse"; }; + hda@70030000 { + compatible = "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_HDA>, + <&tegra_car TEGRA30_CLK_HDA2HDMI>, + <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + ahub@70080000 { compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 diff --git a/dts/src/arm/uniphier-ph1-ld4-ref.dts b/dts/src/arm/uniphier-ph1-ld4-ref.dts new file mode 100644 index 0000000000..200b0c99ed --- /dev/null +++ b/dts/src/arm/uniphier-ph1-ld4-ref.dts @@ -0,0 +1,79 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 Reference Board + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-ld4.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-LD4 Reference Board"; + compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serialsc; + }; + + aliases { + serial0 = &serialsc; + }; +}; + +&extbus { + ranges = <0 0x00000000 0x0f000000 0x01000000 + 1 0x00000000 0x00000000 0x08000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x03f00000 0x00100000>; +}; + +&serialsc { + interrupts = <0 49 4>; +}; diff --git a/dts/src/arm/uniphier-ph1-ld4.dtsi b/dts/src/arm/uniphier-ph1-ld4.dtsi new file mode 100644 index 0000000000..6a34c56e46 --- /dev/null +++ b/dts/src/arm/uniphier-ph1-ld4.dtsi @@ -0,0 +1,110 @@ +/* + * Device Tree Source for UniPhier PH1-LD4 SoC + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,ph1-ld4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + }; +}; diff --git a/dts/src/arm/uniphier-ph1-pro4-ref.dts b/dts/src/arm/uniphier-ph1-pro4-ref.dts new file mode 100644 index 0000000000..d891135a70 --- /dev/null +++ b/dts/src/arm/uniphier-ph1-pro4-ref.dts @@ -0,0 +1,79 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 Reference Board + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-Pro4 Reference Board"; + compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serialsc; + }; + + aliases { + serial0 = &serialsc; + }; +}; + +&extbus { + ranges = <0 0x00000000 0x0f000000 0x01000000 + 1 0x00000000 0x00000000 0x08000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x03f00000 0x00100000>; +}; + +&serialsc { + interrupts = <0 50 4>; +}; diff --git a/dts/src/arm/uniphier-ph1-pro4.dtsi b/dts/src/arm/uniphier-ph1-pro4.dtsi new file mode 100644 index 0000000000..dc633603ae --- /dev/null +++ b/dts/src/arm/uniphier-ph1-pro4.dtsi @@ -0,0 +1,117 @@ +/* + * Device Tree Source for UniPhier PH1-Pro4 SoC + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,ph1-pro4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + }; +}; diff --git a/dts/src/arm/uniphier-ph1-sld3-ref.dts b/dts/src/arm/uniphier-ph1-sld3-ref.dts new file mode 100644 index 0000000000..3ea64ae009 --- /dev/null +++ b/dts/src/arm/uniphier-ph1-sld3-ref.dts @@ -0,0 +1,80 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 Reference Board + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld3.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-sLD3 Reference Board"; + compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000 + 0xc0000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serialsc; + }; + + aliases { + serial0 = &serialsc; + }; +}; + +&extbus { + ranges = <0 0x00000000 0x0f000000 0x01000000 + 1 0x00000000 0x00000000 0x08000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x03f00000 0x00100000>; +}; + +&serialsc { + interrupts = <0 49 4>; +}; diff --git a/dts/src/arm/uniphier-ph1-sld3.dtsi b/dts/src/arm/uniphier-ph1-sld3.dtsi new file mode 100644 index 0000000000..248b188683 --- /dev/null +++ b/dts/src/arm/uniphier-ph1-sld3.dtsi @@ -0,0 +1,117 @@ +/* + * Device Tree Source for UniPhier PH1-sLD3 SoC + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,ph1-sld3"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + timer@20000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x20001000 0x1000>, + <0x20000100 0x100>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + }; +}; diff --git a/dts/src/arm/uniphier-ph1-sld8-ref.dts b/dts/src/arm/uniphier-ph1-sld8-ref.dts new file mode 100644 index 0000000000..dcdc4f7438 --- /dev/null +++ b/dts/src/arm/uniphier-ph1-sld8-ref.dts @@ -0,0 +1,79 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 Reference Board + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-sld8.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-sLD8 Reference Board"; + compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serialsc; + }; + + aliases { + serial0 = &serialsc; + }; +}; + +&extbus { + ranges = <0 0x00000000 0x0f000000 0x01000000 + 1 0x00000000 0x00000000 0x08000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x03f00000 0x00100000>; +}; + +&serialsc { + interrupts = <0 48 4>; +}; diff --git a/dts/src/arm/uniphier-ph1-sld8.dtsi b/dts/src/arm/uniphier-ph1-sld8.dtsi new file mode 100644 index 0000000000..baa71e1feb --- /dev/null +++ b/dts/src/arm/uniphier-ph1-sld8.dtsi @@ -0,0 +1,110 @@ +/* + * Device Tree Source for UniPhier PH1-sLD8 SoC + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,ph1-sld8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + }; +}; diff --git a/dts/src/arm/uniphier-support-card.dtsi b/dts/src/arm/uniphier-support-card.dtsi new file mode 100644 index 0000000000..da271e3b92 --- /dev/null +++ b/dts/src/arm/uniphier-support-card.dtsi @@ -0,0 +1,65 @@ +/* + * Device Tree Source for UniPhier Support Card (Expansion Board) + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +&extbus { + support_card: support_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ethsc: ethernet@00000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x00000000 0x1000>; + phy-mode = "mii"; + reg-io-width = <4>; + }; + + serialsc: uart@000b0000 { + compatible = "ns16550a"; + reg = <0x000b0000 0x20>; + clock-frequency = <12288000>; + reg-shift = <1>; + }; + }; +}; diff --git a/dts/src/arm/vf-colibri.dtsi b/dts/src/arm/vf-colibri.dtsi index fbef0828e9..68ca125b56 100644 --- a/dts/src/arm/vf-colibri.dtsi +++ b/dts/src/arm/vf-colibri.dtsi @@ -140,7 +140,7 @@ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 diff --git a/dts/src/arm/vf610-cosmic.dts b/dts/src/arm/vf610-cosmic.dts index fd8758b639..5447f25946 100644 --- a/dts/src/arm/vf610-cosmic.dts +++ b/dts/src/arm/vf610-cosmic.dts @@ -68,7 +68,7 @@ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 diff --git a/dts/src/arm/vf610-pinfunc.h b/dts/src/arm/vf610-pinfunc.h index 1ee681f7ce..fcad7132c8 100644 --- a/dts/src/arm/vf610-pinfunc.h +++ b/dts/src/arm/vf610-pinfunc.h @@ -369,7 +369,7 @@ #define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 #define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 #define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 -#define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0 +#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 #define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 #define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 #define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 diff --git a/dts/src/arm/vf610-twr.dts b/dts/src/arm/vf610-twr.dts index f64fddce3e..375ab23ca7 100644 --- a/dts/src/arm/vf610-twr.dts +++ b/dts/src/arm/vf610-twr.dts @@ -221,7 +221,7 @@ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 - VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 diff --git a/dts/src/arm/vf610m4-colibri.dts b/dts/src/arm/vf610m4-colibri.dts new file mode 100644 index 0000000000..2931a80cac --- /dev/null +++ b/dts/src/arm/vf610m4-colibri.dts @@ -0,0 +1,99 @@ +/* + * Device tree for Colibri VF61 Cortex-M4 support + * + * Copyright (C) 2015 Stefan Agner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "vf610m4.dtsi" + +/ { + model = "VF610 Cortex-M4"; + compatible = "fsl,vf610m4"; + + chosen { + bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw"; + linux,stdout-path = "&uart2"; + }; + + memory { + reg = <0x8c000000 0x3000000>; + }; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio3 { + status = "disabled"; +}; + +&gpio4 { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&iomuxc { + vf610-colibri { + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + }; +}; diff --git a/dts/src/arm/vf610m4.dtsi b/dts/src/arm/vf610m4.dtsi new file mode 100644 index 0000000000..9ffe2eb68e --- /dev/null +++ b/dts/src/arm/vf610m4.dtsi @@ -0,0 +1,50 @@ +/* + * Device tree for VF6xx Cortex-M4 support + * + * Copyright (C) 2015 Stefan Agner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armv7-m.dtsi" +#include "vfxxx.dtsi" + +&mscm_ir { + interrupt-parent = <&nvic>; +}; diff --git a/dts/src/arm/zx296702-ad1.dts b/dts/src/arm/zx296702-ad1.dts new file mode 100644 index 0000000000..081f980cfb --- /dev/null +++ b/dts/src/arm/zx296702-ad1.dts @@ -0,0 +1,48 @@ + +/dts-v1/; + +#include "zx296702.dtsi" + +/ { + model = "ZTE ZX296702 AD1 Board"; + compatible = "zte,zx296702-ad1", "zte,zx296702"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x50000000 0x20000000>; + }; +}; + +&mmc0 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&mmc1 { + num-slots = <1>; + supports-highspeed; + non-removable; + disable-wp; + status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/src/arm/zx296702.dtsi b/dts/src/arm/zx296702.dtsi new file mode 100644 index 0000000000..d45c8fcd7a --- /dev/null +++ b/dts/src/arm/zx296702.dtsi @@ -0,0 +1,139 @@ + +#include "skeleton.dtsi" +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "zte,zx296702-smp"; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2cc>; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2cc>; + reg = <1>; + }; + }; + + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + matrix: bus-matrix@400000 { + compatible = "zte,zx-bus-matrix"; + reg = <0x00400000 0x1000>; + }; + + intc: interrupt-controller@00801000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00801000 0x1000>, + <0x00800100 0x100>; + }; + + global_timer: timer@008000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x00800200 0x20>; + interrupts = ; + interrupt-parent = <&intc>; + clocks = <&topclk ZX296702_A9_PERIPHCLK>; + }; + + l2cc: l2-cache-controller@0x00c00000 { + compatible = "arm,pl310-cache"; + reg = <0x00c00000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + }; + + pcu: pcu@0xa0008000 { + compatible = "zte,zx296702-pcu"; + reg = <0xa0008000 0x1000>; + }; + + topclk: topclk@0x09800000 { + compatible = "zte,zx296702-topcrm-clk"; + reg = <0x09800000 0x1000>; + #clock-cells = <1>; + }; + + lsp1clk: lsp1clk@0x09400000 { + compatible = "zte,zx296702-lsp1crpm-clk"; + reg = <0x09400000 0x1000>; + #clock-cells = <1>; + }; + + lsp0clk: lsp0clk@0x0b000000 { + compatible = "zte,zx296702-lsp0crpm-clk"; + reg = <0x0b000000 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@0x09405000 { + compatible = "zte,zx296702-uart"; + reg = <0x09405000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART0_WCLK>; + status = "disabled"; + }; + + uart1: serial@0x09406000 { + compatible = "zte,zx296702-uart"; + reg = <0x09406000 0x1000>; + interrupts = ; + clocks = <&lsp1clk ZX296702_UART1_WCLK>; + status = "disabled"; + }; + + mmc0: mmc@0x09408000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x09408000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>, + <&lsp1clk ZX296702_SDMMC0_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + mmc1: mmc@0x0b003000 { + compatible = "snps,dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0b003000 0x1000>; + interrupts = ; + fifo-depth = <32>; + clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>, + <&lsp0clk ZX296702_SDMMC1_WCLK>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + sysctrl: sysctrl@0xa0007000 { + compatible = "zte,sysctrl", "syscon"; + reg = <0xa0007000 0x1000>; + }; + }; +}; diff --git a/dts/src/arm/zynq-7000.dtsi b/dts/src/arm/zynq-7000.dtsi index 9ea54b3dba..06915080b8 100644 --- a/dts/src/arm/zynq-7000.dtsi +++ b/dts/src/arm/zynq-7000.dtsi @@ -193,7 +193,7 @@ }; gem0: ethernet@e000b000 { - compatible = "cdns,zynq-gem"; + compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; @@ -204,7 +204,7 @@ }; gem1: ethernet@e000c000 { - compatible = "cdns,zynq-gem"; + compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; diff --git a/dts/src/arm/zynq-parallella.dts b/dts/src/arm/zynq-parallella.dts index 174571232e..9efd16cb28 100644 --- a/dts/src/arm/zynq-parallella.dts +++ b/dts/src/arm/zynq-parallella.dts @@ -23,14 +23,19 @@ model = "Adapteva Parallella Board"; compatible = "adapteva,parallella", "xlnx,zynq-7000"; + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0x0 0x40000000>; }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; - linux,stdout-path = "/amba/serial@e0001000"; + bootargs = "earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait"; + stdout-path = "serial0:115200n8"; }; }; diff --git a/dts/src/arm/zynq-zc702.dts b/dts/src/arm/zynq-zc702.dts index 1fc1d3911e..fb59d34e8e 100644 --- a/dts/src/arm/zynq-zc702.dts +++ b/dts/src/arm/zynq-zc702.dts @@ -30,7 +30,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/src/arm/zynq-zc706.dts b/dts/src/arm/zynq-zc706.dts index 850518d9b8..abf5d238ae 100644 --- a/dts/src/arm/zynq-zc706.dts +++ b/dts/src/arm/zynq-zc706.dts @@ -30,7 +30,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; usb_phy0: phy0 { diff --git a/dts/src/arm/zynq-zed.dts b/dts/src/arm/zynq-zed.dts index 5658bc8434..b9f2522012 100644 --- a/dts/src/arm/zynq-zed.dts +++ b/dts/src/arm/zynq-zed.dts @@ -29,7 +29,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; usb_phy0: phy0 { diff --git a/dts/src/arm/zynq-zybo.dts b/dts/src/arm/zynq-zybo.dts index a9a12ce502..16c9cacd66 100644 --- a/dts/src/arm/zynq-zybo.dts +++ b/dts/src/arm/zynq-zybo.dts @@ -18,13 +18,19 @@ model = "Zynq ZYBO Development Board"; compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + memory { device_type = "memory"; reg = <0x0 0x20000000>; }; chosen { - bootargs = "console=ttyPS0,115200 earlyprintk"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; }; diff --git a/dts/src/arm64/apm/apm-storm.dtsi b/dts/src/arm64/apm/apm-storm.dtsi index c8d3e0e866..0689c3fb56 100644 --- a/dts/src/arm64/apm/apm-storm.dtsi +++ b/dts/src/arm64/apm/apm-storm.dtsi @@ -374,6 +374,111 @@ }; }; + msi: msi@79000000 { + compatible = "apm,xgene1-msi"; + msi-controller; + reg = <0x00 0x79000000 0x0 0x900000>; + interrupts = < 0x0 0x10 0x4 + 0x0 0x11 0x4 + 0x0 0x12 0x4 + 0x0 0x13 0x4 + 0x0 0x14 0x4 + 0x0 0x15 0x4 + 0x0 0x16 0x4 + 0x0 0x17 0x4 + 0x0 0x18 0x4 + 0x0 0x19 0x4 + 0x0 0x1a 0x4 + 0x0 0x1b 0x4 + 0x0 0x1c 0x4 + 0x0 0x1d 0x4 + 0x0 0x1e 0x4 + 0x0 0x1f 0x4>; + }; + + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + efuse: efuse@1054a000 { + compatible = "apm,xgene-efuse", "syscon"; + reg = <0x0 0x1054a000 0x0 0x20>; + }; + + edac@78800000 { + compatible = "apm,xgene-edac"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + reg = <0x0 0x78800000 0x0 0x100>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacmc@7e840000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e840000 0x0 0x1000>; + memory-controller = <1>; + }; + + edacmc@7e880000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e880000 0x0 0x1000>; + memory-controller = <2>; + }; + + edacmc@7e8c0000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e8c0000 0x0 0x1000>; + memory-controller = <3>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + + edacpmd@7c200000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c200000 0x0 0x200000>; + pmd-controller = <1>; + }; + + edacpmd@7c400000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c400000 0x0 0x200000>; + pmd-controller = <2>; + }; + + edacpmd@7c600000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c600000 0x0 0x200000>; + pmd-controller = <3>; + }; + }; + pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; @@ -395,6 +500,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; dma-coherent; clocks = <&pcie0clk 0>; + msi-parent = <&msi>; }; pcie1: pcie@1f2c0000 { @@ -418,6 +524,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; dma-coherent; clocks = <&pcie1clk 0>; + msi-parent = <&msi>; }; pcie2: pcie@1f2d0000 { @@ -441,6 +548,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; dma-coherent; clocks = <&pcie2clk 0>; + msi-parent = <&msi>; }; pcie3: pcie@1f500000 { @@ -464,6 +572,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; dma-coherent; clocks = <&pcie3clk 0>; + msi-parent = <&msi>; }; pcie4: pcie@1f510000 { @@ -487,6 +596,7 @@ 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; dma-coherent; clocks = <&pcie4clk 0>; + msi-parent = <&msi>; }; serial0: serial@1c020000 { @@ -607,6 +717,19 @@ phy-names = "sata-phy"; }; + sbgpio: sbgpio@17001000{ + compatible = "apm,xgene-gpio-sb"; + reg = <0x0 0x17001000 0x0 0x400>; + #gpio-cells = <2>; + gpio-controller; + interrupts = <0x0 0x28 0x1>, + <0x0 0x29 0x1>, + <0x0 0x2a 0x1>, + <0x0 0x2b 0x1>, + <0x0 0x2c 0x1>, + <0x0 0x2d 0x1>; + }; + rtc: rtc@10510000 { compatible = "apm,xgene-rtc"; reg = <0x0 0x10510000 0x0 0x400>; diff --git a/dts/src/arm64/arm/juno-base.dtsi b/dts/src/arm64/arm/juno-base.dtsi new file mode 100644 index 0000000000..e3ee96036e --- /dev/null +++ b/dts/src/arm64/arm/juno-base.dtsi @@ -0,0 +1,154 @@ + /* + * Devices shared by all Juno boards + */ + + memtimer: timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <50000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 60 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + gic: interrupt-controller@2c010000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + reg = <0x0 0x2c010000 0 0x1000>, + <0x0 0x2c02f000 0 0x2000>, + <0x0 0x2c04f000 0 0x2000>, + <0x0 0x2c06f000 0 0x2000>; + #address-cells = <2>; + #interrupt-cells = <3>; + #size-cells = <2>; + interrupt-controller; + interrupts = ; + ranges = <0 0 0 0x2c1c0000 0 0x40000>; + v2m_0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0 0 0 0x1000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + /include/ "juno-clocks.dtsi" + + dma@7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x7ff00000 0 0x1000>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + }; + + soc_uart0: uart@7ff80000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff80000 0x0 0x1000>; + interrupts = ; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + i2c@7ffa0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x7ffa0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <500>; + clocks = <&soc_smc50mhz>; + + dvi0: dvi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; + + dvi1: dvi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + }; + }; + + ohci@7ffb0000 { + compatible = "generic-ohci"; + reg = <0x0 0x7ffb0000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_usb48mhz>; + }; + + ehci@7ffc0000 { + compatible = "generic-ehci"; + reg = <0x0 0x7ffc0000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_usb48mhz>; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = , + ; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + + memory@80000000 { + device_type = "memory"; + /* last 16MB of the first memory area is reserved for secure world use by firmware */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>, + <0x00000008 0x80000000 0x1 0x80000000>; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 15>; + interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; + + /include/ "juno-motherboard.dtsi" + }; diff --git a/dts/src/arm64/arm/juno-clocks.dtsi b/dts/src/arm64/arm/juno-clocks.dtsi index c9b89efe0f..25352ed943 100644 --- a/dts/src/arm64/arm/juno-clocks.dtsi +++ b/dts/src/arm64/arm/juno-clocks.dtsi @@ -36,9 +36,9 @@ clock-output-names = "apb_pclk"; }; - soc_faxiclk: refclk533mhz { + soc_faxiclk: refclk400mhz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <533000000>; + clock-frequency = <400000000>; clock-output-names = "faxi_clk"; }; diff --git a/dts/src/arm64/arm/juno-motherboard.dtsi b/dts/src/arm64/arm/juno-motherboard.dtsi index 351c95bda8..021e0f40f4 100644 --- a/dts/src/arm64/arm/juno-motherboard.dtsi +++ b/dts/src/arm64/arm/juno-motherboard.dtsi @@ -54,6 +54,55 @@ regulator-always-on; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + button@6 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + ethernet@2,00000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; @@ -89,6 +138,74 @@ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; + apbregs@010000 { + compatible = "syscon", "simple-mfd"; + reg = <0x010000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "vexpress:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "vexpress:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "vexpress:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "vexpress:3"; + linux,default-trigger = "cpu1"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "vexpress:4"; + linux,default-trigger = "cpu2"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "vexpress:5"; + linux,default-trigger = "cpu3"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "vexpress:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "vexpress:7"; + default-state = "off"; + }; + }; + mmci@050000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; @@ -148,5 +265,17 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; }; + + iofpga_gpio0: gpio@1d0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1d0000 0x1000>; + interrupts = <6>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; diff --git a/dts/src/arm64/arm/juno-r1.dts b/dts/src/arm64/arm/juno-r1.dts new file mode 100644 index 0000000000..c62751153a --- /dev/null +++ b/dts/src/arm64/arm/juno-r1.dts @@ -0,0 +1,116 @@ +/* + * ARM Ltd. Juno Platform + * + * Copyright (c) 2015 ARM Ltd. + * + * This file is licensed under a dual GPLv2 or BSD license. + */ + +/dts-v1/; + +#include + +/ { + model = "ARM Juno development board (r1)"; + compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A57_0: cpu@0 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + }; + + A57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x1>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A57_L2>; + }; + + A53_0: cpu@100 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x101>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x102>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x103>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A57_L2: l2-cache0 { + compatible = "cache"; + }; + + A53_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + ; + interrupt-affinity = <&A57_0>, + <&A57_1>, + <&A53_0>, + <&A53_1>, + <&A53_2>, + <&A53_3>; + }; + + #include "juno-base.dtsi" + +}; + +&memtimer { + status = "okay"; +}; diff --git a/dts/src/arm64/arm/juno.dts b/dts/src/arm64/arm/juno.dts index 5e9110a335..d7cbdd482a 100644 --- a/dts/src/arm64/arm/juno.dts +++ b/dts/src/arm64/arm/juno.dts @@ -91,33 +91,6 @@ }; }; - memory@80000000 { - device_type = "memory"; - /* last 16MB of the first memory area is reserved for secure world use by firmware */ - reg = <0x00000000 0x80000000 0x0 0x7f000000>, - <0x00000008 0x80000000 0x1 0x80000000>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - reg = <0x0 0x2c010000 0 0x1000>, - <0x0 0x2c02f000 0 0x2000>, - <0x0 0x2c04f000 0 0x2000>, - <0x0 0x2c06f000 0 0x2000>; - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = , @@ -134,105 +107,5 @@ <&A53_3>; }; - /include/ "juno-clocks.dtsi" - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0x7ff00000 0 0x1000>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&soc_faxiclk>; - clock-names = "apb_pclk"; - }; - - soc_uart0: uart@7ff80000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0x7ff80000 0x0 0x1000>; - interrupts = ; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - i2c@7ffa0000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x7ffa0000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <500>; - clocks = <&soc_smc50mhz>; - - dvi0: dvi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - }; - - dvi1: dvi-transmitter@71 { - compatible = "nxp,tda998x"; - reg = <0x71>; - }; - }; - - ohci@7ffb0000 { - compatible = "generic-ohci"; - reg = <0x0 0x7ffb0000 0x0 0x10000>; - interrupts = ; - clocks = <&soc_usb48mhz>; - }; - - ehci@7ffc0000 { - compatible = "generic-ehci"; - reg = <0x0 0x7ffc0000 0x0 0x10000>; - interrupts = ; - clocks = <&soc_usb48mhz>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = , - ; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - - smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>; - - /include/ "juno-motherboard.dtsi" - }; + #include "juno-base.dtsi" }; diff --git a/dts/src/arm64/hisilicon/hi6220-hikey.dts b/dts/src/arm64/hisilicon/hi6220-hikey.dts new file mode 100644 index 0000000000..e36a539468 --- /dev/null +++ b/dts/src/arm64/hisilicon/hi6220-hikey.dts @@ -0,0 +1,31 @@ +/* + * dts file for Hisilicon HiKey Development Board + * + * Copyright (C) 2015, Hisilicon Ltd. + * + */ + +/dts-v1/; + +/*Reserved 1MB memory for MCU*/ +/memreserve/ 0x05e00000 0x00100000; + +#include "hi6220.dtsi" + +/ { + model = "HiKey Development Board"; + compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; diff --git a/dts/src/arm64/hisilicon/hi6220.dtsi b/dts/src/arm64/hisilicon/hi6220.dtsi new file mode 100644 index 0000000000..3f03380815 --- /dev/null +++ b/dts/src/arm64/hisilicon/hi6220.dtsi @@ -0,0 +1,171 @@ +/* + * dts file for Hisilicon Hi6220 SoC + * + * Copyright (C) 2015, Hisilicon Ltd. + */ + +#include + +/ { + compatible = "hisilicon,hi6220"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f6801000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ + <0x0 0xf6802000 0 0x2000>, /* GICC */ + <0x0 0xf6804000 0 0x2000>, /* GICH */ + <0x0 0xf6806000 0 0x2000>; /* GICV */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; + + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; + + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; + + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; + + uart0: uart@f8015000 { /* console */ + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf8015000 0x0 0x1000>; + interrupts = ; + clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; + clock-names = "uartclk", "apb_pclk"; + }; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi index 924fdb6673..27237a1c1a 100644 --- a/dts/src/arm64/mediatek/mt8173.dtsi +++ b/dts/src/arm64/mediatek/mt8173.dtsi @@ -91,13 +91,13 @@ compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; soc { @@ -106,14 +106,13 @@ compatible = "simple-bus"; ranges; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@0x10005000 { + /* + * Pinctrl access register at 0x10005000 through regmap. + * Register 0x1000b000 is used by EINT. + */ + pio: pinctrl@10005000 { compatible = "mediatek,mt8173-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; + reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; pins-are-numbered; gpio-controller; @@ -121,13 +120,18 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = , - , - ; + , + ; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; }; sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8173-sysirq", - "mediatek,mt6577-sysirq"; + "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; @@ -149,7 +153,7 @@ uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -158,7 +162,7 @@ uart1: serial@11003000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -167,7 +171,7 @@ uart2: serial@11004000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; clocks = <&uart_clk>; @@ -176,13 +180,12 @@ uart3: serial@11005000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; clocks = <&uart_clk>; status = "disabled"; }; }; - }; diff --git a/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi new file mode 100644 index 0000000000..535532b928 --- /dev/null +++ b/dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi @@ -0,0 +1,30 @@ +#include + +&pm8916_gpios { + + pinctrl-names = "default"; + pinctrl-0 = <&pm8916_gpios_default>; + + pm8916_gpios_default: default { + usb_hub_reset_pm { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + usb_sw_sel_pm { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + }; + usr_led_3_ctrl { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + usr_led_4_ctrl { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; +}; diff --git a/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi b/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi new file mode 100644 index 0000000000..5f7023f90d --- /dev/null +++ b/dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi @@ -0,0 +1,21 @@ + +#include + +&msmgpio { + + pinctrl-names = "default"; + pinctrl-0 = <&soc_gpios_default>; + + soc_gpios_default: default { + usr_led_1_ctrl_default: usr_led_1_ctrl_default { + pins = "gpio21"; + function = "gpio"; + output-low; + }; + usr_led_2_ctrl_default: usr_led_2_ctrl_default { + pins = "gpio120"; + function = "gpio"; + output-low; + }; + }; +}; diff --git a/dts/src/arm64/qcom/apq8016-sbc.dtsi b/dts/src/arm64/qcom/apq8016-sbc.dtsi index 703a4f16e7..98abece6b2 100644 --- a/dts/src/arm64/qcom/apq8016-sbc.dtsi +++ b/dts/src/arm64/qcom/apq8016-sbc.dtsi @@ -12,6 +12,9 @@ */ #include "msm8916.dtsi" +#include "pm8916.dtsi" +#include "apq8016-sbc-soc-pins.dtsi" +#include "apq8016-sbc-pmic-pins.dtsi" / { aliases { diff --git a/dts/src/arm64/qcom/msm8916-mtp.dtsi b/dts/src/arm64/qcom/msm8916-mtp.dtsi index bea871b0df..a1aa0b201e 100644 --- a/dts/src/arm64/qcom/msm8916-mtp.dtsi +++ b/dts/src/arm64/qcom/msm8916-mtp.dtsi @@ -12,6 +12,7 @@ */ #include "msm8916.dtsi" +#include "pm8916.dtsi" / { aliases { diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi index f212b8303d..0f49ebd0aa 100644 --- a/dts/src/arm64/qcom/msm8916.dtsi +++ b/dts/src/arm64/qcom/msm8916.dtsi @@ -77,7 +77,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; - pinctrl@1000000 { + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + msmgpio: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; reg = <0x1000000 0x300000>; interrupts = ; @@ -192,5 +197,23 @@ status = "disabled"; }; }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x001000>, + <0x2400000 0x400000>, + <0x2c00000 0x400000>, + <0x3800000 0x200000>, + <0x200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; }; }; diff --git a/dts/src/arm64/qcom/pm8916.dtsi b/dts/src/arm64/qcom/pm8916.dtsi new file mode 100644 index 0000000000..b222ece7e3 --- /dev/null +++ b/dts/src/arm64/qcom/pm8916.dtsi @@ -0,0 +1,99 @@ +#include +#include +#include + +&spmi_bus { + + usid0: pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000 0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pm8916_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>; + }; + + pm8916_mpps: mpps@a000 { + compatible = "qcom,pm8916-mpp"; + reg = <0xa000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + }; + + pm8916_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8916_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8916_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100 0x100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + usb_in { + reg = ; + qcom,pre-scaling = <1 10>; + }; + vph_pwr { + reg = ; + qcom,pre-scaling = <1 3>; + }; + die_temp { + reg = ; + }; + ref_625mv { + reg = ; + }; + ref_1250v { + reg = ; + }; + ref_gnd { + reg = ; + }; + ref_vdd { + reg = ; + }; + }; + }; + + usid1: pm8916@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/dts/src/arm64/skeleton.dtsi b/dts/src/arm64/skeleton.dtsi deleted file mode 100644 index 38ead821bb..0000000000 --- a/dts/src/arm64/skeleton.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Skeleton device tree; the bare minimum needed to boot; just include and - * add a compatible value. The bootloader will typically populate the memory - * node. - */ - -/ { - #address-cells = <2>; - #size-cells = <1>; - chosen { }; - aliases { }; - memory { device_type = "memory"; reg = <0 0 0>; }; -}; diff --git a/dts/src/h8300/edosk2674.dts b/dts/src/h8300/edosk2674.dts new file mode 100644 index 0000000000..dfb5c102f8 --- /dev/null +++ b/dts/src/h8300/edosk2674.dts @@ -0,0 +1,107 @@ +/dts-v1/; +/ { + compatible = "renesas,edosk2674"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&h8intc>; + + chosen { + bootargs = "console=ttySC2,38400"; + stdout-path = <&sci2>; + }; + aliases { + serial0 = &sci0; + serial1 = &sci1; + serial2 = &sci2; + }; + + xclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "xtal"; + }; + pllclk: pllclk { + compatible = "renesas,h8s2678-pll-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>, <0xfee045 2>; + }; + core_clk: core_clk { + compatible = "renesas,h8300-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>; + renesas,width = <3>; + }; + fclk: fclk { + compatible = "fixed-factor-clock"; + clocks = <&core_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + memory@400000 { + device_type = "memory"; + reg = <0x400000 0x800000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "renesas,h8300"; + clock-frequency = <33333333>; + }; + }; + + h8intc: interrupt-controller@fffe00 { + compatible = "renesas,h8s-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfffe00 24>; + }; + + bsc: memory-controller@fffec0 { + compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; + reg = <0xfffec0 24>; + }; + + tpu: timer@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + timer8: timer@ffffb0 { + compatible = "renesas,8bit-timer"; + reg = <0xffffb0 10>; + interrupts = <72 0>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + sci0: serial@ffff78 { + compatible = "renesas,sci"; + reg = <0xffff78 8>; + interrupts = <88 0>, <89 0>, <90 0>, <91 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; + sci1: serial@ffff80 { + compatible = "renesas,sci"; + reg = <0xffff80 8>; + interrupts = <92 0>, <93 0>, <94 0>, <95 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; + sci2: serial@ffff88 { + compatible = "renesas,sci"; + reg = <0xffff88 8>; + interrupts = <96 0>, <97 0>, <98 0>, <99 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; +}; diff --git a/dts/src/h8300/h8300h_sim.dts b/dts/src/h8300/h8300h_sim.dts new file mode 100644 index 0000000000..545bfb57af --- /dev/null +++ b/dts/src/h8300/h8300h_sim.dts @@ -0,0 +1,96 @@ +/dts-v1/; +/ { + compatible = "gnu,gdbsim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&h8intc>; + + chosen { + bootargs = "earlyprintk=h8300-sim"; + stdout-path = <&sci0>; + }; + aliases { + serial0 = &sci0; + serial1 = &sci1; + }; + + xclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + clock-output-names = "xtal"; + }; + core_clk: core_clk { + compatible = "renesas,h8300-div-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee01b 2>; + renesas,width = <2>; + }; + fclk: fclk { + compatible = "fixed-factor-clock"; + clocks = <&core_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + memory@400000 { + device_type = "memory"; + reg = <0x400000 0x400000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "renesas,h8300"; + clock-frequency = <20000000>; + }; + }; + + h8intc: interrupt-controller@fee012 { + compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfee012 7>; + }; + + bsc: memory-controller@fee01e { + compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; + reg = <0xfee01e 8>; + }; + + timer8: timer@ffff80 { + compatible = "renesas,8bit-timer"; + reg = <0xffff80 10>; + interrupts = <36 0>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + timer16: timer@ffff68 { + compatible = "renesas,16bit-timer"; + reg = <0xffff68 8>, <0xffff60 8>; + interrupts = <24 0>; + renesas,channel = <0>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + sci0: serial@ffffb0 { + compatible = "renesas,sci"; + reg = <0xffffb0 8>; + interrupts = <52 0>, <53 0>, <54 0>, <55 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; + + sci1: serial@ffffb8 { + compatible = "renesas,sci"; + reg = <0xffffb8 8>; + interrupts = <56 0>, <57 0>, <58 0>, <59 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; +}; diff --git a/dts/src/h8300/h8s_sim.dts b/dts/src/h8300/h8s_sim.dts new file mode 100644 index 0000000000..bcedba5a3c --- /dev/null +++ b/dts/src/h8300/h8s_sim.dts @@ -0,0 +1,99 @@ +/dts-v1/; +/ { + compatible = "gnu,gdbsim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&h8intc>; + + chosen { + bootargs = "earlyprintk=h8300-sim"; + stdout-path = <&sci0>; + }; + aliases { + serial0 = &sci0; + serial1 = &sci1; + }; + + xclk: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "xtal"; + }; + pllclk: pllclk { + compatible = "renesas,h8s2678-pll-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>, <0xfee045 2>; + }; + core_clk: core_clk { + compatible = "renesas,h8300-div-clock"; + clocks = <&pllclk>; + #clock-cells = <0>; + reg = <0xfee03b 2>; + renesas,width = <3>; + }; + fclk: fclk { + compatible = "fixed-factor-clock"; + clocks = <&core_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + memory@400000 { + device_type = "memory"; + reg = <0x400000 0x800000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "renesas,h8300"; + clock-frequency = <33333333>; + }; + }; + + h8intc: interrupt-controller@fffe00 { + compatible = "renesas,h8s-intc", "renesas,h8300-intc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xfffe00 24>; + }; + + bsc: memory-controller@fffec0 { + compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; + reg = <0xfffec0 24>; + }; + + tpu: timer@ffffe0 { + compatible = "renesas,tpu"; + reg = <0xffffe0 16>, <0xfffff0 12>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + timer8: timer@ffffb0 { + compatible = "renesas,8bit-timer"; + reg = <0xffffb0 10>; + interrupts = <72 0>; + clocks = <&fclk>; + clock-names = "fck"; + }; + + sci0: serial@ffff78 { + compatible = "renesas,sci"; + reg = <0xffff78 8>; + interrupts = <88 0>, <89 0>, <90 0>, <91 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; + sci1: serial@ffff80 { + compatible = "renesas,sci"; + reg = <0xffff80 8>; + interrupts = <92 0>, <93 0>, <94 0>, <95 0>; + clocks = <&fclk>; + clock-names = "sci_ick"; + }; +}; diff --git a/dts/src/mips/brcm/bcm7346.dtsi b/dts/src/mips/brcm/bcm7346.dtsi index 1f30728a31..d817bb46b9 100644 --- a/dts/src/mips/brcm/bcm7346.dtsi +++ b/dts/src/mips/brcm/bcm7346.dtsi @@ -24,6 +24,8 @@ aliases { uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -118,6 +120,30 @@ status = "disabled"; }; + uart1: serial@406940 { + compatible = "ns16550a"; + reg = <0x406940 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <65>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406980 { + compatible = "ns16550a"; + reg = <0x406980 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <66>; + clocks = <&uart_clk>; + status = "disabled"; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/dts/src/mips/brcm/bcm7358.dtsi b/dts/src/mips/brcm/bcm7358.dtsi index 2c2aa9368f..277a90adc1 100644 --- a/dts/src/mips/brcm/bcm7358.dtsi +++ b/dts/src/mips/brcm/bcm7358.dtsi @@ -18,6 +18,8 @@ aliases { uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -112,6 +114,30 @@ status = "disabled"; }; + uart1: serial@406840 { + compatible = "ns16550a"; + reg = <0x406840 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <62>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406880 { + compatible = "ns16550a"; + reg = <0x406880 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <63>; + clocks = <&uart_clk>; + status = "disabled"; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/dts/src/mips/brcm/bcm7360.dtsi b/dts/src/mips/brcm/bcm7360.dtsi index f23b0aed27..9e1e571ba3 100644 --- a/dts/src/mips/brcm/bcm7360.dtsi +++ b/dts/src/mips/brcm/bcm7360.dtsi @@ -18,6 +18,8 @@ aliases { uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -112,6 +114,30 @@ status = "disabled"; }; + uart1: serial@406840 { + compatible = "ns16550a"; + reg = <0x406840 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <62>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406880 { + compatible = "ns16550a"; + reg = <0x406880 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <63>; + clocks = <&uart_clk>; + status = "disabled"; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/dts/src/mips/brcm/bcm7362.dtsi b/dts/src/mips/brcm/bcm7362.dtsi index da99db665b..6e65db86fc 100644 --- a/dts/src/mips/brcm/bcm7362.dtsi +++ b/dts/src/mips/brcm/bcm7362.dtsi @@ -24,6 +24,8 @@ aliases { uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -118,6 +120,30 @@ status = "disabled"; }; + uart1: serial@406840 { + compatible = "ns16550a"; + reg = <0x406840 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <62>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406880 { + compatible = "ns16550a"; + reg = <0x406880 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <63>; + clocks = <&uart_clk>; + status = "disabled"; + }; + enet0: ethernet@430000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/dts/src/mips/brcm/bcm7435.dtsi b/dts/src/mips/brcm/bcm7435.dtsi new file mode 100644 index 0000000000..8b9432cc06 --- /dev/null +++ b/dts/src/mips/brcm/bcm7435.dtsi @@ -0,0 +1,239 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm7435"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <163125000>; + + cpu@0 { + compatible = "brcm,bmips5200"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips5200"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "brcm,bmips5200"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "brcm,bmips5200"; + device_type = "cpu"; + reg = <3>; + }; + }; + + aliases { + uart0 = &uart0; + }; + + cpu_intc: cpu_intc { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + clocks { + uart_clk: uart_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <81000000>; + }; + }; + + rdb { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges = <0 0x10000000 0x01000000>; + + periph_intc: periph_intc@41b500 { + compatible = "brcm,bcm7038-l1-intc"; + reg = <0x41b500 0x40>, <0x41b600 0x40>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + sun_l2_intc: sun_l2_intc@403000 { + compatible = "brcm,l2-intc"; + reg = <0x403000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&periph_intc>; + interrupts = <52>; + }; + + gisb-arb@400000 { + compatible = "brcm,bcm7400-gisb-arb"; + reg = <0x400000 0xdc>; + native-endian; + interrupt-parent = <&sun_l2_intc>; + interrupts = <0>, <2>; + brcm,gisb-arb-master-mask = <0xf77f>; + brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0", + "pcie_0", "bsp_0", + "rdc_0", "raaga_0", + "avd_1", "jtag_0", + "svd_0", "vice_0", + "vice_1", "raaga_1", + "scpu"; + }; + + upg_irq0_intc: upg_irq0_intc@406780 { + compatible = "brcm,bcm7120-l2-intc"; + reg = <0x406780 0x8>; + + brcm,int-map-mask = <0x44>; + brcm,int-fwd-mask = <0x70000>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&periph_intc>; + interrupts = <60>; + }; + + sun_top_ctrl: syscon@404000 { + compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; + reg = <0x404000 0x51c>; + little-endian; + }; + + reboot { + compatible = "brcm,brcmstb-reboot"; + syscon = <&sun_top_ctrl 0x304 0x308>; + }; + + uart0: serial@406b00 { + compatible = "ns16550a"; + reg = <0x406b00 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <66>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + enet0: ethernet@b80000 { + phy-mode = "internal"; + phy-handle = <&phy1>; + mac-address = [ 00 10 18 36 23 1a ]; + compatible = "brcm,genet-v3"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0xb80000 0x11c88>; + interrupts = <17>, <18>; + interrupt-parent = <&periph_intc>; + status = "disabled"; + + mdio@e14 { + compatible = "brcm,genet-mdio-v3"; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0xe14 0x8>; + + phy1: ethernet-phy@1 { + max-speed = <100>; + reg = <0x1>; + compatible = "brcm,40nm-ephy", + "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + ehci0: usb@480300 { + compatible = "brcm,bcm7435-ehci", "generic-ehci"; + reg = <0x480300 0x100>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <70>; + status = "disabled"; + }; + + ohci0: usb@480400 { + compatible = "brcm,bcm7435-ohci", "generic-ohci"; + reg = <0x480400 0x100>; + native-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <72>; + status = "disabled"; + }; + + ehci1: usb@480500 { + compatible = "brcm,bcm7435-ehci", "generic-ehci"; + reg = <0x480500 0x100>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <71>; + status = "disabled"; + }; + + ohci1: usb@480600 { + compatible = "brcm,bcm7435-ohci", "generic-ohci"; + reg = <0x480600 0x100>; + native-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <73>; + status = "disabled"; + }; + + ehci2: usb@490300 { + compatible = "brcm,bcm7435-ehci", "generic-ehci"; + reg = <0x490300 0x100>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <75>; + status = "disabled"; + }; + + ohci2: usb@490400 { + compatible = "brcm,bcm7435-ohci", "generic-ohci"; + reg = <0x490400 0x100>; + native-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <77>; + status = "disabled"; + }; + + ehci3: usb@490500 { + compatible = "brcm,bcm7435-ehci", "generic-ehci"; + reg = <0x490500 0x100>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <76>; + status = "disabled"; + }; + + ohci3: usb@490600 { + compatible = "brcm,bcm7435-ohci", "generic-ohci"; + reg = <0x490600 0x100>; + native-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <78>; + status = "disabled"; + }; + }; +}; diff --git a/dts/src/mips/brcm/bcm97346dbsmb.dts b/dts/src/mips/brcm/bcm97346dbsmb.dts index 70f196d89d..3fe0445b9d 100644 --- a/dts/src/mips/brcm/bcm97346dbsmb.dts +++ b/dts/src/mips/brcm/bcm97346dbsmb.dts @@ -21,6 +21,14 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + &enet0 { status = "okay"; }; diff --git a/dts/src/mips/brcm/bcm97358svmb.dts b/dts/src/mips/brcm/bcm97358svmb.dts index d18e6d9477..a8dc01e303 100644 --- a/dts/src/mips/brcm/bcm97358svmb.dts +++ b/dts/src/mips/brcm/bcm97358svmb.dts @@ -21,6 +21,14 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + &enet0 { status = "okay"; }; diff --git a/dts/src/mips/brcm/bcm97360svmb.dts b/dts/src/mips/brcm/bcm97360svmb.dts index 4fe5155001..eee8b0e326 100644 --- a/dts/src/mips/brcm/bcm97360svmb.dts +++ b/dts/src/mips/brcm/bcm97360svmb.dts @@ -21,6 +21,14 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + &enet0 { status = "okay"; }; diff --git a/dts/src/mips/brcm/bcm97362svmb.dts b/dts/src/mips/brcm/bcm97362svmb.dts index b7b88e5dc9..739c2ef566 100644 --- a/dts/src/mips/brcm/bcm97362svmb.dts +++ b/dts/src/mips/brcm/bcm97362svmb.dts @@ -21,6 +21,14 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + &enet0 { status = "okay"; }; diff --git a/dts/src/mips/brcm/bcm97435svmb.dts b/dts/src/mips/brcm/bcm97435svmb.dts new file mode 100644 index 0000000000..1df0881835 --- /dev/null +++ b/dts/src/mips/brcm/bcm97435svmb.dts @@ -0,0 +1,60 @@ +/dts-v1/; + +/include/ "bcm7435.dtsi" + +/ { + compatible = "brcm,bcm97435svmb", "brcm,bcm7435"; + model = "Broadcom BCM97435SVMB"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>, + <0x20000000 0x30000000>, + <0x90000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200 maxcpus=1"; + stdout-path = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; + +&enet0 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts new file mode 100644 index 0000000000..9fcb9e7d1f --- /dev/null +++ b/dts/src/mips/ingenic/ci20.dts @@ -0,0 +1,44 @@ +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + compatible = "img,ci20", "ingenic,jz4780"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = &uart4; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000 + 0x30000000 0x30000000>; + }; +}; + +&ext { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; diff --git a/dts/src/mips/ingenic/jz4740.dtsi b/dts/src/mips/ingenic/jz4740.dtsi new file mode 100644 index 0000000000..8b2437cd01 --- /dev/null +++ b/dts/src/mips/ingenic/jz4740.dtsi @@ -0,0 +1,68 @@ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4740"; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + rtc: rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: jz4740-cgu@10000000 { + compatible = "ingenic,jz4740-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&rtc>; + clock-names = "ext", "rtc"; + + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10030000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <9>; + + clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; + clock-names = "baud", "module"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4740-uart"; + reg = <0x10031000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + clocks = <&ext>, <&cgu JZ4740_CLK_UART1>; + clock-names = "baud", "module"; + }; +}; diff --git a/dts/src/mips/ingenic/jz4780.dtsi b/dts/src/mips/ingenic/jz4780.dtsi new file mode 100644 index 0000000000..65389f6027 --- /dev/null +++ b/dts/src/mips/ingenic/jz4780.dtsi @@ -0,0 +1,111 @@ +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4780-intc"; + reg = <0x10001000 0x50>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + rtc: rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: jz4780-cgu@10000000 { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&rtc>; + clock-names = "ext", "rtc"; + + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10030000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <51>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10031000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <50>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart3: serial@10033000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10033000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <48>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart4: serial@10034000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10034000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <34>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; + clock-names = "baud", "module"; + + status = "disabled"; + }; +}; diff --git a/dts/src/mips/ingenic/qi_lb60.dts b/dts/src/mips/ingenic/qi_lb60.dts new file mode 100644 index 0000000000..2414d63ae8 --- /dev/null +++ b/dts/src/mips/ingenic/qi_lb60.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "jz4740.dtsi" + +/ { + compatible = "qi,lb60", "ingenic,jz4740"; + + chosen { + stdout-path = &uart0; + }; +}; + +&ext { + clock-frequency = <12000000>; +}; diff --git a/dts/src/mips/mti/malta.dts b/dts/src/mips/mti/malta.dts new file mode 100644 index 0000000000..c678115f5b --- /dev/null +++ b/dts/src/mips/mti/malta.dts @@ -0,0 +1,7 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,malta"; +}; diff --git a/dts/src/mips/qca/ar9132.dtsi b/dts/src/mips/qca/ar9132.dtsi new file mode 100644 index 0000000000..4759cff814 --- /dev/null +++ b/dts/src/mips/qca/ar9132.dtsi @@ -0,0 +1,133 @@ +/ { + compatible = "qca,ar9132"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, + <&ddr_ctrl 0>, <&ddr_ctrl 1>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&cpuintc>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&miscintc>; + + ddr_ctrl: memory-controller@18000000 { + compatible = "qca,ar9132-ddr-controller", + "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + uart@18020000 { + compatible = "ns8250"; + reg = <0x18020000 0x20>; + interrupts = <3>; + + clocks = <&pll 2>; + clock-names = "uart"; + + reg-io-width = <4>; + reg-shift = <2>; + no-loopback-test; + + status = "disabled"; + }; + + gpio: gpio@18040000 { + compatible = "qca,ar9132-gpio", + "qca,ar7100-gpio"; + reg = <0x18040000 0x30>; + interrupts = <2>; + + ngpios = <22>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pll: pll-controller@18050000 { + compatible = "qca,ar9132-ppl", + "qca,ar9130-pll"; + reg = <0x18050000 0x20>; + + clock-names = "ref"; + /* The board must provides the ref clock */ + + #clock-cells = <1>; + clock-output-names = "cpu", "ddr", "ahb"; + }; + + wdt@18060008 { + compatible = "qca,ar7130-wdt"; + reg = <0x18060008 0x8>; + + interrupts = <4>; + + clocks = <&pll 2>; + clock-names = "wdt"; + }; + + miscintc: interrupt-controller@18060010 { + compatible = "qca,ar9132-misc-intc", + "qca,ar7100-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + clocks = <&pll 2>; + clock-names = "ahb"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts b/dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts new file mode 100644 index 0000000000..003015ab34 --- /dev/null +++ b/dts/src/mips/qca/ar9132_tl_wr1043nd_v1.dts @@ -0,0 +1,112 @@ +/dts-v1/; + +#include +#include + +#include "ar9132.dtsi" + +/ { + compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132"; + model = "TP-Link TL-WR1043ND Version 1"; + + alias { + serial0 = "/ahb/apb/uart@18020000"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + extosc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + ahb { + apb { + uart@18020000 { + status = "okay"; + }; + + pll-controller@18050000 { + clocks = <&extosc>; + }; + }; + + spi@1f000000 { + status = "okay"; + num-cs = <1>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25sl064a"; + reg = <0>; + spi-max-frequency = <25000000>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + }; + + partition@1 { + label = "firmware"; + reg = <0x020000 0x7D0000>; + }; + + partition@2 { + label = "art"; + reg = <0x7F0000 0x010000>; + read-only; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + + poll-interval = <20>; + button@0 { + label = "reset"; + linux,code = ; + gpios = <&gpio 3 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + button@1 { + label = "qss"; + linux,code = ; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "tp-link:green:usb"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "tp-link:green:system"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led@2 { + label = "tp-link:green:qss"; + gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + }; + + led@3 { + label = "tp-link:green:wlan"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/dts/src/powerpc/b4qds.dtsi b/dts/src/powerpc/b4qds.dtsi index 24ed80dc21..559d00657f 100644 --- a/dts/src/powerpc/b4qds.dtsi +++ b/dts/src/powerpc/b4qds.dtsi @@ -106,6 +106,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -116,6 +124,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/fsl/b4420si-post.dtsi b/dts/src/powerpc/fsl/b4420si-post.dtsi index 86161ae6c9..1ea8602e43 100644 --- a/dts/src/powerpc/fsl/b4420si-post.dtsi +++ b/dts/src/powerpc/fsl/b4420si-post.dtsi @@ -80,20 +80,9 @@ compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; }; -/include/ "qoriq-clockgen2.dtsi" global-utilities@e1000 { - compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0"; - - mux0: mux0@0 { - #clock-cells = <0>; - reg = <0x0 0x4>; - compatible = "fsl,qoriq-core-mux-2.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, - <&pll1 0>, <&pll1 1>, <&pll1 2>; - clock-names = "pll0", "pll0-div2", "pll0-div4", - "pll1", "pll1-div2", "pll1-div4"; - clock-output-names = "cmux0"; - }; + compatible = "fsl,b4420-clockgen", "fsl,b4-clockgen", + "fsl,qoriq-clockgen-2.0"; }; rcpm: global-utilities@e2000 { diff --git a/dts/src/powerpc/fsl/b4860si-post.dtsi b/dts/src/powerpc/fsl/b4860si-post.dtsi index f35e9e0a54..9ba904be39 100644 --- a/dts/src/powerpc/fsl/b4860si-post.dtsi +++ b/dts/src/powerpc/fsl/b4860si-post.dtsi @@ -167,6 +167,75 @@ }; }; +&qportals { + qportal14: qman-portal@38000 { + compatible = "fsl,qman-portal"; + reg = <0x38000 0x4000>, <0x100e000 0x1000>; + interrupts = <132 0x2 0 0>; + cell-index = <0xe>; + }; + qportal15: qman-portal@3c000 { + compatible = "fsl,qman-portal"; + reg = <0x3c000 0x4000>, <0x100f000 0x1000>; + interrupts = <134 0x2 0 0>; + cell-index = <0xf>; + }; + qportal16: qman-portal@40000 { + compatible = "fsl,qman-portal"; + reg = <0x40000 0x4000>, <0x1010000 0x1000>; + interrupts = <136 0x2 0 0>; + cell-index = <0x10>; + }; + qportal17: qman-portal@44000 { + compatible = "fsl,qman-portal"; + reg = <0x44000 0x4000>, <0x1011000 0x1000>; + interrupts = <138 0x2 0 0>; + cell-index = <0x11>; + }; + qportal18: qman-portal@48000 { + compatible = "fsl,qman-portal"; + reg = <0x48000 0x4000>, <0x1012000 0x1000>; + interrupts = <140 0x2 0 0>; + cell-index = <0x12>; + }; + qportal19: qman-portal@4c000 { + compatible = "fsl,qman-portal"; + reg = <0x4c000 0x4000>, <0x1013000 0x1000>; + interrupts = <142 0x2 0 0>; + cell-index = <0x13>; + }; + qportal20: qman-portal@50000 { + compatible = "fsl,qman-portal"; + reg = <0x50000 0x4000>, <0x1014000 0x1000>; + interrupts = <144 0x2 0 0>; + cell-index = <0x14>; + }; + qportal21: qman-portal@54000 { + compatible = "fsl,qman-portal"; + reg = <0x54000 0x4000>, <0x1015000 0x1000>; + interrupts = <146 0x2 0 0>; + cell-index = <0x15>; + }; + qportal22: qman-portal@58000 { + compatible = "fsl,qman-portal"; + reg = <0x58000 0x4000>, <0x1016000 0x1000>; + interrupts = <148 0x2 0 0>; + cell-index = <0x16>; + }; + qportal23: qman-portal@5c000 { + compatible = "fsl,qman-portal"; + reg = <0x5c000 0x4000>, <0x1017000 0x1000>; + interrupts = <150 0x2 0 0>; + cell-index = <0x17>; + }; + qportal24: qman-portal@60000 { + compatible = "fsl,qman-portal"; + reg = <0x60000 0x4000>, <0x1018000 0x1000>; + interrupts = <152 0x2 0 0>; + cell-index = <0x18>; + }; +}; + &soc { ddr2: memory-controller@9000 { compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; @@ -182,20 +251,9 @@ compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; }; -/include/ "qoriq-clockgen2.dtsi" global-utilities@e1000 { - compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0"; - - mux0: mux0@0 { - #clock-cells = <0>; - reg = <0x0 0x4>; - compatible = "fsl,qoriq-core-mux-2.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, - <&pll1 0>, <&pll1 1>, <&pll1 2>; - clock-names = "pll0", "pll0-div2", "pll0-div4", - "pll1", "pll1-div2", "pll1-div4"; - clock-output-names = "cmux0"; - }; + compatible = "fsl,b4860-clockgen", "fsl,b4-clockgen", + "fsl,qoriq-clockgen-2.0"; }; rcpm: global-utilities@e2000 { diff --git a/dts/src/powerpc/fsl/b4si-post.dtsi b/dts/src/powerpc/fsl/b4si-post.dtsi index 73136c0029..603910ac1d 100644 --- a/dts/src/powerpc/fsl/b4si-post.dtsi +++ b/dts/src/powerpc/fsl/b4si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &ifc { #address-cells = <2>; #size-cells = <1>; @@ -210,6 +220,97 @@ }; }; +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; + qportal10: qman-portal@28000 { + compatible = "fsl,qman-portal"; + reg = <0x28000 0x4000>, <0x100a000 0x1000>; + interrupts = <124 0x2 0 0>; + cell-index = <0xa>; + }; + qportal11: qman-portal@2c000 { + compatible = "fsl,qman-portal"; + reg = <0x2c000 0x4000>, <0x100b000 0x1000>; + interrupts = <126 0x2 0 0>; + cell-index = <0xb>; + }; + qportal12: qman-portal@30000 { + compatible = "fsl,qman-portal"; + reg = <0x30000 0x4000>, <0x100c000 0x1000>; + interrupts = <128 0x2 0 0>; + cell-index = <0xc>; + }; + qportal13: qman-portal@34000 { + compatible = "fsl,qman-portal"; + reg = <0x34000 0x4000>, <0x100d000 0x1000>; + interrupts = <130 0x2 0 0>; + cell-index = <0xd>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -296,9 +397,21 @@ fsl,liodn-bits = <12>; }; +/include/ "qoriq-clockgen2.dtsi" clockgen: global-utilities@e1000 { compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0"; reg = <0xe1000 0x1000>; + + mux0: mux0@0 { + #clock-cells = <0>; + reg = <0x0 0x4>; + compatible = "fsl,qoriq-core-mux-2.0"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, + <&pll1 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div4", + "pll1", "pll1-div2", "pll1-div4"; + clock-output-names = "cmux0"; + }; }; rcpm: global-utilities@e2000 { @@ -343,6 +456,11 @@ /include/ "qoriq-duart-1.dtsi" /include/ "qoriq-sec5.3-0.dtsi" +/include/ "qoriq-qman3.dtsi" + qman: qman@318000 { + interrupts = <16 2 1 28>; + }; + /include/ "qoriq-bman1.dtsi" bman: bman@31a000 { interrupts = <16 2 1 29>; diff --git a/dts/src/powerpc/fsl/p1023si-post.dtsi b/dts/src/powerpc/fsl/p1023si-post.dtsi index 7780f21430..da6d3fc6ba 100644 --- a/dts/src/powerpc/fsl/p1023si-post.dtsi +++ b/dts/src/powerpc/fsl/p1023si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10 0>; +}; + &lbc { #address-cells = <2>; #size-cells = <1>; @@ -102,6 +112,31 @@ }; }; +&qportals { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x100000 0x1000>; + interrupts = <29 2 0 0>; + cell-index = <0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x101000 0x1000>; + interrupts = <31 2 0 0>; + cell-index = <1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x102000 0x1000>; + interrupts = <33 2 0 0>; + cell-index = <2>; + }; +}; + &bportals { #address-cells = <1>; #size-cells = <1>; @@ -248,6 +283,14 @@ /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" + qman: qman@88000 { + compatible = "fsl,qman"; + reg = <0x88000 0x1000>; + interrupts = <16 2 0 0>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; + }; + bman: bman@8a000 { compatible = "fsl,bman"; reg = <0x8a000 0x1000>; diff --git a/dts/src/powerpc/fsl/p2041si-post.dtsi b/dts/src/powerpc/fsl/p2041si-post.dtsi index f2feacfd9a..04ad177b6a 100644 --- a/dts/src/powerpc/fsl/p2041si-post.dtsi +++ b/dts/src/powerpc/fsl/p2041si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10 0>; +}; + &lbc { compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus"; interrupts = <25 2 0 0>; @@ -223,6 +233,8 @@ /include/ "qoriq-bman1-portals.dtsi" +/include/ "qoriq-qman1-portals.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; @@ -370,6 +382,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p2041-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu1>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ sdhci,auto-cmd12; @@ -415,5 +428,6 @@ crypto: crypto@300000 { fsl,iommu-parent = <&pamu1>; }; +/include/ "qoriq-qman1.dtsi" /include/ "qoriq-bman1.dtsi" }; diff --git a/dts/src/powerpc/fsl/p3041si-post.dtsi b/dts/src/powerpc/fsl/p3041si-post.dtsi index d6fea37395..2cab18af6d 100644 --- a/dts/src/powerpc/fsl/p3041si-post.dtsi +++ b/dts/src/powerpc/fsl/p3041si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10 0>; +}; + &lbc { compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; interrupts = <25 2 0 0>; @@ -250,6 +260,8 @@ /include/ "qoriq-bman1-portals.dtsi" +/include/ "qoriq-qman1-portals.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; @@ -397,6 +409,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p3041-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu1>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ sdhci,auto-cmd12; @@ -442,5 +455,6 @@ crypto: crypto@300000 { fsl,iommu-parent = <&pamu1>; }; +/include/ "qoriq-qman1.dtsi" /include/ "qoriq-bman1.dtsi" }; diff --git a/dts/src/powerpc/fsl/p4080si-post.dtsi b/dts/src/powerpc/fsl/p4080si-post.dtsi index 89482c9b23..dfc76bc41c 100644 --- a/dts/src/powerpc/fsl/p4080si-post.dtsi +++ b/dts/src/powerpc/fsl/p4080si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10 0>; +}; + &lbc { compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; interrupts = <25 2 0 0>; @@ -250,6 +260,8 @@ /include/ "qoriq-bman1-portals.dtsi" +/include/ "qoriq-qman1-portals.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; @@ -469,6 +481,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p4080-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu1>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ voltage-ranges = <3300 3300>; @@ -498,5 +511,6 @@ crypto: crypto@300000 { fsl,iommu-parent = <&pamu1>; }; +/include/ "qoriq-qman1.dtsi" /include/ "qoriq-bman1.dtsi" }; diff --git a/dts/src/powerpc/fsl/p5020si-post.dtsi b/dts/src/powerpc/fsl/p5020si-post.dtsi index 6e04851e2f..b77923ad72 100644 --- a/dts/src/powerpc/fsl/p5020si-post.dtsi +++ b/dts/src/powerpc/fsl/p5020si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &lbc { compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; interrupts = <25 2 0 0>; @@ -247,6 +257,8 @@ /include/ "qoriq-bman1-portals.dtsi" +/include/ "qoriq-qman1-portals.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; @@ -384,6 +396,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p5020-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu1>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ sdhci,auto-cmd12; @@ -428,6 +441,7 @@ fsl,iommu-parent = <&pamu1>; }; +/include/ "qoriq-qman1.dtsi" /include/ "qoriq-bman1.dtsi" /include/ "qoriq-raid1.0-0.dtsi" diff --git a/dts/src/powerpc/fsl/p5040si-post.dtsi b/dts/src/powerpc/fsl/p5040si-post.dtsi index 5e44dfa1e1..6d214526b8 100644 --- a/dts/src/powerpc/fsl/p5040si-post.dtsi +++ b/dts/src/powerpc/fsl/p5040si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &lbc { compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus"; interrupts = <25 2 0 0>; @@ -202,6 +212,8 @@ /include/ "qoriq-bman1-portals.dtsi" +/include/ "qoriq-qman1-portals.dtsi" + &soc { #address-cells = <1>; #size-cells = <1>; @@ -362,6 +374,7 @@ /include/ "qoriq-esdhc-0.dtsi" sdhc@114000 { + compatible = "fsl,p5040-esdhc", "fsl,esdhc"; fsl,iommu-parent = <&pamu2>; fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ sdhci,auto-cmd12; @@ -407,5 +420,6 @@ fsl,iommu-parent = <&pamu4>; }; +/include/ "qoriq-qman1.dtsi" /include/ "qoriq-bman1.dtsi" }; diff --git a/dts/src/powerpc/fsl/qoriq-qman1-portals.dtsi b/dts/src/powerpc/fsl/qoriq-qman1-portals.dtsi index 05d51acafa..e77e4b4ed5 100644 --- a/dts/src/powerpc/fsl/qoriq-qman1-portals.dtsi +++ b/dts/src/powerpc/fsl/qoriq-qman1-portals.dtsi @@ -41,61 +41,61 @@ compatible = "fsl,qman-portal"; reg = <0x0 0x4000>, <0x100000 0x1000>; interrupts = <104 2 0 0>; - fsl,qman-channel-id = <0x0>; + cell-index = <0x0>; }; qportal1: qman-portal@4000 { compatible = "fsl,qman-portal"; reg = <0x4000 0x4000>, <0x101000 0x1000>; interrupts = <106 2 0 0>; - fsl,qman-channel-id = <1>; + cell-index = <1>; }; qportal2: qman-portal@8000 { compatible = "fsl,qman-portal"; reg = <0x8000 0x4000>, <0x102000 0x1000>; interrupts = <108 2 0 0>; - fsl,qman-channel-id = <2>; + cell-index = <2>; }; qportal3: qman-portal@c000 { compatible = "fsl,qman-portal"; reg = <0xc000 0x4000>, <0x103000 0x1000>; interrupts = <110 2 0 0>; - fsl,qman-channel-id = <3>; + cell-index = <3>; }; qportal4: qman-portal@10000 { compatible = "fsl,qman-portal"; reg = <0x10000 0x4000>, <0x104000 0x1000>; interrupts = <112 2 0 0>; - fsl,qman-channel-id = <4>; + cell-index = <4>; }; qportal5: qman-portal@14000 { compatible = "fsl,qman-portal"; reg = <0x14000 0x4000>, <0x105000 0x1000>; interrupts = <114 2 0 0>; - fsl,qman-channel-id = <5>; + cell-index = <5>; }; qportal6: qman-portal@18000 { compatible = "fsl,qman-portal"; reg = <0x18000 0x4000>, <0x106000 0x1000>; interrupts = <116 2 0 0>; - fsl,qman-channel-id = <6>; + cell-index = <6>; }; qportal7: qman-portal@1c000 { compatible = "fsl,qman-portal"; reg = <0x1c000 0x4000>, <0x107000 0x1000>; interrupts = <118 2 0 0>; - fsl,qman-channel-id = <7>; + cell-index = <7>; }; qportal8: qman-portal@20000 { compatible = "fsl,qman-portal"; reg = <0x20000 0x4000>, <0x108000 0x1000>; interrupts = <120 2 0 0>; - fsl,qman-channel-id = <8>; + cell-index = <8>; }; qportal9: qman-portal@24000 { compatible = "fsl,qman-portal"; reg = <0x24000 0x4000>, <0x109000 0x1000>; interrupts = <122 2 0 0>; - fsl,qman-channel-id = <9>; + cell-index = <9>; }; }; diff --git a/dts/src/powerpc/fsl/t1023si-post.dtsi b/dts/src/powerpc/fsl/t1023si-post.dtsi new file mode 100644 index 0000000000..df1f068a53 --- /dev/null +++ b/dts/src/powerpc/fsl/t1023si-post.dtsi @@ -0,0 +1,330 @@ +/* + * T1023 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,ifc", "simple-bus"; + interrupts = <25 2 0 0>; +}; + +&pci0 { + compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <20 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <20 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 40 1 0 0 + 0000 0 0 2 &mpic 1 1 0 0 + 0000 0 0 3 &mpic 2 1 0 0 + 0000 0 0 4 &mpic 3 1 0 0 + >; + }; +}; + +&pci1 { + compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0 0xff>; + interrupts = <21 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <21 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 41 1 0 0 + 0000 0 0 2 &mpic 5 1 0 0 + 0000 0 0 3 &mpic 6 1 0 0 + 0000 0 0 4 &mpic 7 1 0 0 + >; + }; +}; + +&pci2 { + compatible = "fsl,t1023-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + bus-range = <0x0 0xff>; + interrupts = <22 2 0 0>; + fsl,iommu-parent = <&pamu0>; + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <22 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 42 1 0 0 + 0000 0 0 2 &mpic 9 1 0 0 + 0000 0 0 3 &mpic 10 1 0 0 + 0000 0 0 4 &mpic 11 1 0 0 + >; + }; +}; + +&dcsr { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,dcsr", "simple-bus"; + + dcsr-epu@0 { + compatible = "fsl,t1023-dcsr-epu", "fsl,dcsr-epu"; + interrupts = <52 2 0 0 + 84 2 0 0 + 85 2 0 0>; + reg = <0x0 0x1000>; + }; + dcsr-npc { + compatible = "fsl,t1023-dcsr-cnpc", "fsl,dcsr-cnpc"; + reg = <0x1000 0x1000 0x1002000 0x10000>; + }; + dcsr-nxc@2000 { + compatible = "fsl,dcsr-nxc"; + reg = <0x2000 0x1000>; + }; + dcsr-corenet { + compatible = "fsl,dcsr-corenet"; + reg = <0x8000 0x1000 0x1A000 0x1000>; + }; + dcsr-ocn@11000 { + compatible = "fsl,t1023-dcsr-ocn", "fsl,dcsr-ocn"; + reg = <0x11000 0x1000>; + }; + dcsr-ddr@12000 { + compatible = "fsl,dcsr-ddr"; + dev-handle = <&ddr1>; + reg = <0x12000 0x1000>; + }; + dcsr-nal@18000 { + compatible = "fsl,t1023-dcsr-nal", "fsl,dcsr-nal"; + reg = <0x18000 0x1000>; + }; + dcsr-rcpm@22000 { + compatible = "fsl,t1023-dcsr-rcpm", "fsl,dcsr-rcpm"; + reg = <0x22000 0x1000>; + }; + dcsr-snpc@30000 { + compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x30000 0x1000 0x1022000 0x10000>; + }; + dcsr-snpc@31000 { + compatible = "fsl,t1023-dcsr-snpc", "fsl,dcsr-snpc"; + reg = <0x31000 0x1000 0x1042000 0x10000>; + }; + dcsr-cpu-sb-proxy@100000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu0>; + reg = <0x100000 0x1000 0x101000 0x1000>; + }; + dcsr-cpu-sb-proxy@108000 { + compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; + cpu-handle = <&cpu1>; + reg = <0x108000 0x1000 0x109000 0x1000>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + soc-sram-error { + compatible = "fsl,soc-sram-error"; + interrupts = <16 2 1 29>; + }; + + corenet-law@0 { + compatible = "fsl,corenet-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <16>; + }; + + ddr1: memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v5.0", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; + + cpc: l3-cache-controller@10000 { + compatible = "fsl,t1023-l3-cache-controller", "cache"; + reg = <0x10000 0x1000>; + interrupts = <16 2 1 27>; + }; + + corenet-cf@18000 { + compatible = "fsl,corenet2-cf"; + reg = <0x18000 0x1000>; + interrupts = <16 2 1 31>; + }; + + iommu@20000 { + compatible = "fsl,pamu-v1.0", "fsl,pamu"; + reg = <0x20000 0x1000>; + ranges = <0 0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = < + 24 2 0 0 + 16 2 1 30>; + pamu0: pamu@0 { + reg = <0 0x1000>; + fsl,primary-cache-geometry = <128 1>; + fsl,secondary-cache-geometry = <32 2>; + }; + }; + +/include/ "qoriq-mpic.dtsi" + + guts: global-utilities@e0000 { + compatible = "fsl,t1023-device-config", "fsl,qoriq-device-config-2.0"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + fsl,liodn-bits = <12>; + }; + +/include/ "qoriq-clockgen2.dtsi" + global-utilities@e1000 { + compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0"; + mux0: mux0@0 { + #clock-cells = <0>; + reg = <0x0 4>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>; + clock-names = "pll0_0", "pll0_1"; + clock-output-names = "cmux0"; + }; + mux1: mux1@20 { + #clock-cells = <0>; + reg = <0x20 4>; + compatible = "fsl,core-mux-clock"; + clocks = <&pll0 0>, <&pll0 1>; + clock-names = "pll0_0", "pll0_1"; + clock-output-names = "cmux1"; + }; + }; + + rcpm: global-utilities@e2000 { + compatible = "fsl,t1023-rcpm", "fsl,qoriq-rcpm-2.0"; + reg = <0xe2000 0x1000>; + }; + + sfp: sfp@e8000 { + compatible = "fsl,t1023-sfp"; + reg = <0xe8000 0x1000>; + }; + + serdes: serdes@ea000 { + compatible = "fsl,t1023-serdes"; + reg = <0xea000 0x4000>; + }; + + scfg: global-utilities@fc000 { + compatible = "fsl,t1023-scfg"; + reg = <0xfc000 0x1000>; + }; + +/include/ "elo3-dma-0.dtsi" +/include/ "elo3-dma-1.dtsi" + +/include/ "qoriq-espi-0.dtsi" + spi@110000 { + fsl,espi-num-chipselects = <4>; + }; + +/include/ "qoriq-esdhc-0.dtsi" + sdhc@114000 { + compatible = "fsl,t1023-esdhc", "fsl,esdhc"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */ + sdhci,auto-cmd12; + no-1-8-v; + }; +/include/ "qoriq-i2c-0.dtsi" +/include/ "qoriq-i2c-1.dtsi" +/include/ "qoriq-duart-0.dtsi" +/include/ "qoriq-duart-1.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-usb2-mph-0.dtsi" + usb0: usb@210000 { + compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ + phy_type = "utmi"; + port0; + }; +/include/ "qoriq-usb2-dr-0.dtsi" + usb1: usb@211000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */ + dr_mode = "host"; + phy_type = "utmi"; + }; +/include/ "qoriq-sata2-0.dtsi" + sata@220000 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */ + }; + +/include/ "qoriq-sec5.0-0.dtsi" +}; diff --git a/dts/src/powerpc/fsl/t1024si-post.dtsi b/dts/src/powerpc/fsl/t1024si-post.dtsi new file mode 100644 index 0000000000..95e3af8d76 --- /dev/null +++ b/dts/src/powerpc/fsl/t1024si-post.dtsi @@ -0,0 +1,100 @@ +/* + * T1024 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "t1023si-post.dtsi" + +/ { + aliases { + vga = &display; + display = &display; + }; + + qe:qe@ffe140000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xf 0xfe140000 0x40000>; + reg = <0xf 0xfe140000 0 0x480>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + brg-frequency = <0>; + bus-frequency = <0>; + }; +}; + +&soc { + display:display@180000 { + compatible = "fsl,t1024-diu", "fsl,diu"; + reg = <0x180000 1000>; + interrupts = <74 2 0 0>; + }; +}; + +&qe { + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; +}; diff --git a/dts/src/powerpc/fsl/t102xsi-pre.dtsi b/dts/src/powerpc/fsl/t102xsi-pre.dtsi new file mode 100644 index 0000000000..1f1a9f8474 --- /dev/null +++ b/dts/src/powerpc/fsl/t102xsi-pre.dtsi @@ -0,0 +1,87 @@ +/* + * T1024/T1023 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + aliases { + ccsr = &soc; + dcsr = &dcsr; + + dma0 = &dma0; + dma1 = &dma1; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + usb0 = &usb0; + usb1 = &usb1; + sdhc = &sdhc; + + crypto = &crypto; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + clocks = <&mux0>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + next-level-cache = <&cpc>; + }; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + clocks = <&mux1>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + next-level-cache = <&cpc>; + }; + }; + }; +}; diff --git a/dts/src/powerpc/fsl/t1040si-post.dtsi b/dts/src/powerpc/fsl/t1040si-post.dtsi index 5cc01be5b1..9e9f7e201d 100644 --- a/dts/src/powerpc/fsl/t1040si-post.dtsi +++ b/dts/src/powerpc/fsl/t1040si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &ifc { #address-cells = <2>; #size-cells = <1>; @@ -280,6 +290,73 @@ }; }; +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -463,5 +540,6 @@ fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */ }; /include/ "qoriq-sec5.0-0.dtsi" +/include/ "qoriq-qman3.dtsi" /include/ "qoriq-bman1.dtsi" }; diff --git a/dts/src/powerpc/fsl/t2081si-post.dtsi b/dts/src/powerpc/fsl/t2081si-post.dtsi index 86bdaf6cbd..32c790ae7f 100644 --- a/dts/src/powerpc/fsl/t2081si-post.dtsi +++ b/dts/src/powerpc/fsl/t2081si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &ifc { #address-cells = <2>; #size-cells = <1>; @@ -326,6 +336,121 @@ }; }; +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; + qportal10: qman-portal@28000 { + compatible = "fsl,qman-portal"; + reg = <0x28000 0x4000>, <0x100a000 0x1000>; + interrupts = <124 0x2 0 0>; + cell-index = <0xa>; + }; + qportal11: qman-portal@2c000 { + compatible = "fsl,qman-portal"; + reg = <0x2c000 0x4000>, <0x100b000 0x1000>; + interrupts = <126 0x2 0 0>; + cell-index = <0xb>; + }; + qportal12: qman-portal@30000 { + compatible = "fsl,qman-portal"; + reg = <0x30000 0x4000>, <0x100c000 0x1000>; + interrupts = <128 0x2 0 0>; + cell-index = <0xc>; + }; + qportal13: qman-portal@34000 { + compatible = "fsl,qman-portal"; + reg = <0x34000 0x4000>, <0x100d000 0x1000>; + interrupts = <130 0x2 0 0>; + cell-index = <0xd>; + }; + qportal14: qman-portal@38000 { + compatible = "fsl,qman-portal"; + reg = <0x38000 0x4000>, <0x100e000 0x1000>; + interrupts = <132 0x2 0 0>; + cell-index = <0xe>; + }; + qportal15: qman-portal@3c000 { + compatible = "fsl,qman-portal"; + reg = <0x3c000 0x4000>, <0x100f000 0x1000>; + interrupts = <134 0x2 0 0>; + cell-index = <0xf>; + }; + qportal16: qman-portal@40000 { + compatible = "fsl,qman-portal"; + reg = <0x40000 0x4000>, <0x1010000 0x1000>; + interrupts = <136 0x2 0 0>; + cell-index = <0x10>; + }; + qportal17: qman-portal@44000 { + compatible = "fsl,qman-portal"; + reg = <0x44000 0x4000>, <0x1011000 0x1000>; + interrupts = <138 0x2 0 0>; + cell-index = <0x11>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -417,7 +542,7 @@ compatible = "fsl,qoriq-core-mux-2.0"; clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll1 0>, <&pll1 1>, <&pll1 2>; - clock-names = "pll0", "pll0-div2", "pll1-div4", + clock-names = "pll0", "pll0-div2", "pll0-div4", "pll1", "pll1-div2", "pll1-div4"; clock-output-names = "cmux0"; }; @@ -428,7 +553,7 @@ compatible = "fsl,qoriq-core-mux-2.0"; clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll1 0>, <&pll1 1>, <&pll1 2>; - clock-names = "pll0", "pll0-div2", "pll1-div4", + clock-names = "pll0", "pll0-div2", "pll0-div4", "pll1", "pll1-div2", "pll1-div4"; clock-output-names = "cmux1"; }; @@ -502,6 +627,7 @@ phy_type = "utmi"; }; /include/ "qoriq-sec5.2-0.dtsi" +/include/ "qoriq-qman3.dtsi" /include/ "qoriq-bman1.dtsi" L2_1: l2-cache-controller@c20000 { diff --git a/dts/src/powerpc/fsl/t4240si-post.dtsi b/dts/src/powerpc/fsl/t4240si-post.dtsi index 4d4f25895d..d806360d0f 100644 --- a/dts/src/powerpc/fsl/t4240si-post.dtsi +++ b/dts/src/powerpc/fsl/t4240si-post.dtsi @@ -37,6 +37,16 @@ alloc-ranges = <0 0 0x10000 0>; }; +&qman_fqd { + compatible = "fsl,qman-fqd"; + alloc-ranges = <0 0 0x10000 0>; +}; + +&qman_pfdr { + compatible = "fsl,qman-pfdr"; + alloc-ranges = <0 0 0x10000 0>; +}; + &ifc { #address-cells = <2>; #size-cells = <1>; @@ -556,6 +566,313 @@ }; }; +&qportals { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + + qportal0: qman-portal@0 { + compatible = "fsl,qman-portal"; + reg = <0x0 0x4000>, <0x1000000 0x1000>; + interrupts = <104 0x2 0 0>; + cell-index = <0x0>; + }; + qportal1: qman-portal@4000 { + compatible = "fsl,qman-portal"; + reg = <0x4000 0x4000>, <0x1001000 0x1000>; + interrupts = <106 0x2 0 0>; + cell-index = <0x1>; + }; + qportal2: qman-portal@8000 { + compatible = "fsl,qman-portal"; + reg = <0x8000 0x4000>, <0x1002000 0x1000>; + interrupts = <108 0x2 0 0>; + cell-index = <0x2>; + }; + qportal3: qman-portal@c000 { + compatible = "fsl,qman-portal"; + reg = <0xc000 0x4000>, <0x1003000 0x1000>; + interrupts = <110 0x2 0 0>; + cell-index = <0x3>; + }; + qportal4: qman-portal@10000 { + compatible = "fsl,qman-portal"; + reg = <0x10000 0x4000>, <0x1004000 0x1000>; + interrupts = <112 0x2 0 0>; + cell-index = <0x4>; + }; + qportal5: qman-portal@14000 { + compatible = "fsl,qman-portal"; + reg = <0x14000 0x4000>, <0x1005000 0x1000>; + interrupts = <114 0x2 0 0>; + cell-index = <0x5>; + }; + qportal6: qman-portal@18000 { + compatible = "fsl,qman-portal"; + reg = <0x18000 0x4000>, <0x1006000 0x1000>; + interrupts = <116 0x2 0 0>; + cell-index = <0x6>; + }; + qportal7: qman-portal@1c000 { + compatible = "fsl,qman-portal"; + reg = <0x1c000 0x4000>, <0x1007000 0x1000>; + interrupts = <118 0x2 0 0>; + cell-index = <0x7>; + }; + qportal8: qman-portal@20000 { + compatible = "fsl,qman-portal"; + reg = <0x20000 0x4000>, <0x1008000 0x1000>; + interrupts = <120 0x2 0 0>; + cell-index = <0x8>; + }; + qportal9: qman-portal@24000 { + compatible = "fsl,qman-portal"; + reg = <0x24000 0x4000>, <0x1009000 0x1000>; + interrupts = <122 0x2 0 0>; + cell-index = <0x9>; + }; + qportal10: qman-portal@28000 { + compatible = "fsl,qman-portal"; + reg = <0x28000 0x4000>, <0x100a000 0x1000>; + interrupts = <124 0x2 0 0>; + cell-index = <0xa>; + }; + qportal11: qman-portal@2c000 { + compatible = "fsl,qman-portal"; + reg = <0x2c000 0x4000>, <0x100b000 0x1000>; + interrupts = <126 0x2 0 0>; + cell-index = <0xb>; + }; + qportal12: qman-portal@30000 { + compatible = "fsl,qman-portal"; + reg = <0x30000 0x4000>, <0x100c000 0x1000>; + interrupts = <128 0x2 0 0>; + cell-index = <0xc>; + }; + qportal13: qman-portal@34000 { + compatible = "fsl,qman-portal"; + reg = <0x34000 0x4000>, <0x100d000 0x1000>; + interrupts = <130 0x2 0 0>; + cell-index = <0xd>; + }; + qportal14: qman-portal@38000 { + compatible = "fsl,qman-portal"; + reg = <0x38000 0x4000>, <0x100e000 0x1000>; + interrupts = <132 0x2 0 0>; + cell-index = <0xe>; + }; + qportal15: qman-portal@3c000 { + compatible = "fsl,qman-portal"; + reg = <0x3c000 0x4000>, <0x100f000 0x1000>; + interrupts = <134 0x2 0 0>; + cell-index = <0xf>; + }; + qportal16: qman-portal@40000 { + compatible = "fsl,qman-portal"; + reg = <0x40000 0x4000>, <0x1010000 0x1000>; + interrupts = <136 0x2 0 0>; + cell-index = <0x10>; + }; + qportal17: qman-portal@44000 { + compatible = "fsl,qman-portal"; + reg = <0x44000 0x4000>, <0x1011000 0x1000>; + interrupts = <138 0x2 0 0>; + cell-index = <0x11>; + }; + qportal18: qman-portal@48000 { + compatible = "fsl,qman-portal"; + reg = <0x48000 0x4000>, <0x1012000 0x1000>; + interrupts = <140 0x2 0 0>; + cell-index = <0x12>; + }; + qportal19: qman-portal@4c000 { + compatible = "fsl,qman-portal"; + reg = <0x4c000 0x4000>, <0x1013000 0x1000>; + interrupts = <142 0x2 0 0>; + cell-index = <0x13>; + }; + qportal20: qman-portal@50000 { + compatible = "fsl,qman-portal"; + reg = <0x50000 0x4000>, <0x1014000 0x1000>; + interrupts = <144 0x2 0 0>; + cell-index = <0x14>; + }; + qportal21: qman-portal@54000 { + compatible = "fsl,qman-portal"; + reg = <0x54000 0x4000>, <0x1015000 0x1000>; + interrupts = <146 0x2 0 0>; + cell-index = <0x15>; + }; + qportal22: qman-portal@58000 { + compatible = "fsl,qman-portal"; + reg = <0x58000 0x4000>, <0x1016000 0x1000>; + interrupts = <148 0x2 0 0>; + cell-index = <0x16>; + }; + qportal23: qman-portal@5c000 { + compatible = "fsl,qman-portal"; + reg = <0x5c000 0x4000>, <0x1017000 0x1000>; + interrupts = <150 0x2 0 0>; + cell-index = <0x17>; + }; + qportal24: qman-portal@60000 { + compatible = "fsl,qman-portal"; + reg = <0x60000 0x4000>, <0x1018000 0x1000>; + interrupts = <152 0x2 0 0>; + cell-index = <0x18>; + }; + qportal25: qman-portal@64000 { + compatible = "fsl,qman-portal"; + reg = <0x64000 0x4000>, <0x1019000 0x1000>; + interrupts = <154 0x2 0 0>; + cell-index = <0x19>; + }; + qportal26: qman-portal@68000 { + compatible = "fsl,qman-portal"; + reg = <0x68000 0x4000>, <0x101a000 0x1000>; + interrupts = <156 0x2 0 0>; + cell-index = <0x1a>; + }; + qportal27: qman-portal@6c000 { + compatible = "fsl,qman-portal"; + reg = <0x6c000 0x4000>, <0x101b000 0x1000>; + interrupts = <158 0x2 0 0>; + cell-index = <0x1b>; + }; + qportal28: qman-portal@70000 { + compatible = "fsl,qman-portal"; + reg = <0x70000 0x4000>, <0x101c000 0x1000>; + interrupts = <160 0x2 0 0>; + cell-index = <0x1c>; + }; + qportal29: qman-portal@74000 { + compatible = "fsl,qman-portal"; + reg = <0x74000 0x4000>, <0x101d000 0x1000>; + interrupts = <162 0x2 0 0>; + cell-index = <0x1d>; + }; + qportal30: qman-portal@78000 { + compatible = "fsl,qman-portal"; + reg = <0x78000 0x4000>, <0x101e000 0x1000>; + interrupts = <164 0x2 0 0>; + cell-index = <0x1e>; + }; + qportal31: qman-portal@7c000 { + compatible = "fsl,qman-portal"; + reg = <0x7c000 0x4000>, <0x101f000 0x1000>; + interrupts = <166 0x2 0 0>; + cell-index = <0x1f>; + }; + qportal32: qman-portal@80000 { + compatible = "fsl,qman-portal"; + reg = <0x80000 0x4000>, <0x1020000 0x1000>; + interrupts = <168 0x2 0 0>; + cell-index = <0x20>; + }; + qportal33: qman-portal@84000 { + compatible = "fsl,qman-portal"; + reg = <0x84000 0x4000>, <0x1021000 0x1000>; + interrupts = <170 0x2 0 0>; + cell-index = <0x21>; + }; + qportal34: qman-portal@88000 { + compatible = "fsl,qman-portal"; + reg = <0x88000 0x4000>, <0x1022000 0x1000>; + interrupts = <172 0x2 0 0>; + cell-index = <0x22>; + }; + qportal35: qman-portal@8c000 { + compatible = "fsl,qman-portal"; + reg = <0x8c000 0x4000>, <0x1023000 0x1000>; + interrupts = <174 0x2 0 0>; + cell-index = <0x23>; + }; + qportal36: qman-portal@90000 { + compatible = "fsl,qman-portal"; + reg = <0x90000 0x4000>, <0x1024000 0x1000>; + interrupts = <384 0x2 0 0>; + cell-index = <0x24>; + }; + qportal37: qman-portal@94000 { + compatible = "fsl,qman-portal"; + reg = <0x94000 0x4000>, <0x1025000 0x1000>; + interrupts = <386 0x2 0 0>; + cell-index = <0x25>; + }; + qportal38: qman-portal@98000 { + compatible = "fsl,qman-portal"; + reg = <0x98000 0x4000>, <0x1026000 0x1000>; + interrupts = <388 0x2 0 0>; + cell-index = <0x26>; + }; + qportal39: qman-portal@9c000 { + compatible = "fsl,qman-portal"; + reg = <0x9c000 0x4000>, <0x1027000 0x1000>; + interrupts = <390 0x2 0 0>; + cell-index = <0x27>; + }; + qportal40: qman-portal@a0000 { + compatible = "fsl,qman-portal"; + reg = <0xa0000 0x4000>, <0x1028000 0x1000>; + interrupts = <392 0x2 0 0>; + cell-index = <0x28>; + }; + qportal41: qman-portal@a4000 { + compatible = "fsl,qman-portal"; + reg = <0xa4000 0x4000>, <0x1029000 0x1000>; + interrupts = <394 0x2 0 0>; + cell-index = <0x29>; + }; + qportal42: qman-portal@a8000 { + compatible = "fsl,qman-portal"; + reg = <0xa8000 0x4000>, <0x102a000 0x1000>; + interrupts = <396 0x2 0 0>; + cell-index = <0x2a>; + }; + qportal43: qman-portal@ac000 { + compatible = "fsl,qman-portal"; + reg = <0xac000 0x4000>, <0x102b000 0x1000>; + interrupts = <398 0x2 0 0>; + cell-index = <0x2b>; + }; + qportal44: qman-portal@b0000 { + compatible = "fsl,qman-portal"; + reg = <0xb0000 0x4000>, <0x102c000 0x1000>; + interrupts = <400 0x2 0 0>; + cell-index = <0x2c>; + }; + qportal45: qman-portal@b4000 { + compatible = "fsl,qman-portal"; + reg = <0xb4000 0x4000>, <0x102d000 0x1000>; + interrupts = <402 0x2 0 0>; + cell-index = <0x2d>; + }; + qportal46: qman-portal@b8000 { + compatible = "fsl,qman-portal"; + reg = <0xb8000 0x4000>, <0x102e000 0x1000>; + interrupts = <404 0x2 0 0>; + cell-index = <0x2e>; + }; + qportal47: qman-portal@bc000 { + compatible = "fsl,qman-portal"; + reg = <0xbc000 0x4000>, <0x102f000 0x1000>; + interrupts = <406 0x2 0 0>; + cell-index = <0x2f>; + }; + qportal48: qman-portal@c0000 { + compatible = "fsl,qman-portal"; + reg = <0xc0000 0x4000>, <0x1030000 0x1000>; + interrupts = <408 0x2 0 0>; + cell-index = <0x30>; + }; + qportal49: qman-portal@c4000 { + compatible = "fsl,qman-portal"; + reg = <0xc4000 0x4000>, <0x1031000 0x1000>; + interrupts = <410 0x2 0 0>; + cell-index = <0x31>; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -748,6 +1065,7 @@ /include/ "qoriq-sata2-0.dtsi" /include/ "qoriq-sata2-1.dtsi" /include/ "qoriq-sec5.0-0.dtsi" +/include/ "qoriq-qman3.dtsi" /include/ "qoriq-bman1.dtsi" L2_1: l2-cache-controller@c20000 { diff --git a/dts/src/powerpc/kmcoge4.dts b/dts/src/powerpc/kmcoge4.dts index 97e6d11d1e..48dab6a504 100644 --- a/dts/src/powerpc/kmcoge4.dts +++ b/dts/src/powerpc/kmcoge4.dts @@ -34,6 +34,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -44,6 +52,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/oca4080.dts b/dts/src/powerpc/oca4080.dts index eb76caae11..42796c5b05 100644 --- a/dts/src/powerpc/oca4080.dts +++ b/dts/src/powerpc/oca4080.dts @@ -58,6 +58,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -68,6 +76,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/p1023rdb.dts b/dts/src/powerpc/p1023rdb.dts index 9236e3742a..05a00a4d28 100644 --- a/dts/src/powerpc/p1023rdb.dts +++ b/dts/src/powerpc/p1023rdb.dts @@ -56,6 +56,18 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; + }; + + qportals: qman-portals@ff000000 { + ranges = <0x0 0xf 0xff000000 0x200000>; }; bportals: bman-portals@ff200000 { diff --git a/dts/src/powerpc/p2041rdb.dts b/dts/src/powerpc/p2041rdb.dts index c1e69dc718..d2bb0765bd 100644 --- a/dts/src/powerpc/p2041rdb.dts +++ b/dts/src/powerpc/p2041rdb.dts @@ -54,6 +54,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -64,6 +72,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/p3041ds.dts b/dts/src/powerpc/p3041ds.dts index 2192fe9486..eca6c697cf 100644 --- a/dts/src/powerpc/p3041ds.dts +++ b/dts/src/powerpc/p3041ds.dts @@ -54,6 +54,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -64,6 +72,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/p4080ds.dts b/dts/src/powerpc/p4080ds.dts index fad4416546..4f80c9d02c 100644 --- a/dts/src/powerpc/p4080ds.dts +++ b/dts/src/powerpc/p4080ds.dts @@ -54,6 +54,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -64,6 +72,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/p5020ds.dts b/dts/src/powerpc/p5020ds.dts index 7382636dc5..d0309a8b97 100644 --- a/dts/src/powerpc/p5020ds.dts +++ b/dts/src/powerpc/p5020ds.dts @@ -54,6 +54,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -64,6 +72,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/p5040ds.dts b/dts/src/powerpc/p5040ds.dts index 35dabf5b60..05168236d3 100644 --- a/dts/src/powerpc/p5040ds.dts +++ b/dts/src/powerpc/p5040ds.dts @@ -54,6 +54,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -64,6 +72,10 @@ ranges = <0x0 0xf 0xf4000000 0x200000>; }; + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t1023rdb.dts b/dts/src/powerpc/t1023rdb.dts new file mode 100644 index 0000000000..06b090aba0 --- /dev/null +++ b/dts/src/powerpc/t1023rdb.dts @@ -0,0 +1,151 @@ +/* + * T1023 RDB Device Tree Source + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/t102xsi-pre.dtsi" + +/ { + model = "fsl,T1023RDB"; + compatible = "fsl,T1023RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x08000000 + 1 0 0xf 0xff800000 0x00010000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + }; + + memory { + device_type = "memory"; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01072000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <10000000>; /* input clk */ + }; + }; + + i2c@118000 { + eeprom@50 { + compatible = "st,m24256"; + reg = <0x50>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + interrupts = <0x5 0x1 0 0>; + }; + }; + + i2c@118100 { + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + reg = <0xf 0xfe260000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; +}; + +/include/ "fsl/t1023si-post.dtsi" diff --git a/dts/src/powerpc/t1024qds.dts b/dts/src/powerpc/t1024qds.dts new file mode 100644 index 0000000000..f31fabb383 --- /dev/null +++ b/dts/src/powerpc/t1024qds.dts @@ -0,0 +1,251 @@ +/* + * T1024 QDS Device Tree Source + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/t102xsi-pre.dtsi" + +/ { + model = "fsl,T1024QDS"; + compatible = "fsl,T1024QDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x08000000 + 2 0 0xf 0xff800000 0x00010000 + 3 0 0xf 0xffdf0000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + + board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis"; + reg = <3 0 0x300>; + ranges = <0 3 0 0x300>; + }; + }; + + memory { + device_type = "memory"; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01072000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11"; /* 16MB */ + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040"; /* 512KB */ + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eon,en25s64"; /* 8MB */ + reg = <2>; + spi-max-frequency = <10000000>; + }; + + slic@2 { + compatible = "maxim,ds26522"; + reg = <2>; + spi-max-frequency = <2000000>; + }; + + slic@3 { + compatible = "maxim,ds26522"; + reg = <3>; + spi-max-frequency = <2000000>; + }; + }; + + i2c@118000 { + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7461@4c { + /* Thermal Monitor */ + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + eeprom@55 { + compatible = "atmel,24c02"; + reg = <0x55>; + }; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + }; + }; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = <0x5 0x1 0 0>; + }; + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + reg = <0xf 0xfe260000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; +}; + +/include/ "fsl/t1024si-post.dtsi" diff --git a/dts/src/powerpc/t1024rdb.dts b/dts/src/powerpc/t1024rdb.dts new file mode 100644 index 0000000000..733e723ffe --- /dev/null +++ b/dts/src/powerpc/t1024rdb.dts @@ -0,0 +1,185 @@ +/* + * T1024 RDB Device Tree Source + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/t102xsi-pre.dtsi" + +/ { + model = "fsl,T1024RDB"; + compatible = "fsl,T1024RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + ifc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x2000>; + ranges = <0 0 0xf 0xe8000000 0x08000000 + 2 0 0xf 0xff800000 0x00010000 + 3 0 0xf 0xffdf0000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + + board-control@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,t1024-cpld"; + reg = <3 0 0x300>; + ranges = <0 3 0 0x300>; + bank-width = <1>; + device-width = <1>; + }; + }; + + memory { + device_type = "memory"; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01072000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3"; + reg = <0>; + spi-max-frequency = <10000000>; /* input clk */ + }; + + slic@1 { + compatible = "maxim,ds26522"; + reg = <1>; + spi-max-frequency = <2000000>; + }; + + slic@2 { + compatible = "maxim,ds26522"; + reg = <2>; + spi-max-frequency = <2000000>; + }; + }; + + i2c@118000 { + adt7461@4c { + /* Thermal Monitor */ + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + interrupts = <0x1 0x1 0 0>; + }; + }; + + i2c@118100 { + pca9546@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + pci0: pcie@ffe240000 { + reg = <0xf 0xfe240000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe250000 { + reg = <0xf 0xfe250000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe260000 { + reg = <0xf 0xfe260000 0 0x10000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x10000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; +}; + +/include/ "fsl/t1024si-post.dtsi" diff --git a/dts/src/powerpc/t104xqds.dtsi b/dts/src/powerpc/t104xqds.dtsi index f7e9bfbeef..1498d1e4ae 100644 --- a/dts/src/powerpc/t104xqds.dtsi +++ b/dts/src/powerpc/t104xqds.dtsi @@ -47,6 +47,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; ifc: localbus@ffe124000 { @@ -92,6 +100,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t104xrdb.dtsi b/dts/src/powerpc/t104xrdb.dtsi index 76e07a3f2c..830ea48429 100644 --- a/dts/src/powerpc/t104xrdb.dtsi +++ b/dts/src/powerpc/t104xrdb.dtsi @@ -42,6 +42,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; ifc: localbus@ffe124000 { @@ -83,6 +91,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t208xqds.dtsi b/dts/src/powerpc/t208xqds.dtsi index c42e07f4f6..869f9159b4 100644 --- a/dts/src/powerpc/t208xqds.dtsi +++ b/dts/src/powerpc/t208xqds.dtsi @@ -48,6 +48,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; ifc: localbus@ffe124000 { @@ -93,6 +101,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t208xrdb.dtsi b/dts/src/powerpc/t208xrdb.dtsi index e1463b165d..693d2a8fa0 100644 --- a/dts/src/powerpc/t208xrdb.dtsi +++ b/dts/src/powerpc/t208xrdb.dtsi @@ -48,6 +48,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; ifc: localbus@ffe124000 { @@ -94,6 +102,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t4240qds.dts b/dts/src/powerpc/t4240qds.dts index 6df7776641..93722da10e 100644 --- a/dts/src/powerpc/t4240qds.dts +++ b/dts/src/powerpc/t4240qds.dts @@ -109,6 +109,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -119,6 +127,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; diff --git a/dts/src/powerpc/t4240rdb.dts b/dts/src/powerpc/t4240rdb.dts index 46049cf37f..993eb4b8a4 100644 --- a/dts/src/powerpc/t4240rdb.dts +++ b/dts/src/powerpc/t4240rdb.dts @@ -78,6 +78,14 @@ size = <0 0x1000000>; alignment = <0 0x1000000>; }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; }; dcsr: dcsr@f00000000 { @@ -88,6 +96,10 @@ ranges = <0x0 0xf 0xf4000000 0x2000000>; }; + qportals: qman-portals@ff6000000 { + ranges = <0x0 0xf 0xf6000000 0x2000000>; + }; + soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; -- cgit v1.2.3