From f16050f80b317dbcafa377f0eb78681d7ea3f208 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 21 Sep 2020 14:06:13 +0200 Subject: dts: update to v5.9-rc2 Signed-off-by: Sascha Hauer --- dts/Bindings/clock/imx23-clock.yaml | 2 +- dts/Bindings/clock/imx28-clock.yaml | 2 +- dts/Bindings/gpio/gpio-mxs.yaml | 2 +- dts/Bindings/i2c/i2c-mxs.yaml | 2 +- dts/Bindings/mmc/fsl-imx-esdhc.yaml | 2 +- dts/Bindings/mmc/mxs-mmc.yaml | 2 +- dts/Bindings/net/ethernet-controller.yaml | 3 +- dts/Bindings/net/renesas,ether.yaml | 22 ++++++++---- dts/Bindings/pci/intel-gw-pcie.yaml | 8 +++++ dts/Bindings/pwm/mxs-pwm.yaml | 2 +- dts/Bindings/spi/fsl-imx-cspi.yaml | 2 +- dts/Bindings/spi/spi-fsl-lpspi.yaml | 1 + dts/Bindings/thermal/imx-thermal.yaml | 2 +- dts/Bindings/timer/sifive,clint.yaml | 60 +++++++++++++++++++++++++++++++ dts/Bindings/vendor-prefixes.yaml | 2 +- 15 files changed, 96 insertions(+), 18 deletions(-) create mode 100644 dts/Bindings/timer/sifive,clint.yaml (limited to 'dts') diff --git a/dts/Bindings/clock/imx23-clock.yaml b/dts/Bindings/clock/imx23-clock.yaml index 66cb238a10..ad21899981 100644 --- a/dts/Bindings/clock/imx23-clock.yaml +++ b/dts/Bindings/clock/imx23-clock.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Clock bindings for Freescale i.MX23 maintainers: - - Shawn Guo + - Shawn Guo description: | The clock consumer should specify the desired clock by having the clock diff --git a/dts/Bindings/clock/imx28-clock.yaml b/dts/Bindings/clock/imx28-clock.yaml index 72328d5ca0..f1af110812 100644 --- a/dts/Bindings/clock/imx28-clock.yaml +++ b/dts/Bindings/clock/imx28-clock.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Clock bindings for Freescale i.MX28 maintainers: - - Shawn Guo + - Shawn Guo description: | The clock consumer should specify the desired clock by having the clock diff --git a/dts/Bindings/gpio/gpio-mxs.yaml b/dts/Bindings/gpio/gpio-mxs.yaml index ccf5b50e79..dfa1133f8c 100644 --- a/dts/Bindings/gpio/gpio-mxs.yaml +++ b/dts/Bindings/gpio/gpio-mxs.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MXS GPIO controller maintainers: - - Shawn Guo + - Shawn Guo - Anson Huang description: | diff --git a/dts/Bindings/i2c/i2c-mxs.yaml b/dts/Bindings/i2c/i2c-mxs.yaml index d3134ed775..21ae7bce03 100644 --- a/dts/Bindings/i2c/i2c-mxs.yaml +++ b/dts/Bindings/i2c/i2c-mxs.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MXS Inter IC (I2C) Controller maintainers: - - Shawn Guo + - Shawn Guo properties: compatible: diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml index 75dc1168d7..10b45966f1 100644 --- a/dts/Bindings/mmc/fsl-imx-esdhc.yaml +++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX maintainers: - - Shawn Guo + - Shawn Guo allOf: - $ref: "mmc-controller.yaml" diff --git a/dts/Bindings/mmc/mxs-mmc.yaml b/dts/Bindings/mmc/mxs-mmc.yaml index 1cccc0478d..bec8f8c71f 100644 --- a/dts/Bindings/mmc/mxs-mmc.yaml +++ b/dts/Bindings/mmc/mxs-mmc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MXS MMC controller maintainers: - - Shawn Guo + - Shawn Guo description: | The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller diff --git a/dts/Bindings/net/ethernet-controller.yaml b/dts/Bindings/net/ethernet-controller.yaml index 1c4474036d..fa2baca8c7 100644 --- a/dts/Bindings/net/ethernet-controller.yaml +++ b/dts/Bindings/net/ethernet-controller.yaml @@ -54,7 +54,8 @@ properties: phy-connection-type: description: - Operation mode of the PHY interface + Specifies interface type between the Ethernet device and a physical + layer (PHY) device. enum: # There is not a standard bus between the MAC and the PHY, # something proprietary is being used to embed the PHY in the diff --git a/dts/Bindings/net/renesas,ether.yaml b/dts/Bindings/net/renesas,ether.yaml index 08678af5ed..8ce5ed8a58 100644 --- a/dts/Bindings/net/renesas,ether.yaml +++ b/dts/Bindings/net/renesas,ether.yaml @@ -59,9 +59,15 @@ properties: clocks: maxItems: 1 - pinctrl-0: true + power-domains: + maxItems: 1 + + resets: + maxItems: 1 - pinctrl-names: true + phy-mode: true + + phy-handle: true renesas,no-ether-link: type: boolean @@ -74,6 +80,11 @@ properties: specify when the Ether LINK signal is active-low instead of normal active-high +patternProperties: + "^ethernet-phy@[0-9a-f]$": + type: object + $ref: ethernet-phy.yaml# + required: - compatible - reg @@ -83,7 +94,8 @@ required: - '#address-cells' - '#size-cells' - clocks - - pinctrl-0 + +additionalProperties: false examples: # Lager board @@ -99,8 +111,6 @@ examples: clocks = <&mstp8_clks R8A7790_CLK_ETHER>; phy-mode = "rmii"; phy-handle = <&phy1>; - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; renesas,ether-link-active-low; #address-cells = <1>; #size-cells = <0>; @@ -109,7 +119,5 @@ examples: reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&phy1_pins>; - pinctrl-names = "default"; }; }; diff --git a/dts/Bindings/pci/intel-gw-pcie.yaml b/dts/Bindings/pci/intel-gw-pcie.yaml index 64b2c64ca8..a1e2be737e 100644 --- a/dts/Bindings/pci/intel-gw-pcie.yaml +++ b/dts/Bindings/pci/intel-gw-pcie.yaml @@ -9,6 +9,14 @@ title: PCIe RC controller on Intel Gateway SoCs maintainers: - Dilip Kota +select: + properties: + compatible: + contains: + const: intel,lgm-pcie + required: + - compatible + properties: compatible: items: diff --git a/dts/Bindings/pwm/mxs-pwm.yaml b/dts/Bindings/pwm/mxs-pwm.yaml index da68f4a25d..8740e07606 100644 --- a/dts/Bindings/pwm/mxs-pwm.yaml +++ b/dts/Bindings/pwm/mxs-pwm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MXS PWM controller maintainers: - - Shawn Guo + - Shawn Guo - Anson Huang properties: diff --git a/dts/Bindings/spi/fsl-imx-cspi.yaml b/dts/Bindings/spi/fsl-imx-cspi.yaml index 1b50cedbfb..50df1a40bb 100644 --- a/dts/Bindings/spi/fsl-imx-cspi.yaml +++ b/dts/Bindings/spi/fsl-imx-cspi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX maintainers: - - Shawn Guo + - Shawn Guo allOf: - $ref: "/schemas/spi/spi-controller.yaml#" diff --git a/dts/Bindings/spi/spi-fsl-lpspi.yaml b/dts/Bindings/spi/spi-fsl-lpspi.yaml index 22882e769e..312d8fee9d 100644 --- a/dts/Bindings/spi/spi-fsl-lpspi.yaml +++ b/dts/Bindings/spi/spi-fsl-lpspi.yaml @@ -39,6 +39,7 @@ properties: spi common code does not support use of CS signals discontinuously. i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add this property to re-config the chipselect value in the LPSPI driver. + type: boolean required: - compatible diff --git a/dts/Bindings/thermal/imx-thermal.yaml b/dts/Bindings/thermal/imx-thermal.yaml index aedac16699..16b57f57d1 100644 --- a/dts/Bindings/thermal/imx-thermal.yaml +++ b/dts/Bindings/thermal/imx-thermal.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX Thermal Binding maintainers: - - Shawn Guo + - Shawn Guo - Anson Huang properties: diff --git a/dts/Bindings/timer/sifive,clint.yaml b/dts/Bindings/timer/sifive,clint.yaml new file mode 100644 index 0000000000..2a0e9cd9fb --- /dev/null +++ b/dts/Bindings/timer/sifive,clint.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Core Local Interruptor + +maintainers: + - Palmer Dabbelt + - Anup Patel + +description: + SiFive (and other RISC-V) SOCs include an implementation of the SiFive + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor + interrupts. It directly connects to the timer and inter-processor interrupt + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for CLINT device. + The clock frequency of CLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: sifive,fu540-c000-clint + - const: sifive,clint0 + + description: + Should be "sifive,-clint" and "sifive,clint". + Supported compatible strings are - + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive + CLINT v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x2000000 0x10000>; + }; +... diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml index 2baee2c817..63996ab035 100644 --- a/dts/Bindings/vendor-prefixes.yaml +++ b/dts/Bindings/vendor-prefixes.yaml @@ -993,7 +993,7 @@ patternProperties: "^sst,.*": description: Silicon Storage Technology, Inc. "^sstar,.*": - description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. + description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.) "^st,.*": description: STMicroelectronics -- cgit v1.2.3