From bb2308ddedff72ec5fe3b1aca4f95797ed98ce6f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 3 May 2019 12:15:11 +0200 Subject: ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images TQ has unified SD and eMMC images in their U-Boot. Do the same in barebox aswell. Signed-off-by: Sascha Hauer --- images/Makefile.layerscape | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'images') diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape index 47df3777f0..59f672791b 100644 --- a/images/Makefile.layerscape +++ b/images/Makefile.layerscape @@ -45,15 +45,10 @@ $(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \ $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg $(call if_changed,lspbl_image) -$(obj)/barebox-tqmls1046a-emmc.image: $(obj)/start_tqmls1046a.pblb \ - $(board)/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg \ - $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg - $(call if_changed,lspbl_image) - $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \ $(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \ $(board)/tqmls1046a/tqmls1046a_pbi_qspi.cfg $(call if_changed,lspbl_image) -image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image barebox-tqmls1046a-emmc.image \ +image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \ barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image -- cgit v1.2.3 From 18afb284dc1c355c29c6b6d4368cb63efa834a2a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 9 May 2019 08:54:03 +0200 Subject: ARM: Layerscape: Add QSPI boot support Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer --- arch/arm/mach-layerscape/Makefile | 1 + arch/arm/mach-layerscape/include/mach/xload.h | 2 ++ arch/arm/mach-layerscape/xload-qspi.c | 37 +++++++++++++++++++++++++++ images/Makefile.layerscape | 6 +++++ scripts/pblimage.c | 17 +++++++++++- 5 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-layerscape/xload-qspi.c (limited to 'images') diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile index ad4e2f7af3..4705154fb1 100644 --- a/arch/arm/mach-layerscape/Makefile +++ b/arch/arm/mach-layerscape/Makefile @@ -3,3 +3,4 @@ lwl-y += lowlevel.o errata.o lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o obj-y += icid.o obj-pbl-y += boot.o +pbl-y += xload-qspi.o diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h index fedd36e020..94756ed13d 100644 --- a/arch/arm/mach-layerscape/include/mach/xload.h +++ b/arch/arm/mach-layerscape/include/mach/xload.h @@ -2,5 +2,7 @@ #define __MACH_XLOAD_H int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2); +int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1, + unsigned long r2); #endif /* __MACH_XLOAD_H */ diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c new file mode 100644 index 0000000000..c76780a0e8 --- /dev/null +++ b/arch/arm/mach-layerscape/xload-qspi.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include + +/* + * The offset of the 2nd stage image in the output file. This must match with the + * offset the pblimage tool puts barebox to. + */ +#define BAREBOX_START (128 * 1024) + +int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1, + unsigned long r2) +{ + void *qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR); + void *membase = (void *)LS1046A_DDR_SDRAM_BASE; + void *qspi_mem_base = IOMEM(0x40000000); + void (*barebox)(unsigned long, unsigned long, unsigned long) = membase; + + /* Switch controller into little endian mode */ + out_be32(qspi_reg_base, 0x000f400c); + + memcpy(membase, qspi_mem_base + BAREBOX_START, barebox_image_size); + icache_invalidate(); + + printf("Starting barebox\n"); + + barebox(r0, r1, r2); + + printf("failed\n"); + + return -EIO; +} diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape index 59f672791b..38e6648729 100644 --- a/images/Makefile.layerscape +++ b/images/Makefile.layerscape @@ -14,6 +14,12 @@ quiet_cmd_lspbl_image = LSPBL-IMG $@ $(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) \ -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $< +quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@ + cmd_lspbl_spi_image = $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-rcw-tmp) $(word 2,$^) ; \ + $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-pbi-tmp) $(word 3,$^) ; \ + $(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) -s \ + -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $< + pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl $(obj)/barebox-ls1046ardb-2nd.image: $(obj)/start_ls1046ardb.pblb $(call if_changed,shipped) diff --git a/scripts/pblimage.c b/scripts/pblimage.c index 56256260c8..73c0169ac1 100644 --- a/scripts/pblimage.c +++ b/scripts/pblimage.c @@ -13,6 +13,7 @@ #include #include #include +#include #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) #define PBL_ACS_CONT_CMD 0x81000000 @@ -49,6 +50,7 @@ static int pbl_end; static int image_size; static int out_fd; static int in_fd; +static int spiimage; static uint32_t pbl_cmd_initaddr; static uint32_t pbi_crc_cmd1; @@ -229,6 +231,7 @@ static void add_end_cmd(void) static void pbl_load_image(void) { int size; + uint64_t *buf64 = (void *)mem_buf; /* parse the rcw.cfg file. */ pbl_parser(rcwfile); @@ -245,6 +248,15 @@ static void pbl_load_image(void) add_end_cmd(); + if (spiimage) { + int i; + + pbl_size = roundup(pbl_size, 8); + + for (i = 0; i < pbl_size / 8; i++) + buf64[i] = bswap_64(buf64[i]); + } + size = pbl_size; if (write(out_fd, (const void *)&mem_buf, size) != size) { @@ -338,7 +350,7 @@ int main(int argc, char *argv[]) int opt, ret; off_t pos; - while ((opt = getopt(argc, argv, "i:r:p:o:m:")) != -1) { + while ((opt = getopt(argc, argv, "i:r:p:o:m:s")) != -1) { switch (opt) { case 'i': infile = optarg; @@ -355,6 +367,9 @@ int main(int argc, char *argv[]) case 'm': pbl_end = atoi(optarg); break; + case 's': + spiimage = 1; + break; default: exit(EXIT_FAILURE); } -- cgit v1.2.3 From e29efeb0af9a2b8a602e9ff2f9f4b00945eb3f50 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 9 May 2019 08:59:20 +0200 Subject: ARM: Layerscape: TQMLS1046a: unify pbi files This unifies the two different pbi files. With our approach for QSPI booting differences in the pbi files are not necessary: - We do not do execute in place for QSPI, so we do not need different image execution addresses - Setting up the QSPI clock doesn't hurt even for SD boot Signed-off-by: Sascha Hauer --- arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg | 37 ++++++++++++++++++++++ arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg | 33 ------------------- arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg | 35 -------------------- images/Makefile.layerscape | 4 +-- 4 files changed, 39 insertions(+), 70 deletions(-) create mode 100644 arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg delete mode 100644 arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg delete mode 100644 arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg (limited to 'images') diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg new file mode 100644 index 0000000000..0a04afa770 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg @@ -0,0 +1,37 @@ +#Configure QSPI clock +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009c +0957041c 0000009c +09570420 0000009c +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link (errata A-010477) +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#PEX gen3 equalization preset values (errata A-008851) +894008bc 01000000 +89400154 47474747 +89400158 47474747 +894008bc 00000000 +895008bc 01000000 +89500154 47474747 +89500158 47474747 +895008bc 00000000 +896008bc 01000000 +89600154 47474747 +89600158 47474747 +896008bc 00000000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg deleted file mode 100644 index 32865ca2d0..0000000000 --- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg +++ /dev/null @@ -1,33 +0,0 @@ -#Configure QSPI clock -0957015c 40100000 -#Configure Scratch register -09570600 00000000 -09570604 40010000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009c -0957041c 0000009c -09570420 0000009c -#Serdes SATA -09eb1300 80104e20 -09eb08dc 00502880 -#PEX gen3 link (errata A-010477) -09570158 00000300 -89400890 01048000 -89500890 01048000 -89600890 01048000 -#PEX gen3 equalization preset values (errata A-008851) -894008bc 01000000 -89400154 47474747 -89400158 47474747 -894008bc 00000000 -895008bc 01000000 -89500154 47474747 -89500158 47474747 -895008bc 00000000 -896008bc 01000000 -89600154 47474747 -89600158 47474747 -896008bc 00000000 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg deleted file mode 100644 index 7ac1398123..0000000000 --- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg +++ /dev/null @@ -1,35 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009c -0957041c 0000009c -09570420 0000009c -#Serdes SATA -09eb1300 80104e20 -09eb08dc 00502880 -#PEX gen3 link (errata A-010477) -09570158 00000300 -89400890 01048000 -89500890 01048000 -89600890 01048000 -#PEX gen3 equalization preset values (errata A-008851) -894008bc 01000000 -89400154 47474747 -89400158 47474747 -894008bc 00000000 -895008bc 01000000 -89500154 47474747 -89500158 47474747 -895008bc 00000000 -896008bc 01000000 -89600154 47474747 -89600158 47474747 -896008bc 00000000 -#Alt base register -09570158 00001000 -#flush PBI data -096100c0 000fffff diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape index 38e6648729..0f892aeb62 100644 --- a/images/Makefile.layerscape +++ b/images/Makefile.layerscape @@ -48,12 +48,12 @@ $(obj)/barebox-tqmls1046a-2nd.image: $(obj)/start_tqmls1046a.pblb $(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \ $(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \ - $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg + $(board)/tqmls1046a/tqmls1046a_pbi.cfg $(call if_changed,lspbl_image) $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \ $(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \ - $(board)/tqmls1046a/tqmls1046a_pbi_qspi.cfg + $(board)/tqmls1046a/tqmls1046a_pbi.cfg $(call if_changed,lspbl_image) image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \ -- cgit v1.2.3 From 6a7b4b186a6d6e6c6987f0b2d82800f91609d28d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 9 May 2019 12:48:25 +0200 Subject: ARM: Layerscape: TQMLS1046a: Support booting from QSPI We have to build correct images suitable for QSPI, thus have to call lspbl_spi_image instead of lspbl_image. In lowlevel code call the xload function which detects the bootsource rather than hardcoding SD/MMC. Signed-off-by: Sascha Hauer --- arch/arm/boards/tqmls1046a/lowlevel.c | 2 +- images/Makefile.layerscape | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'images') diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c index 9815925599..2d0223ce89 100644 --- a/arch/arm/boards/tqmls1046a/lowlevel.c +++ b/arch/arm/boards/tqmls1046a/lowlevel.c @@ -257,7 +257,7 @@ static noinline __noreturn void tqmls1046a_r_entry(void) ls1046a_errata_post_ddr(); - ls1046a_esdhc_start_image(0, 0, 0); + ls1046a_xload_start_image(0, 0, 0); pr_err("Booting failed\n"); diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape index 0f892aeb62..d20cc6a37e 100644 --- a/images/Makefile.layerscape +++ b/images/Makefile.layerscape @@ -37,7 +37,7 @@ $(obj)/barebox-ls1046ardb-emmc.image: $(obj)/start_ls1046ardb.pblb \ $(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \ $(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \ $(board)/ls1046ardb/ls1046ardb_pbi.cfg - $(call if_changed,lspbl_image) + $(call if_changed,lspbl_spi_image) image-$(CONFIG_MACH_LS1046ARDB) += barebox-ls1046ardb-sd.image barebox-ls1046ardb-qspi.image \ barebox-ls1046ardb-emmc.image barebox-ls1046ardb-2nd.image @@ -54,7 +54,7 @@ $(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \ $(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \ $(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \ $(board)/tqmls1046a/tqmls1046a_pbi.cfg - $(call if_changed,lspbl_image) + $(call if_changed,lspbl_spi_image) image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \ barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image -- cgit v1.2.3