From 887e2ec9ecf49366a60a49b32b73825804909865 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Sep 2006 11:51:23 +0200 Subject: Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006 --- include/configs/sequoia.h | 431 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 431 insertions(+) create mode 100644 include/configs/sequoia.h (limited to 'include/configs/sequoia.h') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h new file mode 100644 index 0000000000..d3fcc032aa --- /dev/null +++ b/include/configs/sequoia.h @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * sequoia.h - configuration for Sequoia board (PowerPC440EPx) + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_BCSR_BASE 0xc0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#if 0 +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#else +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#endif + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif +#if 0 +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE CFG_NAND_ADDR + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sequoia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/sequoia/uImage\0" \ + "kernel_addr=FE000000\0" \ + "ramdisk_addr=FE180000\0" \ + "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB ) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_NAND 0xD0000000 +#define CFG_CPLD 0xC0000000 + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 3 (NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x03017300 +#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#endif + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x24814580 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit v1.2.3 From d12ae80889568365ecb9e6698322f9771ae76dde Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 12 Sep 2006 20:19:10 +0200 Subject: Add NAND environment support for PPC440EPx Sequoia NAND boot config Patch by Stefan Roese, 12 Sep 2006 --- CHANGELOG | 3 +++ board/amcc/sequoia/u-boot-nand.lds | 8 +++++- common/env_nand.c | 50 +++++++++++++++++++++++++++++++++++++- common/environment.c | 3 ++- include/configs/sequoia.h | 27 ++++++-------------- include/environment.h | 4 +++ nand_spl/nand_boot.c | 3 +-- 7 files changed, 73 insertions(+), 25 deletions(-) (limited to 'include/configs/sequoia.h') diff --git a/CHANGELOG b/CHANGELOG index a6dc762348..9840863bf7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add NAND environment support for PPC440EPx Sequoia NAND boot config + Patch by Stefan Roese, 12 Sep 2006 + * Update NAND boot documentation Patch by Stefan Roese, 12 Sep 2006 diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index c3d3d968fe..cf2e2b5581 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -56,6 +56,12 @@ SECTIONS cpu/ppc4xx/start.o (.text) + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + *(.text) *(.fixup) *(.got1) diff --git a/common/env_nand.c b/common/env_nand.c index 0a05b09a7a..67c4a4e011 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH @@ -76,7 +76,9 @@ env_t *env_ptr = 0; /* local functions */ +#if !defined(ENV_IS_EMBEDDED) static void use_default(void); +#endif DECLARE_GLOBAL_DATA_PTR; @@ -91,11 +93,55 @@ uchar env_get_char_spec (int index) * Mark it OK for now. env_relocate() in env_common.c * will call our relocate function which will does * the real validation. + * + * When using a NAND boot image (like sequoia_nand), the environment + * can be embedded or attached to the U-Boot image in NAND flash. This way + * the SPL loads not only the U-Boot image from NAND but also the + * environment. */ int env_init(void) { +#if defined(ENV_IS_EMBEDDED) + ulong total; + int crc1_ok = 0, crc2_ok = 0; + env_t *tmp_env1, *tmp_env2; + + total = CFG_ENV_SIZE; + + tmp_env1 = env_ptr; + tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE); + + crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); + crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); + + if (!crc1_ok && !crc2_ok) + gd->env_valid = 0; + else if(crc1_ok && !crc2_ok) + gd->env_valid = 1; + else if(!crc1_ok && crc2_ok) + gd->env_valid = 2; + else { + /* both ok - check serial */ + if(tmp_env1->flags == 255 && tmp_env2->flags == 0) + gd->env_valid = 2; + else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) + gd->env_valid = 1; + else if(tmp_env1->flags > tmp_env2->flags) + gd->env_valid = 1; + else if(tmp_env2->flags > tmp_env1->flags) + gd->env_valid = 2; + else /* flags are equal - almost impossible */ + gd->env_valid = 1; + } + + if (gd->env_valid == 1) + env_ptr = tmp_env1; + else if (gd->env_valid == 2) + env_ptr = tmp_env2; +#else /* ENV_IS_EMBEDDED */ gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; +#endif /* ENV_IS_EMBEDDED */ return (0); } @@ -236,6 +282,7 @@ void env_relocate_spec (void) } #endif /* CFG_ENV_OFFSET_REDUND */ +#if !defined(ENV_IS_EMBEDDED) static void use_default() { puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); @@ -253,5 +300,6 @@ static void use_default() gd->env_valid = 1; } +#endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/common/environment.c b/common/environment.c index 81471ce71c..19bdeb0f62 100644 --- a/common/environment.c +++ b/common/environment.c @@ -60,7 +60,8 @@ defined(CONFIG_RRVISION) || \ defined(CONFIG_TRAB) || \ defined(CONFIG_PPCHAMELEONEVB) || \ - defined(CONFIG_M5271EVB)) && \ + defined(CONFIG_M5271EVB) || \ + defined(CONFIG_NAND_U_BOOT)) && \ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ /* XXX - This only works with GNU C */ # define __PPCENV__ __attribute__ ((section(".ppcenv"))) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index d3fcc032aa..639765d599 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -69,14 +69,9 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -#if 0 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#else #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ -#endif #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ @@ -98,18 +93,11 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 /* test-only */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ #endif -#if 0 -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -189,8 +177,12 @@ #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ #ifdef CFG_ENV_IS_IN_NAND -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE) +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) #endif @@ -214,11 +206,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ #define CONFIG_DTT_AD7414 1 /* use AD7414 */ diff --git a/include/environment.h b/include/environment.h index 422f800897..26b07120da 100644 --- a/include/environment.h +++ b/include/environment.h @@ -79,6 +79,10 @@ # ifdef CFG_ENV_OFFSET_REDUND # define CFG_REDUNDAND_ENVIRONMENT # endif +# if defined(CONFIG_NAND_U_BOOT) +/* Use embedded environment in NAND boot versions */ +# define ENV_IS_EMBEDDED 1 +# endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 6e3af13939..21abb09e39 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -166,8 +166,7 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, - CFG_NAND_U_BOOT_SIZE, + ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, (uchar *)CFG_NAND_U_BOOT_DST); /* -- cgit v1.2.3 From 854bc8da75709f13dab4cfa6e9094c0cb49b5c5a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 13 Sep 2006 13:51:58 +0200 Subject: Add support for AMCC Rainier PPX440GRx eval board Patch by Stefan Roese, 13 Sep 2006 --- CHANGELOG | 3 +++ Makefile | 15 +++++++++++++++ board/amcc/sequoia/sequoia.c | 8 ++++++++ cpu/ppc4xx/4xx_enet.c | 2 +- cpu/ppc4xx/vecnum.h | 2 +- include/configs/sequoia.h | 13 ++++++++++++- 6 files changed, 40 insertions(+), 3 deletions(-) (limited to 'include/configs/sequoia.h') diff --git a/CHANGELOG b/CHANGELOG index a896e253a9..0f4b4d561e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -7,6 +7,9 @@ Changes since U-Boot 1.1.4: * Cleanup examples binaries +* Add support for AMCC Rainier PPX440GRx eval board + Patch by Stefan Roese, 13 Sep 2006 + * Add NAND environment support for PPC440EPx Sequoia NAND boot config Patch by Stefan Roese, 12 Sep 2006 diff --git a/Makefile b/Makefile index ccf7f9f88f..f48ca6cebb 100644 --- a/Makefile +++ b/Makefile @@ -1142,6 +1142,21 @@ PPChameleonEVB_HI_33_config: unconfig } @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave +rainier_config: unconfig + @echo "#define CONFIG_RAINIER" > include/config.h + @echo "Configuring for rainier board as subset of sequoia..." + @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc + +rainier_nand_config: unconfig + @echo "#define CONFIG_RAINIER" > include/config.h + @echo "Configuring for rainier board as subset of sequoia..." + @ln -s board/amcc/sequoia/Makefile nand_spl/Makefile + @echo "#define CONFIG_NAND_U_BOOT" >> include/config.h + @echo "Compile NAND boot image for sequoia" + @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc + @echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk + sbc405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405 diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 95734b9c57..a8ba2c0831 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -140,10 +140,12 @@ int misc_init_r(void) { uint pbcr; int size_val = 0; +#ifdef CONFIG_440EPX unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; char *act = getenv("usbact"); +#endif /* * FLASH stuff... @@ -211,6 +213,7 @@ int misc_init_r(void) /* * USB suff... */ +#ifdef CONFIG_440EPX if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -322,6 +325,7 @@ int misc_init_r(void) printf("USB: Device(int phy)\n"); } +#endif /* CONFIG_440EPX */ return 0; } @@ -330,7 +334,11 @@ int checkboard(void) { char *s = getenv("serial#"); +#ifdef CONFIG_440EPX printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); +#else + printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); +#endif if (s != NULL) { puts(", serial# "); puts(s); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5b1c17c351..81d49ffdfe 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -133,7 +133,7 @@ #define BI_PHYMODE_GMII 3 #define BI_PHYMODE_RTBI 4 #define BI_PHYMODE_TBI 5 -#if defined (CONFIG_440EPX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define BI_PHYMODE_SMII 6 #define BI_PHYMODE_MII 7 #endif diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 70e436aab2..685d48bcf6 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,7 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC 0 */ #define VECNUM_U0 0 /* UART 0 */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 639765d599..f67fd9163d 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -31,8 +31,13 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ +/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ +#ifndef CONFIG_RAINIER #define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#else +#define CONFIG_440GRX 1 /* Specific PPC440GRx */ +#endif #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ @@ -272,12 +277,18 @@ #define CONFIG_PHY1_ADDR 1 /* USB */ +#ifdef CONFIG_440EPX #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE +#define CMD_USB CFG_CMD_USB +#else +#define CMD_USB 0 /* no USB on 440GRx */ +#endif /* CONFIG_440EPX */ + /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -301,7 +312,7 @@ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_USB ) + CMD_USB) #define CONFIG_SUPPORT_VFAT -- cgit v1.2.3