Altera SoCFPGA
==============

Alteras SoCFPGA SoCs have a two-stage boot process. The first stage is
known as preloader which loads the second stage bootloader. barebox can act
as both the first and the second stage loader.
In barebox the preloader is called xload, so to build as a first stage loader,
build the ``socfpga-xload_defconfig``; for second stage use the normal
``socfpga_defconfig``.

Bootstrapping
-------------

The supported bootsources are: SD card and QSPI.

Bootsource selection
^^^^^^^^^^^^^^^^^^^^

+--------------+-----------+-----------+
| Board        | BSEL[2:0] | CSEL[1:0] |
+==============+===========+===========+
| Sockit SD    | 0b100     | 0b00      |
+--------------+-----------+-----------+
| Sockit QSPI  | 0b110     | 0b00      |
+--------------+-----------+-----------+
| Socrates SD  | 0b101     | 0b11      |
+--------------+-----------+-----------+
| Socrates QSPI| 0b111     | 0b11      |
+--------------+-----------+-----------+
| SocDK SD     | 0b100     | 0b00      |
+--------------+-----------+-----------+
| SocDK QSPI   | 0b110     | 0b00      |
+--------------+-----------+-----------+

SD card
^^^^^^^

The Boot ROM searches for a partition of type A2 and loads what it finds there.
When barebox is placed in such a partition it will then itself try and mount the
second partition of the SD card, which must be of type FAT32. On this partition
barebox searches for a file called barebox.bin.

To boot barebox on a Terasic SoCkit, the procedure is as follows (sdb1 is the A2 and
sdb2 the FAT32 partition):

.. code-block:: sh

  mount -t fat /dev/sdb2 /mnt
  make socfpga-xload_defconfig
  make
  make socfpga_defconfig
  make

barebox has now generated multiple files in the images directory. So for the SoCkit
proceed with:

.. code-block:: sh

  cat images/barebox-socfpga-sockit-xload.img > /dev/sdb1
  cp images/barebox-socfpga-sockit.img /mnt/barebox.bin
  umount /mnt

For the EBV Socrates use ``images/barebox-socfpga-socrates(-xload).img`` instead.

QSPI
^^^^

The Boot ROM loads the preloader starting from address 0x0 on the QSPI flash.
barebox then searches for a barebox image at the 256K offset and loads it.

The default bootsource is SD card, so to change that to QSPI, you have to:

.. code-block:: sh

  make socfpga-xload_defconfig
  make menuconfig

And then select the options `MTD` and `SPI_CADENCE_QUADSPI`. Now:

.. code-block:: sh

  make
  cat images/barebox-socfpga-<board>-xload.img > /dev/mtd0

For barebox itself, the build step is like for SD card. The resulting image has to be
written to the offset 256K.

Warning! There is a known issue with booting from QSPI and doing Cold/Warm-Resets.
Please consult `Rocketboards <http://rocketboards.org/foswiki/Documentation/SocBoardQspiBoot#Serial_Flash_Challenges>`_
to see how to fix this.


Updating handoff files
----------------------

(Tools needed: Quartus II + SoCEDS)

As barebox uses some of the autogenerated files from Quartus II, every
time Altera makes a new release, there might be some updates to the
handoff files. As these files are split up in the code base and generated
explicitely for some specific U-boot code base, some manual work might be
necessary.

The boardspecific files for `arch/arm/boards/<yourboard>` are:

* iocsr_config_cyclone5.c
* pinmux_config_cyclone5.c -> pinmux_config.c
* pll_config.h
* sdram/sdram_config.h -> sdram_config.h
* sequencer_auto.h
* sequencer_auto_ac_init.c
* sequencer_auto_inst_init.c
* sequencer_defines.h

To update the handoff files, the following procedure is necessary:

1. Regenerate the project with Qsys
2. Load up your project in Quartus II and assemble the design
3. Go to the SoCEDS installation and run
   ``./embedded_command_shell.sh``
4. Now run ``bsp-editor``
5. Create a new BSP
6. Select the directory `hps_isw_handoff/soc_system_hps_0` under the
   preloader settings directory
7. Click ``Ok`` than ``Generate``

Now run the command:

.. code-block:: sh

  scripts/socfpga_import_preloader <SPL_GENERATED_DIR> <ISW_HANDOFF> <BOARD_DIRECTORY>

where `<SPL_GENERATED_DIR>` is the directory where the bsp-editor generated the files,
`<ISW_HANDOFF>` is the directory where Quartus generated the handoff files, and
`<BOARD_DIRECTORY>` is your board directory under `arch/arm/boards`.


Integrating new SDRAM driver
----------------------------

This step must only be executed if the SDRAM driver needs updates. It is not necessary
for adding a new board to barebox.

The following files are generic and belong into the `arch/arm/mach-socfpga` directory
tree:

* sdram_io.h
* sequencer.c as cyclone5-sequencer.c
* sequencer.h as cyclone5-sequencer.h
* sequencer_defines.h
* system.h
* tclrpt.h

To add these files, run:

.. code-block:: sh

  scripts/socfpga_get_sequencer <UBOOT-SRC> scripts/socfpga_sequencer_defines_defaults

where `<UBOOT-SRC>` is the directory where the Altera bsp-editor generated the u-boot
directory. Refer to the Altera documentation for how to use the bsp-editor.