/* * Copyright (C) 2016 NXP Semiconductors * * SPDX-License-Identifier: GPL-2.0 * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage */ soc imx7 loadaddr 0x80000000 dcdofs 0x400 #include wm 32 0x30340004 0x4F400005 /* Clear then set bit30 to ensure exit from DDR retention */ wm 32 0x30360388 0x40000000 wm 32 0x30360384 0x40000000 wm 32 0x30391000 0x00000002 wm 32 MX7_DDRC_MSTR 0x01040001 wm 32 MX7_DDRC_DFIUPD0 0x80400003 wm 32 MX7_DDRC_DFIUPD1 0x00100020 wm 32 MX7_DDRC_DFIUPD2 0x80100004 wm 32 MX7_DDRC_RFSHTMG 0x00400046 wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 wm 32 MX7_DDRC_INIT0 0x00020083 wm 32 MX7_DDRC_INIT1 0x00690000 wm 32 MX7_DDRC_INIT3 0x09300004 wm 32 MX7_DDRC_INIT4 0x04080000 wm 32 MX7_DDRC_INIT5 0x00100004 wm 32 MX7_DDRC_RANKCTL 0x0000033f wm 32 MX7_DDRC_DRAMTMG0 0x09081109 wm 32 MX7_DDRC_DRAMTMG1 0x0007020d wm 32 MX7_DDRC_DRAMTMG2 0x03040407 wm 32 MX7_DDRC_DRAMTMG3 0x00002006 wm 32 MX7_DDRC_DRAMTMG4 0x04020205 wm 32 MX7_DDRC_DRAMTMG5 0x03030202 wm 32 MX7_DDRC_DRAMTMG8 0x00000803 wm 32 MX7_DDRC_ZQCTL0 0x00800020 wm 32 MX7_DDRC_ZQCTL1 0x02000100 wm 32 MX7_DDRC_DFITMG0 0x02098204 wm 32 MX7_DDRC_DFITMG1 0x00030303 wm 32 MX7_DDRC_ADDRMAP0 0x00000016 wm 32 MX7_DDRC_ADDRMAP1 0x00171717 wm 32 MX7_DDRC_ADDRMAP5 0x04040404 wm 32 MX7_DDRC_ADDRMAP6 0x0f040404 wm 32 MX7_DDRC_ODTCFG 0x06000604 wm 32 MX7_DDRC_ODTMAP 0x00000001 wm 32 0x30391000 0x00000000 wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40 wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808 wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808 wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f check 32 until_any_bit_set MX7_DDRC_STAT 0x1