/* SPDX-License-Identifier: GPL-2.0-only */

/*
 * Some defines for PAD setup:
 * Unfortunately we don't have a powerful pre-processor, so we need to
 * define explicit 32-bit hex values.
 */
#define PAD_DSE_48 0x00000028
#define PAD_DSE_40 0x00000030

#define PAD_DIFF_IN_DSE_48 0x00020028
#define PAD_DIFF_IN_DSE_40 0x00020030
#define PAD_DIFF_IN_DSE_34 0x00020038

/* Disable ISB LED ASAP */
wm 32 0x020e04a8 0x000130b0

#define PAD_SDQS PAD_DSE_48
wm 32 0x020e04bc PAD_SDQS /* SDQS0_P */
wm 32 0x020e04c0 PAD_SDQS /* SDQS1_P */
wm 32 0x020e04c4 PAD_SDQS /* SDQS2_P */
wm 32 0x020e04c8 PAD_SDQS /* SDQS3_P */
wm 32 0x020e04cc PAD_SDQS /* SDQS4_P */
wm 32 0x020e04d0 PAD_SDQS /* SDQS5_P */
wm 32 0x020e04d4 PAD_SDQS /* SDQS6_P */
wm 32 0x020e04d8 PAD_SDQS /* SDQS7_P */

#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48
#define PAD_SDCLK    PAD_DIFF_IN_DSE_40
wm 32 0x020e0470 PAD_DQM_CTRL /* DQM0 */
wm 32 0x020e0474 PAD_DQM_CTRL /* DQM1 */
wm 32 0x020e0478 PAD_DQM_CTRL /* DQM2 */
wm 32 0x020e047c PAD_DQM_CTRL /* DQM3 */
wm 32 0x020e0480 PAD_DQM_CTRL /* DQM4 */
wm 32 0x020e0484 PAD_DQM_CTRL /* DQM5 */
wm 32 0x020e0488 PAD_DQM_CTRL /* DQM6 */
wm 32 0x020e048c PAD_DQM_CTRL /* DQM7 */
wm 32 0x020e0464 PAD_DQM_CTRL /* CAS */
wm 32 0x020e0490 PAD_DQM_CTRL /* RAS */
wm 32 0x020e04ac PAD_SDCLK /* SDCLK0_P */
wm 32 0x020e04b0 PAD_SDCLK /* SDCLK1_P */
wm 32 0x020e0494 PAD_DQM_CTRL /* RESET */

/* 0x00003000 = 100k PU */
wm 32 0x020e04a4 0x00003000 /* SDCKE0 */
wm 32 0x020e04a8 0x00003000 /* SDCKE1 */
wm 32 0x020e04a0 0x00000000 /* SDBA2: disable PU */

/* 0x00003030 = PU + 40 Ohm drive */
wm 32 0x020e04b4 0x00003030 /* ODT0 */
wm 32 0x020e04b8 0x00003030 /* ODT1 */

#define PAD_BxDS PAD_DSE_48
wm 32 0x020e0764 PAD_BxDS /* B0DS */
wm 32 0x020e0770 PAD_BxDS /* B1DS */
wm 32 0x020e0778 PAD_BxDS /* B2DS */
wm 32 0x020e077c PAD_BxDS /* B3DS */
wm 32 0x020e0780 PAD_BxDS /* B4DS */
wm 32 0x020e0784 PAD_BxDS /* B5DS */
wm 32 0x020e078c PAD_BxDS /* B6DS */
wm 32 0x020e0748 PAD_BxDS /* B7DS */
wm 32 0x020e074c PAD_DSE_48 /* ADDDS */

wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */
wm 32 0x020e0754 0x00000000 /* DDRPKE disable PU */
wm 32 0x020e0760 0x00020000 /* DDRMODE data */

wm 32 0x020e076c 0x00000030 /* CTLDS 40 Ohm */

wm 32 0x020e0774 0x000c0000 /* DDR_TYPE DDR3 */