/* SPDX-License-Identifier: GPL-2.0-only */

/*
 * Some defines for PAD setup:
 * Unfortunately we don't have a powerful pre-processor, so we need to
 * define explicit 32-bit hex values.
 */

#define PAD_DSE_48 0x00000028
#define PAD_DSE_40 0x00000030

#define PAD_SDQS PAD_DSE_48
wm 32 0x020e0280 PAD_SDQS /* SDQS0_P */
wm 32 0x020e0284 PAD_SDQS /* SDQS1_P */

#define PAD_DQM_CTRL PAD_DSE_48
#define PAD_SDCLK PAD_DSE_48

wm 32 0x020e0244 PAD_DQM_CTRL /* DQM0 */
wm 32 0x020e0248 PAD_DQM_CTRL /* DQM1 */
wm 32 0x020e024c PAD_DQM_CTRL /* RAS */
wm 32 0x020e0250 PAD_DQM_CTRL /* CAS */
wm 32 0x020e027c PAD_SDCLK /* SDCLK0_P */
wm 32 0x020e0288 PAD_DQM_CTRL /* RESET */

wm 32 0x020e0270 0x00000000 /* SDBA2: disable PU */

wm 32 0x020e0260 PAD_DSE_48 /* ODT0 */
wm 32 0x020e0264 PAD_DSE_48 /* ODT1 */

#define PAD_BxDS PAD_DSE_48
wm 32 0x020e0498 PAD_BxDS /* B0DS */
wm 32 0x020e04a4 PAD_BxDS /* B1DS */

wm 32 0x020e0490 PAD_DSE_48  /* ADDDS */

wm 32 0x020e0494 0x00020000 /* DDRMODE_CTL */
wm 32 0x020e04ac 0x00000000 /* DDRPKE disable PU */
wm 32 0x020e04b0 0x00020000 /* DDRMODE data */

wm 32 0x020e04a0 0x00000030 /* CTLDS 40 Ohm */

wm 32 0x020e04b4 0x000c0000 /* DDR_TYPE DDR3 */