/* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. */ #include #include #include #include #include #include #include #include #include #include #include #include static void __udelay(int us) { volatile int i; for (i = 0; i < us * 4; i++); } /* * Driving strength: * 0x30 == 40 Ohm * 0x28 == 48 Ohm */ #define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6SDL_DRIVE_STRENGTH 0x28 /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, .dram_cas = IMX6DQ_DRIVE_STRENGTH, .dram_ras = IMX6DQ_DRIVE_STRENGTH, .dram_reset = IMX6DQ_DRIVE_STRENGTH, .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdba2 = 0x00000000, .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, }; /* configure MX6Q/DUAL mmdc GRP io registers */ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = IMX6DQ_DRIVE_STRENGTH, .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, .grp_ddrmode = 0x00020000, .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, }; /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, .dram_cas = IMX6SDL_DRIVE_STRENGTH, .dram_ras = IMX6SDL_DRIVE_STRENGTH, .dram_reset = IMX6SDL_DRIVE_STRENGTH, .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdba2 = 0x00000000, .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, }; /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_ddr_type = 0x000c0000, .grp_ddrmode_ctl = 0x00020000, .grp_ddrpke = 0x00000000, .grp_addds = IMX6SDL_DRIVE_STRENGTH, .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, .grp_ddrmode = 0x00020000, .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, }; /* H5T04G63AFR-PB */ static struct mx6_ddr3_cfg h5t04g63afr = { .mem_speed = 1600, .density = 4, .width = 16, .banks = 8, .rowaddr = 15, .coladdr = 10, .pagesz = 2, .trcd = 1375, .trcmin = 4875, .trasmin = 3500, }; /* H5TQ2G63DFR-H9 */ static struct mx6_ddr3_cfg h5tq2g63dfr = { .mem_speed = 1333, .density = 2, .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, .pagesz = 2, .trcd = 1350, .trcmin = 4950, .trasmin = 3600, }; static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = { .p0_mpwldectrl0 = 0x001f001f, .p0_mpwldectrl1 = 0x001f001f, .p1_mpwldectrl0 = 0x001f001f, .p1_mpwldectrl1 = 0x001f001f, .p0_mpdgctrl0 = 0x4301030d, .p0_mpdgctrl1 = 0x03020277, .p1_mpdgctrl0 = 0x4300030a, .p1_mpdgctrl1 = 0x02780248, .p0_mprddlctl = 0x4536393b, .p1_mprddlctl = 0x36353441, .p0_mpwrdlctl = 0x41414743, .p1_mpwrdlctl = 0x462f453f, }; /* DDR 64bit 2GB */ static struct mx6_ddr_sysinfo mem_q = { .dsize = 2, .cs1_mirror = 0, .cs_density = 16, .ncs = 1, .bi_on = 1, .rtt_nom = 1, .rtt_wr = 0, .ralat = 5, .walat = 0, .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, }; static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { .p0_mpwldectrl0 = 0x001f001f, .p0_mpwldectrl1 = 0x001f001f, .p1_mpwldectrl0 = 0x001f001f, .p1_mpwldectrl1 = 0x001f001f, .p0_mpdgctrl0 = 0x420e020e, .p0_mpdgctrl1 = 0x02000200, .p1_mpdgctrl0 = 0x42020202, .p1_mpdgctrl1 = 0x01720172, .p0_mprddlctl = 0x494c4f4c, .p1_mprddlctl = 0x4a4c4c49, .p0_mpwrdlctl = 0x3f3f3133, .p1_mpwrdlctl = 0x39373f2e, }; static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = { .p0_mpwldectrl0 = 0x0040003c, .p0_mpwldectrl1 = 0x0032003e, .p0_mpdgctrl0 = 0x42350231, .p0_mpdgctrl1 = 0x021a0218, .p0_mprddlctl = 0x4b4b4e49, .p0_mpwrdlctl = 0x3f3f3035, }; /* DDR 64bit 1GB */ static struct mx6_ddr_sysinfo mem_dl = { .dsize = 2, .cs1_mirror = 0, .cs_density = 8, .ncs = 1, .bi_on = 1, .rtt_nom = 1, .rtt_wr = 0, .ralat = 5, .walat = 0, .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, }; /* DDR 32bit 512MB */ static struct mx6_ddr_sysinfo mem_s = { .dsize = 1, .cs1_mirror = 0, .cs_density = 4, .ncs = 1, .bi_on = 1, .rtt_nom = 1, .rtt_wr = 0, .ralat = 5, .walat = 0, .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, }; static unsigned long wandboard_dram_init(void) { int cpu_type = __imx6_cpu_type(); unsigned long memsize; switch (cpu_type) { case IMX6_CPUTYPE_IMX6S: mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); memsize = SZ_512M; break; case IMX6_CPUTYPE_IMX6DL: mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr); memsize = SZ_1G; break; case IMX6_CPUTYPE_IMX6Q: mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr); memsize = SZ_2G; break; default: return 0; } __udelay(100); mmdc_do_dqs_calibration(); #ifdef DEBUG mmdc_print_calibration_results(); #endif return memsize; } static void setup_uart(void) { int cpu_type = __imx6_cpu_type(); void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; /* mux UART1 TX on PAD_CSI0_DATA10 */ switch (cpu_type) { case IMX6_CPUTYPE_IMX6S: case IMX6_CPUTYPE_IMX6DL: writel(0x00000003, iomuxbase + 0x4c); writel(0x0001b0b1, iomuxbase + 0x360); writel(0x00000000, iomuxbase + 0x8fc); break; case IMX6_CPUTYPE_IMX6Q: writel(0x00000003, iomuxbase + 0x280); writel(0x0001b0b1, iomuxbase + 0x650); writel(0x00000001, iomuxbase + 0x920); break; default: return; } imx6_ungate_all_peripherals(); imx6_uart_setup((void *)MX6_UART1_BASE_ADDR); pbl_set_putc(imx_uart_putc, (void *)MX6_UART1_BASE_ADDR); pr_debug("\n"); } static void wandboard_init(void) { unsigned long sdram_size; setup_uart(); if (get_pc() > 0x10000000) return; sdram_size = wandboard_dram_init(); pr_debug("SDRAM init finished. SDRAM size 0x%08lx\n", sdram_size); imx6_esdhc_start_image(2); pr_info("Loading image from SPI flash\n"); imx6_spi_start_image(0); } extern char __dtb_z_imx6dl_wandboard_start[]; extern char __dtb_z_imx6q_wandboard_start[]; static noinline void wandboard_start(void) { int cpu_type = __imx6_cpu_type(); void *dtb; wandboard_init(); switch (cpu_type) { case IMX6_CPUTYPE_IMX6S: case IMX6_CPUTYPE_IMX6DL: dtb = __dtb_z_imx6dl_wandboard_start; break; case IMX6_CPUTYPE_IMX6Q: dtb = __dtb_z_imx6q_wandboard_start; break; default: hang(); } imx6q_barebox_entry(dtb); } ENTRY_FUNCTION(start_imx6_wandboard, r0, r1, r2) { imx6_cpu_lowlevel_init(); arm_setup_stack(0x00920000); relocate_to_current_adr(); setup_c(); barrier(); wandboard_start(); }