/*
 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/ {
	chosen {
		environment-nand {
			compatible = "barebox,environment";
			device-path = &gpmi, "partname:barebox-environment";
			status = "disabled";
		};

		environment-spinor {
			compatible = "barebox,environment";
			device-path = &flash, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd {
			compatible = "barebox,environment";
			device-path = &usdhc3, "partname:barebox-environment";
			status = "disabled";
		};
	};
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "disabled";
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 24 0>;

	flash: m25p80@0 {
		compatible = "m25p80";
		spi-max-frequency = <20000000>;
		reg = <0>;

		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "barebox";
			reg = <0x0 0x80000>;
		};

		partition@1 {
			label = "barebox-environment";
			reg = <0x80000 0x10000>;
		};

	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-handle = <&ethphy>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 23 0>;
	status = "disabled";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@3 {
			reg = <3>;

			txc-skew-ps = <1680>;
			rxc-skew-ps = <1860>;
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0x400000>;
	};

	partition@1 {
		label = "barebox-environment";
		reg = <0x400000 0x20000>;
	};

	partition@2 {
		label = "oftree";
		reg = <0x420000 0x20000>;
	};

	partition@3 {
		label = "kernel";
		reg = <0x440000 0x800000>;
	};

	partition@4 {
		label = "root";
		reg = <0xC40000 0x0>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	ecspi3 {
		pinctrl_ecspi3: ecspi3grp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
			>;
		};
	};

	enet {
		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
			>;
		};
	};

	gpmi-nand {
		pinctrl_gpmi_nand: gpmi-nand {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
				MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
				MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
				MX6QDL_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
				MX6QDL_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
				MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
				MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
				MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
				MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
				MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
				MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
				MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
				MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
				MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
				MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
				MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
			>;
		};
	};

	hog {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
			>;
		};
	};

	uart4 {
		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
			>;
		};
	};

	usdhc2 {
		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
			>;
		};
	};

	usdhc3 {
		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
			>;
		};
	};
};

&ocotp {
	barebox,provide-mac-address = <&fec 0x620>;
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "disabled";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio1 4 0>;
	wp-gpios = <&gpio1 2 0>;
	status = "disabled";
};

&usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
        cd-gpios = <&gpio1 27 0>;
        wp-gpios = <&gpio1 29 0>;
        status = "disabled";

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0x80000>;
	};
	partition@1 {
		label = "barebox-environment";
		reg = <0x80000 0x80000>;
	};
};